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0008 #ifndef _MSCC_OCELOT_ANA_H_
0009 #define _MSCC_OCELOT_ANA_H_
0010
0011 #define ANA_ANAGEFIL_B_DOM_EN BIT(22)
0012 #define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
0013 #define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
0014 #define ANA_ANAGEFIL_PID_EN BIT(19)
0015 #define ANA_ANAGEFIL_PID_VAL(x) (((x) << 14) & GENMASK(18, 14))
0016 #define ANA_ANAGEFIL_PID_VAL_M GENMASK(18, 14)
0017 #define ANA_ANAGEFIL_PID_VAL_X(x) (((x) & GENMASK(18, 14)) >> 14)
0018 #define ANA_ANAGEFIL_VID_EN BIT(13)
0019 #define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0))
0020 #define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0)
0021
0022 #define ANA_STORMLIMIT_CFG_RSZ 0x4
0023
0024 #define ANA_STORMLIMIT_CFG_STORM_RATE(x) (((x) << 3) & GENMASK(6, 3))
0025 #define ANA_STORMLIMIT_CFG_STORM_RATE_M GENMASK(6, 3)
0026 #define ANA_STORMLIMIT_CFG_STORM_RATE_X(x) (((x) & GENMASK(6, 3)) >> 3)
0027 #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
0028 #define ANA_STORMLIMIT_CFG_STORM_MODE(x) ((x) & GENMASK(1, 0))
0029 #define ANA_STORMLIMIT_CFG_STORM_MODE_M GENMASK(1, 0)
0030
0031 #define ANA_AUTOAGE_AGE_FAST BIT(21)
0032 #define ANA_AUTOAGE_AGE_PERIOD(x) (((x) << 1) & GENMASK(20, 1))
0033 #define ANA_AUTOAGE_AGE_PERIOD_M GENMASK(20, 1)
0034 #define ANA_AUTOAGE_AGE_PERIOD_X(x) (((x) & GENMASK(20, 1)) >> 1)
0035 #define ANA_AUTOAGE_AUTOAGE_LOCKED BIT(0)
0036
0037 #define ANA_MACTOPTIONS_REDUCED_TABLE BIT(1)
0038 #define ANA_MACTOPTIONS_SHADOW BIT(0)
0039
0040 #define ANA_AGENCTRL_FID_MASK(x) (((x) << 12) & GENMASK(23, 12))
0041 #define ANA_AGENCTRL_FID_MASK_M GENMASK(23, 12)
0042 #define ANA_AGENCTRL_FID_MASK_X(x) (((x) & GENMASK(23, 12)) >> 12)
0043 #define ANA_AGENCTRL_IGNORE_DMAC_FLAGS BIT(11)
0044 #define ANA_AGENCTRL_IGNORE_SMAC_FLAGS BIT(10)
0045 #define ANA_AGENCTRL_FLOOD_SPECIAL BIT(9)
0046 #define ANA_AGENCTRL_FLOOD_IGNORE_VLAN BIT(8)
0047 #define ANA_AGENCTRL_MIRROR_CPU BIT(7)
0048 #define ANA_AGENCTRL_LEARN_CPU_COPY BIT(6)
0049 #define ANA_AGENCTRL_LEARN_FWD_KILL BIT(5)
0050 #define ANA_AGENCTRL_LEARN_IGNORE_VLAN BIT(4)
0051 #define ANA_AGENCTRL_CPU_CPU_KILL_ENA BIT(3)
0052 #define ANA_AGENCTRL_GREEN_COUNT_MODE BIT(2)
0053 #define ANA_AGENCTRL_YELLOW_COUNT_MODE BIT(1)
0054 #define ANA_AGENCTRL_RED_COUNT_MODE BIT(0)
0055
0056 #define ANA_FLOODING_RSZ 0x4
0057
0058 #define ANA_FLOODING_FLD_UNICAST(x) (((x) << 12) & GENMASK(17, 12))
0059 #define ANA_FLOODING_FLD_UNICAST_M GENMASK(17, 12)
0060 #define ANA_FLOODING_FLD_UNICAST_X(x) (((x) & GENMASK(17, 12)) >> 12)
0061 #define ANA_FLOODING_FLD_BROADCAST(x) (((x) << 6) & GENMASK(11, 6))
0062 #define ANA_FLOODING_FLD_BROADCAST_M GENMASK(11, 6)
0063 #define ANA_FLOODING_FLD_BROADCAST_X(x) (((x) & GENMASK(11, 6)) >> 6)
0064 #define ANA_FLOODING_FLD_MULTICAST(x) ((x) & GENMASK(5, 0))
0065 #define ANA_FLOODING_FLD_MULTICAST_M GENMASK(5, 0)
0066
0067 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL(x) (((x) << 18) & GENMASK(23, 18))
0068 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_M GENMASK(23, 18)
0069 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_X(x) (((x) & GENMASK(23, 18)) >> 18)
0070 #define ANA_FLOODING_IPMC_FLD_MC4_DATA(x) (((x) << 12) & GENMASK(17, 12))
0071 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_M GENMASK(17, 12)
0072 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_X(x) (((x) & GENMASK(17, 12)) >> 12)
0073 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL(x) (((x) << 6) & GENMASK(11, 6))
0074 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_M GENMASK(11, 6)
0075 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_X(x) (((x) & GENMASK(11, 6)) >> 6)
0076 #define ANA_FLOODING_IPMC_FLD_MC6_DATA(x) ((x) & GENMASK(5, 0))
0077 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_M GENMASK(5, 0)
0078
0079 #define ANA_SFLOW_CFG_RSZ 0x4
0080
0081 #define ANA_SFLOW_CFG_SF_RATE(x) (((x) << 2) & GENMASK(13, 2))
0082 #define ANA_SFLOW_CFG_SF_RATE_M GENMASK(13, 2)
0083 #define ANA_SFLOW_CFG_SF_RATE_X(x) (((x) & GENMASK(13, 2)) >> 2)
0084 #define ANA_SFLOW_CFG_SF_SAMPLE_RX BIT(1)
0085 #define ANA_SFLOW_CFG_SF_SAMPLE_TX BIT(0)
0086
0087 #define ANA_PORT_MODE_RSZ 0x4
0088
0089 #define ANA_PORT_MODE_REDTAG_PARSE_CFG BIT(3)
0090 #define ANA_PORT_MODE_VLAN_PARSE_CFG(x) (((x) << 1) & GENMASK(2, 1))
0091 #define ANA_PORT_MODE_VLAN_PARSE_CFG_M GENMASK(2, 1)
0092 #define ANA_PORT_MODE_VLAN_PARSE_CFG_X(x) (((x) & GENMASK(2, 1)) >> 1)
0093 #define ANA_PORT_MODE_L3_PARSE_CFG BIT(0)
0094
0095 #define ANA_CUT_THRU_CFG_RSZ 0x4
0096
0097 #define ANA_PGID_PGID_RSZ 0x4
0098
0099 #define ANA_PGID_PGID_PGID(x) ((x) & GENMASK(11, 0))
0100 #define ANA_PGID_PGID_PGID_M GENMASK(11, 0)
0101 #define ANA_PGID_PGID_CPUQ_DST_PGID(x) (((x) << 27) & GENMASK(29, 27))
0102 #define ANA_PGID_PGID_CPUQ_DST_PGID_M GENMASK(29, 27)
0103 #define ANA_PGID_PGID_CPUQ_DST_PGID_X(x) (((x) & GENMASK(29, 27)) >> 27)
0104
0105 #define ANA_TABLES_MACHDATA_VID(x) (((x) << 16) & GENMASK(28, 16))
0106 #define ANA_TABLES_MACHDATA_VID_M GENMASK(28, 16)
0107 #define ANA_TABLES_MACHDATA_VID_X(x) (((x) & GENMASK(28, 16)) >> 16)
0108 #define ANA_TABLES_MACHDATA_MACHDATA(x) ((x) & GENMASK(15, 0))
0109 #define ANA_TABLES_MACHDATA_MACHDATA_M GENMASK(15, 0)
0110
0111 #define ANA_TABLES_STREAMDATA_SSID_VALID BIT(16)
0112 #define ANA_TABLES_STREAMDATA_SSID(x) (((x) << 9) & GENMASK(15, 9))
0113 #define ANA_TABLES_STREAMDATA_SSID_M GENMASK(15, 9)
0114 #define ANA_TABLES_STREAMDATA_SSID_X(x) (((x) & GENMASK(15, 9)) >> 9)
0115 #define ANA_TABLES_STREAMDATA_SFID_VALID BIT(8)
0116 #define ANA_TABLES_STREAMDATA_SFID(x) ((x) & GENMASK(7, 0))
0117 #define ANA_TABLES_STREAMDATA_SFID_M GENMASK(7, 0)
0118
0119 #define ANA_TABLES_MACACCESS_MAC_CPU_COPY BIT(15)
0120 #define ANA_TABLES_MACACCESS_SRC_KILL BIT(14)
0121 #define ANA_TABLES_MACACCESS_IGNORE_VLAN BIT(13)
0122 #define ANA_TABLES_MACACCESS_AGED_FLAG BIT(12)
0123 #define ANA_TABLES_MACACCESS_VALID BIT(11)
0124 #define ANA_TABLES_MACACCESS_ENTRYTYPE(x) (((x) << 9) & GENMASK(10, 9))
0125 #define ANA_TABLES_MACACCESS_ENTRYTYPE_M GENMASK(10, 9)
0126 #define ANA_TABLES_MACACCESS_ENTRYTYPE_X(x) (((x) & GENMASK(10, 9)) >> 9)
0127 #define ANA_TABLES_MACACCESS_DEST_IDX(x) (((x) << 3) & GENMASK(8, 3))
0128 #define ANA_TABLES_MACACCESS_DEST_IDX_M GENMASK(8, 3)
0129 #define ANA_TABLES_MACACCESS_DEST_IDX_X(x) (((x) & GENMASK(8, 3)) >> 3)
0130 #define ANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) ((x) & GENMASK(2, 0))
0131 #define ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M GENMASK(2, 0)
0132 #define MACACCESS_CMD_IDLE 0
0133 #define MACACCESS_CMD_LEARN 1
0134 #define MACACCESS_CMD_FORGET 2
0135 #define MACACCESS_CMD_AGE 3
0136 #define MACACCESS_CMD_GET_NEXT 4
0137 #define MACACCESS_CMD_INIT 5
0138 #define MACACCESS_CMD_READ 6
0139 #define MACACCESS_CMD_WRITE 7
0140
0141 #define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(x) (((x) << 2) & GENMASK(13, 2))
0142 #define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK_M GENMASK(13, 2)
0143 #define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK_X(x) (((x) & GENMASK(13, 2)) >> 2)
0144 #define ANA_TABLES_VLANACCESS_VLAN_TBL_CMD(x) ((x) & GENMASK(1, 0))
0145 #define ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M GENMASK(1, 0)
0146 #define ANA_TABLES_VLANACCESS_CMD_IDLE 0x0
0147 #define ANA_TABLES_VLANACCESS_CMD_WRITE 0x2
0148 #define ANA_TABLES_VLANACCESS_CMD_INIT 0x3
0149
0150 #define ANA_TABLES_VLANTIDX_VLAN_SEC_FWD_ENA BIT(17)
0151 #define ANA_TABLES_VLANTIDX_VLAN_FLOOD_DIS BIT(16)
0152 #define ANA_TABLES_VLANTIDX_VLAN_PRIV_VLAN BIT(15)
0153 #define ANA_TABLES_VLANTIDX_VLAN_LEARN_DISABLED BIT(14)
0154 #define ANA_TABLES_VLANTIDX_VLAN_MIRROR BIT(13)
0155 #define ANA_TABLES_VLANTIDX_VLAN_SRC_CHK BIT(12)
0156 #define ANA_TABLES_VLANTIDX_V_INDEX(x) ((x) & GENMASK(11, 0))
0157 #define ANA_TABLES_VLANTIDX_V_INDEX_M GENMASK(11, 0)
0158
0159 #define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK(x) (((x) << 2) & GENMASK(8, 2))
0160 #define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK_M GENMASK(8, 2)
0161 #define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK_X(x) (((x) & GENMASK(8, 2)) >> 2)
0162 #define ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD(x) ((x) & GENMASK(1, 0))
0163 #define ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD_M GENMASK(1, 0)
0164
0165 #define ANA_TABLES_ISDXTIDX_ISDX_SDLBI(x) (((x) << 21) & GENMASK(28, 21))
0166 #define ANA_TABLES_ISDXTIDX_ISDX_SDLBI_M GENMASK(28, 21)
0167 #define ANA_TABLES_ISDXTIDX_ISDX_SDLBI_X(x) (((x) & GENMASK(28, 21)) >> 21)
0168 #define ANA_TABLES_ISDXTIDX_ISDX_MSTI(x) (((x) << 15) & GENMASK(20, 15))
0169 #define ANA_TABLES_ISDXTIDX_ISDX_MSTI_M GENMASK(20, 15)
0170 #define ANA_TABLES_ISDXTIDX_ISDX_MSTI_X(x) (((x) & GENMASK(20, 15)) >> 15)
0171 #define ANA_TABLES_ISDXTIDX_ISDX_ES0_KEY_ENA BIT(14)
0172 #define ANA_TABLES_ISDXTIDX_ISDX_FORCE_ENA BIT(10)
0173 #define ANA_TABLES_ISDXTIDX_ISDX_INDEX(x) ((x) & GENMASK(7, 0))
0174 #define ANA_TABLES_ISDXTIDX_ISDX_INDEX_M GENMASK(7, 0)
0175
0176 #define ANA_TABLES_ENTRYLIM_RSZ 0x4
0177
0178 #define ANA_TABLES_ENTRYLIM_ENTRYLIM(x) (((x) << 14) & GENMASK(17, 14))
0179 #define ANA_TABLES_ENTRYLIM_ENTRYLIM_M GENMASK(17, 14)
0180 #define ANA_TABLES_ENTRYLIM_ENTRYLIM_X(x) (((x) & GENMASK(17, 14)) >> 14)
0181 #define ANA_TABLES_ENTRYLIM_ENTRYSTAT(x) ((x) & GENMASK(13, 0))
0182 #define ANA_TABLES_ENTRYLIM_ENTRYSTAT_M GENMASK(13, 0)
0183
0184 #define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM(x) (((x) << 4) & GENMASK(31, 4))
0185 #define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM_M GENMASK(31, 4)
0186 #define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM_X(x) (((x) & GENMASK(31, 4)) >> 4)
0187 #define ANA_TABLES_STREAMACCESS_SEQ_GEN_REC_ENA BIT(3)
0188 #define ANA_TABLES_STREAMACCESS_GEN_REC_TYPE BIT(2)
0189 #define ANA_TABLES_STREAMACCESS_STREAM_TBL_CMD(x) ((x) & GENMASK(1, 0))
0190 #define ANA_TABLES_STREAMACCESS_STREAM_TBL_CMD_M GENMASK(1, 0)
0191
0192 #define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS(x) (((x) << 30) & GENMASK(31, 30))
0193 #define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS_M GENMASK(31, 30)
0194 #define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS_X(x) (((x) & GENMASK(31, 30)) >> 30)
0195 #define ANA_TABLES_STREAMTIDX_S_INDEX(x) (((x) << 16) & GENMASK(22, 16))
0196 #define ANA_TABLES_STREAMTIDX_S_INDEX_M GENMASK(22, 16)
0197 #define ANA_TABLES_STREAMTIDX_S_INDEX_X(x) (((x) & GENMASK(22, 16)) >> 16)
0198 #define ANA_TABLES_STREAMTIDX_FORCE_SF_BEHAVIOUR BIT(14)
0199 #define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN(x) (((x) << 8) & GENMASK(13, 8))
0200 #define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN_M GENMASK(13, 8)
0201 #define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN_X(x) (((x) & GENMASK(13, 8)) >> 8)
0202 #define ANA_TABLES_STREAMTIDX_RESET_ON_ROGUE BIT(7)
0203 #define ANA_TABLES_STREAMTIDX_REDTAG_POP BIT(6)
0204 #define ANA_TABLES_STREAMTIDX_STREAM_SPLIT BIT(5)
0205 #define ANA_TABLES_STREAMTIDX_SEQ_SPACE_LOG2(x) ((x) & GENMASK(4, 0))
0206 #define ANA_TABLES_STREAMTIDX_SEQ_SPACE_LOG2_M GENMASK(4, 0)
0207
0208 #define ANA_TABLES_SEQ_MASK_SPLIT_MASK(x) (((x) << 16) & GENMASK(22, 16))
0209 #define ANA_TABLES_SEQ_MASK_SPLIT_MASK_M GENMASK(22, 16)
0210 #define ANA_TABLES_SEQ_MASK_SPLIT_MASK_X(x) (((x) & GENMASK(22, 16)) >> 16)
0211 #define ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK(x) ((x) & GENMASK(6, 0))
0212 #define ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK_M GENMASK(6, 0)
0213
0214 #define ANA_TABLES_SFID_MASK_IGR_PORT_MASK(x) (((x) << 1) & GENMASK(7, 1))
0215 #define ANA_TABLES_SFID_MASK_IGR_PORT_MASK_M GENMASK(7, 1)
0216 #define ANA_TABLES_SFID_MASK_IGR_PORT_MASK_X(x) (((x) & GENMASK(7, 1)) >> 1)
0217 #define ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA BIT(0)
0218
0219 #define ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA BIT(22)
0220 #define ANA_TABLES_SFIDACCESS_IGR_PRIO(x) (((x) << 19) & GENMASK(21, 19))
0221 #define ANA_TABLES_SFIDACCESS_IGR_PRIO_M GENMASK(21, 19)
0222 #define ANA_TABLES_SFIDACCESS_IGR_PRIO_X(x) (((x) & GENMASK(21, 19)) >> 19)
0223 #define ANA_TABLES_SFIDACCESS_FORCE_BLOCK BIT(18)
0224 #define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(x) (((x) << 2) & GENMASK(17, 2))
0225 #define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN_M GENMASK(17, 2)
0226 #define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN_X(x) (((x) & GENMASK(17, 2)) >> 2)
0227 #define ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(x) ((x) & GENMASK(1, 0))
0228 #define ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M GENMASK(1, 0)
0229
0230 #define SFIDACCESS_CMD_IDLE 0
0231 #define SFIDACCESS_CMD_READ 1
0232 #define SFIDACCESS_CMD_WRITE 2
0233 #define SFIDACCESS_CMD_INIT 3
0234
0235 #define ANA_TABLES_SFIDTIDX_SGID_VALID BIT(26)
0236 #define ANA_TABLES_SFIDTIDX_SGID(x) (((x) << 18) & GENMASK(25, 18))
0237 #define ANA_TABLES_SFIDTIDX_SGID_M GENMASK(25, 18)
0238 #define ANA_TABLES_SFIDTIDX_SGID_X(x) (((x) & GENMASK(25, 18)) >> 18)
0239 #define ANA_TABLES_SFIDTIDX_POL_ENA BIT(17)
0240 #define ANA_TABLES_SFIDTIDX_POL_IDX(x) (((x) << 8) & GENMASK(16, 8))
0241 #define ANA_TABLES_SFIDTIDX_POL_IDX_M GENMASK(16, 8)
0242 #define ANA_TABLES_SFIDTIDX_POL_IDX_X(x) (((x) & GENMASK(16, 8)) >> 8)
0243 #define ANA_TABLES_SFIDTIDX_SFID_INDEX(x) ((x) & GENMASK(7, 0))
0244 #define ANA_TABLES_SFIDTIDX_SFID_INDEX_M GENMASK(7, 0)
0245
0246 #define ANA_MSTI_STATE_RSZ 0x4
0247
0248 #define ANA_OAM_UPM_LM_CNT_RSZ 0x4
0249
0250 #define ANA_SG_ACCESS_CTRL_SGID(x) ((x) & GENMASK(7, 0))
0251 #define ANA_SG_ACCESS_CTRL_SGID_M GENMASK(7, 0)
0252 #define ANA_SG_ACCESS_CTRL_CONFIG_CHANGE BIT(28)
0253
0254 #define ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
0255 #define ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0)
0256 #define ANA_SG_CONFIG_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(18, 16))
0257 #define ANA_SG_CONFIG_REG_3_LIST_LENGTH_M GENMASK(18, 16)
0258 #define ANA_SG_CONFIG_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(18, 16)) >> 16)
0259 #define ANA_SG_CONFIG_REG_3_GATE_ENABLE BIT(20)
0260 #define ANA_SG_CONFIG_REG_3_INIT_IPS(x) (((x) << 21) & GENMASK(24, 21))
0261 #define ANA_SG_CONFIG_REG_3_INIT_IPS_M GENMASK(24, 21)
0262 #define ANA_SG_CONFIG_REG_3_INIT_IPS_X(x) (((x) & GENMASK(24, 21)) >> 21)
0263 #define ANA_SG_CONFIG_REG_3_IPV_VALID BIT(24)
0264 #define ANA_SG_CONFIG_REG_3_IPV_INVALID(x) (((x) << 24) & GENMASK(24, 24))
0265 #define ANA_SG_CONFIG_REG_3_INIT_IPV(x) (((x) << 21) & GENMASK(23, 21))
0266 #define ANA_SG_CONFIG_REG_3_INIT_IPV_M GENMASK(23, 21)
0267 #define ANA_SG_CONFIG_REG_3_INIT_IPV_X(x) (((x) & GENMASK(23, 21)) >> 21)
0268 #define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE BIT(25)
0269
0270 #define ANA_SG_GCL_GS_CONFIG_RSZ 0x4
0271
0272 #define ANA_SG_GCL_GS_CONFIG_IPS(x) ((x) & GENMASK(3, 0))
0273 #define ANA_SG_GCL_GS_CONFIG_IPS_M GENMASK(3, 0)
0274 #define ANA_SG_GCL_GS_CONFIG_GATE_STATE BIT(4)
0275
0276 #define ANA_SG_GCL_TI_CONFIG_RSZ 0x4
0277
0278 #define ANA_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
0279 #define ANA_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_M GENMASK(15, 0)
0280 #define ANA_SG_STATUS_REG_3_GATE_STATE BIT(16)
0281 #define ANA_SG_STATUS_REG_3_IPS(x) (((x) << 20) & GENMASK(23, 20))
0282 #define ANA_SG_STATUS_REG_3_IPS_M GENMASK(23, 20)
0283 #define ANA_SG_STATUS_REG_3_IPS_X(x) (((x) & GENMASK(23, 20)) >> 20)
0284 #define ANA_SG_STATUS_REG_3_CONFIG_PENDING BIT(24)
0285
0286 #define ANA_PORT_VLAN_CFG_GSZ 0x100
0287
0288 #define ANA_PORT_VLAN_CFG_VLAN_VID_AS_ISDX BIT(21)
0289 #define ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA BIT(20)
0290 #define ANA_PORT_VLAN_CFG_VLAN_POP_CNT(x) (((x) << 18) & GENMASK(19, 18))
0291 #define ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M GENMASK(19, 18)
0292 #define ANA_PORT_VLAN_CFG_VLAN_POP_CNT_X(x) (((x) & GENMASK(19, 18)) >> 18)
0293 #define ANA_PORT_VLAN_CFG_VLAN_INNER_TAG_ENA BIT(17)
0294 #define ANA_PORT_VLAN_CFG_VLAN_TAG_TYPE BIT(16)
0295 #define ANA_PORT_VLAN_CFG_VLAN_DEI BIT(15)
0296 #define ANA_PORT_VLAN_CFG_VLAN_PCP(x) (((x) << 12) & GENMASK(14, 12))
0297 #define ANA_PORT_VLAN_CFG_VLAN_PCP_M GENMASK(14, 12)
0298 #define ANA_PORT_VLAN_CFG_VLAN_PCP_X(x) (((x) & GENMASK(14, 12)) >> 12)
0299 #define ANA_PORT_VLAN_CFG_VLAN_VID(x) ((x) & GENMASK(11, 0))
0300 #define ANA_PORT_VLAN_CFG_VLAN_VID_M GENMASK(11, 0)
0301
0302 #define ANA_PORT_DROP_CFG_GSZ 0x100
0303
0304 #define ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA BIT(6)
0305 #define ANA_PORT_DROP_CFG_DROP_S_TAGGED_ENA BIT(5)
0306 #define ANA_PORT_DROP_CFG_DROP_C_TAGGED_ENA BIT(4)
0307 #define ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA BIT(3)
0308 #define ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA BIT(2)
0309 #define ANA_PORT_DROP_CFG_DROP_NULL_MAC_ENA BIT(1)
0310 #define ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA BIT(0)
0311
0312 #define ANA_PORT_QOS_CFG_GSZ 0x100
0313
0314 #define ANA_PORT_QOS_CFG_DP_DEFAULT_VAL BIT(8)
0315 #define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL(x) (((x) << 5) & GENMASK(7, 5))
0316 #define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_M GENMASK(7, 5)
0317 #define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(x) (((x) & GENMASK(7, 5)) >> 5)
0318 #define ANA_PORT_QOS_CFG_QOS_DSCP_ENA BIT(4)
0319 #define ANA_PORT_QOS_CFG_QOS_PCP_ENA BIT(3)
0320 #define ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA BIT(2)
0321 #define ANA_PORT_QOS_CFG_DSCP_REWR_CFG(x) ((x) & GENMASK(1, 0))
0322 #define ANA_PORT_QOS_CFG_DSCP_REWR_CFG_M GENMASK(1, 0)
0323
0324 #define ANA_PORT_VCAP_CFG_GSZ 0x100
0325
0326 #define ANA_PORT_VCAP_CFG_S1_ENA BIT(14)
0327 #define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA(x) (((x) << 11) & GENMASK(13, 11))
0328 #define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_M GENMASK(13, 11)
0329 #define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_X(x) (((x) & GENMASK(13, 11)) >> 11)
0330 #define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA(x) (((x) << 8) & GENMASK(10, 8))
0331 #define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA_M GENMASK(10, 8)
0332 #define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA_X(x) (((x) & GENMASK(10, 8)) >> 8)
0333 #define ANA_PORT_VCAP_CFG_PAG_VAL(x) ((x) & GENMASK(7, 0))
0334 #define ANA_PORT_VCAP_CFG_PAG_VAL_M GENMASK(7, 0)
0335
0336 #define ANA_PORT_VCAP_S1_KEY_CFG_GSZ 0x100
0337 #define ANA_PORT_VCAP_S1_KEY_CFG_RSZ 0x4
0338
0339 #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG(x) (((x) << 4) & GENMASK(6, 4))
0340 #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_M GENMASK(6, 4)
0341 #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_X(x) (((x) & GENMASK(6, 4)) >> 4)
0342 #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG(x) (((x) << 2) & GENMASK(3, 2))
0343 #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG_M GENMASK(3, 2)
0344 #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG_X(x) (((x) & GENMASK(3, 2)) >> 2)
0345 #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_OTHER_CFG(x) ((x) & GENMASK(1, 0))
0346 #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_OTHER_CFG_M GENMASK(1, 0)
0347
0348 #define ANA_PORT_VCAP_S2_CFG_GSZ 0x100
0349
0350 #define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA(x) (((x) << 17) & GENMASK(18, 17))
0351 #define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA_M GENMASK(18, 17)
0352 #define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA_X(x) (((x) & GENMASK(18, 17)) >> 17)
0353 #define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA(x) (((x) << 15) & GENMASK(16, 15))
0354 #define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA_M GENMASK(16, 15)
0355 #define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA_X(x) (((x) & GENMASK(16, 15)) >> 15)
0356 #define ANA_PORT_VCAP_S2_CFG_S2_ENA BIT(14)
0357 #define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS(x) (((x) << 12) & GENMASK(13, 12))
0358 #define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_M GENMASK(13, 12)
0359 #define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_X(x) (((x) & GENMASK(13, 12)) >> 12)
0360 #define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS(x) (((x) << 10) & GENMASK(11, 10))
0361 #define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_M GENMASK(11, 10)
0362 #define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_X(x) (((x) & GENMASK(11, 10)) >> 10)
0363 #define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS(x) (((x) << 8) & GENMASK(9, 8))
0364 #define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_M GENMASK(9, 8)
0365 #define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_X(x) (((x) & GENMASK(9, 8)) >> 8)
0366 #define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS(x) (((x) << 6) & GENMASK(7, 6))
0367 #define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_M GENMASK(7, 6)
0368 #define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_X(x) (((x) & GENMASK(7, 6)) >> 6)
0369 #define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(x) (((x) << 2) & GENMASK(5, 2))
0370 #define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG_M GENMASK(5, 2)
0371 #define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG_X(x) (((x) & GENMASK(5, 2)) >> 2)
0372 #define ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS(x) ((x) & GENMASK(1, 0))
0373 #define ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS_M GENMASK(1, 0)
0374
0375 #define ANA_PORT_PCP_DEI_MAP_GSZ 0x100
0376 #define ANA_PORT_PCP_DEI_MAP_RSZ 0x4
0377
0378 #define ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL BIT(3)
0379 #define ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL(x) ((x) & GENMASK(2, 0))
0380 #define ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL_M GENMASK(2, 0)
0381
0382 #define ANA_PORT_CPU_FWD_CFG_GSZ 0x100
0383
0384 #define ANA_PORT_CPU_FWD_CFG_CPU_VRAP_REDIR_ENA BIT(7)
0385 #define ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA BIT(6)
0386 #define ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA BIT(5)
0387 #define ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA BIT(4)
0388 #define ANA_PORT_CPU_FWD_CFG_CPU_SRC_COPY_ENA BIT(3)
0389 #define ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_DROP_ENA BIT(2)
0390 #define ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_REDIR_ENA BIT(1)
0391 #define ANA_PORT_CPU_FWD_CFG_CPU_OAM_ENA BIT(0)
0392
0393 #define ANA_PORT_CPU_FWD_BPDU_CFG_GSZ 0x100
0394
0395 #define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16))
0396 #define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA_M GENMASK(31, 16)
0397 #define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16)
0398 #define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(x) ((x) & GENMASK(15, 0))
0399 #define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA_M GENMASK(15, 0)
0400
0401 #define ANA_PORT_CPU_FWD_GARP_CFG_GSZ 0x100
0402
0403 #define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16))
0404 #define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA_M GENMASK(31, 16)
0405 #define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16)
0406 #define ANA_PORT_CPU_FWD_GARP_CFG_GARP_REDIR_ENA(x) ((x) & GENMASK(15, 0))
0407 #define ANA_PORT_CPU_FWD_GARP_CFG_GARP_REDIR_ENA_M GENMASK(15, 0)
0408
0409 #define ANA_PORT_CPU_FWD_CCM_CFG_GSZ 0x100
0410
0411 #define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16))
0412 #define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA_M GENMASK(31, 16)
0413 #define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16)
0414 #define ANA_PORT_CPU_FWD_CCM_CFG_CCM_REDIR_ENA(x) ((x) & GENMASK(15, 0))
0415 #define ANA_PORT_CPU_FWD_CCM_CFG_CCM_REDIR_ENA_M GENMASK(15, 0)
0416
0417 #define ANA_PORT_PORT_CFG_GSZ 0x100
0418
0419 #define ANA_PORT_PORT_CFG_SRC_MIRROR_ENA BIT(15)
0420 #define ANA_PORT_PORT_CFG_LIMIT_DROP BIT(14)
0421 #define ANA_PORT_PORT_CFG_LIMIT_CPU BIT(13)
0422 #define ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_DROP BIT(12)
0423 #define ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_CPU BIT(11)
0424 #define ANA_PORT_PORT_CFG_LEARNDROP BIT(10)
0425 #define ANA_PORT_PORT_CFG_LEARNCPU BIT(9)
0426 #define ANA_PORT_PORT_CFG_LEARNAUTO BIT(8)
0427 #define ANA_PORT_PORT_CFG_LEARN_ENA BIT(7)
0428 #define ANA_PORT_PORT_CFG_RECV_ENA BIT(6)
0429 #define ANA_PORT_PORT_CFG_PORTID_VAL(x) (((x) << 2) & GENMASK(5, 2))
0430 #define ANA_PORT_PORT_CFG_PORTID_VAL_M GENMASK(5, 2)
0431 #define ANA_PORT_PORT_CFG_PORTID_VAL_X(x) (((x) & GENMASK(5, 2)) >> 2)
0432 #define ANA_PORT_PORT_CFG_USE_B_DOM_TBL BIT(1)
0433 #define ANA_PORT_PORT_CFG_LSR_MODE BIT(0)
0434
0435 #define ANA_PORT_POL_CFG_GSZ 0x100
0436
0437 #define ANA_PORT_POL_CFG_POL_CPU_REDIR_8021 BIT(19)
0438 #define ANA_PORT_POL_CFG_POL_CPU_REDIR_IP BIT(18)
0439 #define ANA_PORT_POL_CFG_PORT_POL_ENA BIT(17)
0440 #define ANA_PORT_POL_CFG_QUEUE_POL_ENA(x) (((x) << 9) & GENMASK(16, 9))
0441 #define ANA_PORT_POL_CFG_QUEUE_POL_ENA_M GENMASK(16, 9)
0442 #define ANA_PORT_POL_CFG_QUEUE_POL_ENA_X(x) (((x) & GENMASK(16, 9)) >> 9)
0443 #define ANA_PORT_POL_CFG_POL_ORDER(x) ((x) & GENMASK(8, 0))
0444 #define ANA_PORT_POL_CFG_POL_ORDER_M GENMASK(8, 0)
0445
0446 #define ANA_PORT_PTP_CFG_GSZ 0x100
0447
0448 #define ANA_PORT_PTP_CFG_PTP_BACKPLANE_MODE BIT(0)
0449
0450 #define ANA_PORT_PTP_DLY1_CFG_GSZ 0x100
0451
0452 #define ANA_PORT_PTP_DLY2_CFG_GSZ 0x100
0453
0454 #define ANA_PORT_SFID_CFG_GSZ 0x100
0455 #define ANA_PORT_SFID_CFG_RSZ 0x4
0456
0457 #define ANA_PORT_SFID_CFG_SFID_VALID BIT(8)
0458 #define ANA_PORT_SFID_CFG_SFID(x) ((x) & GENMASK(7, 0))
0459 #define ANA_PORT_SFID_CFG_SFID_M GENMASK(7, 0)
0460
0461 #define ANA_PFC_PFC_CFG_GSZ 0x40
0462
0463 #define ANA_PFC_PFC_CFG_RX_PFC_ENA(x) (((x) << 2) & GENMASK(9, 2))
0464 #define ANA_PFC_PFC_CFG_RX_PFC_ENA_M GENMASK(9, 2)
0465 #define ANA_PFC_PFC_CFG_RX_PFC_ENA_X(x) (((x) & GENMASK(9, 2)) >> 2)
0466 #define ANA_PFC_PFC_CFG_FC_LINK_SPEED(x) ((x) & GENMASK(1, 0))
0467 #define ANA_PFC_PFC_CFG_FC_LINK_SPEED_M GENMASK(1, 0)
0468
0469 #define ANA_PFC_PFC_TIMER_GSZ 0x40
0470 #define ANA_PFC_PFC_TIMER_RSZ 0x4
0471
0472 #define ANA_IPT_OAM_MEP_CFG_GSZ 0x8
0473
0474 #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P(x) (((x) << 6) & GENMASK(10, 6))
0475 #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_M GENMASK(10, 6)
0476 #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_X(x) (((x) & GENMASK(10, 6)) >> 6)
0477 #define ANA_IPT_OAM_MEP_CFG_MEP_IDX(x) (((x) << 1) & GENMASK(5, 1))
0478 #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_M GENMASK(5, 1)
0479 #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_X(x) (((x) & GENMASK(5, 1)) >> 1)
0480 #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_ENA BIT(0)
0481
0482 #define ANA_IPT_IPT_GSZ 0x8
0483
0484 #define ANA_IPT_IPT_IPT_CFG(x) (((x) << 15) & GENMASK(16, 15))
0485 #define ANA_IPT_IPT_IPT_CFG_M GENMASK(16, 15)
0486 #define ANA_IPT_IPT_IPT_CFG_X(x) (((x) & GENMASK(16, 15)) >> 15)
0487 #define ANA_IPT_IPT_ISDX_P(x) (((x) << 7) & GENMASK(14, 7))
0488 #define ANA_IPT_IPT_ISDX_P_M GENMASK(14, 7)
0489 #define ANA_IPT_IPT_ISDX_P_X(x) (((x) & GENMASK(14, 7)) >> 7)
0490 #define ANA_IPT_IPT_PPT_IDX(x) ((x) & GENMASK(6, 0))
0491 #define ANA_IPT_IPT_PPT_IDX_M GENMASK(6, 0)
0492
0493 #define ANA_PPT_PPT_RSZ 0x4
0494
0495 #define ANA_FID_MAP_FID_MAP_RSZ 0x4
0496
0497 #define ANA_FID_MAP_FID_MAP_FID_C_VAL(x) (((x) << 6) & GENMASK(11, 6))
0498 #define ANA_FID_MAP_FID_MAP_FID_C_VAL_M GENMASK(11, 6)
0499 #define ANA_FID_MAP_FID_MAP_FID_C_VAL_X(x) (((x) & GENMASK(11, 6)) >> 6)
0500 #define ANA_FID_MAP_FID_MAP_FID_B_VAL(x) ((x) & GENMASK(5, 0))
0501 #define ANA_FID_MAP_FID_MAP_FID_B_VAL_M GENMASK(5, 0)
0502
0503 #define ANA_AGGR_CFG_AC_RND_ENA BIT(7)
0504 #define ANA_AGGR_CFG_AC_DMAC_ENA BIT(6)
0505 #define ANA_AGGR_CFG_AC_SMAC_ENA BIT(5)
0506 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA BIT(4)
0507 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA BIT(3)
0508 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA BIT(2)
0509 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA BIT(1)
0510 #define ANA_AGGR_CFG_AC_ISDX_ENA BIT(0)
0511
0512 #define ANA_CPUQ_CFG_CPUQ_MLD(x) (((x) << 27) & GENMASK(29, 27))
0513 #define ANA_CPUQ_CFG_CPUQ_MLD_M GENMASK(29, 27)
0514 #define ANA_CPUQ_CFG_CPUQ_MLD_X(x) (((x) & GENMASK(29, 27)) >> 27)
0515 #define ANA_CPUQ_CFG_CPUQ_IGMP(x) (((x) << 24) & GENMASK(26, 24))
0516 #define ANA_CPUQ_CFG_CPUQ_IGMP_M GENMASK(26, 24)
0517 #define ANA_CPUQ_CFG_CPUQ_IGMP_X(x) (((x) & GENMASK(26, 24)) >> 24)
0518 #define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(x) (((x) << 21) & GENMASK(23, 21))
0519 #define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL_M GENMASK(23, 21)
0520 #define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL_X(x) (((x) & GENMASK(23, 21)) >> 21)
0521 #define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(x) (((x) << 18) & GENMASK(20, 18))
0522 #define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE_M GENMASK(20, 18)
0523 #define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE_X(x) (((x) & GENMASK(20, 18)) >> 18)
0524 #define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(x) (((x) << 15) & GENMASK(17, 15))
0525 #define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE_M GENMASK(17, 15)
0526 #define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE_X(x) (((x) & GENMASK(17, 15)) >> 15)
0527 #define ANA_CPUQ_CFG_CPUQ_SRC_COPY(x) (((x) << 12) & GENMASK(14, 12))
0528 #define ANA_CPUQ_CFG_CPUQ_SRC_COPY_M GENMASK(14, 12)
0529 #define ANA_CPUQ_CFG_CPUQ_SRC_COPY_X(x) (((x) & GENMASK(14, 12)) >> 12)
0530 #define ANA_CPUQ_CFG_CPUQ_MAC_COPY(x) (((x) << 9) & GENMASK(11, 9))
0531 #define ANA_CPUQ_CFG_CPUQ_MAC_COPY_M GENMASK(11, 9)
0532 #define ANA_CPUQ_CFG_CPUQ_MAC_COPY_X(x) (((x) & GENMASK(11, 9)) >> 9)
0533 #define ANA_CPUQ_CFG_CPUQ_LRN(x) (((x) << 6) & GENMASK(8, 6))
0534 #define ANA_CPUQ_CFG_CPUQ_LRN_M GENMASK(8, 6)
0535 #define ANA_CPUQ_CFG_CPUQ_LRN_X(x) (((x) & GENMASK(8, 6)) >> 6)
0536 #define ANA_CPUQ_CFG_CPUQ_MIRROR(x) (((x) << 3) & GENMASK(5, 3))
0537 #define ANA_CPUQ_CFG_CPUQ_MIRROR_M GENMASK(5, 3)
0538 #define ANA_CPUQ_CFG_CPUQ_MIRROR_X(x) (((x) & GENMASK(5, 3)) >> 3)
0539 #define ANA_CPUQ_CFG_CPUQ_SFLOW(x) ((x) & GENMASK(2, 0))
0540 #define ANA_CPUQ_CFG_CPUQ_SFLOW_M GENMASK(2, 0)
0541
0542 #define ANA_CPUQ_8021_CFG_RSZ 0x4
0543
0544 #define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(x) (((x) << 6) & GENMASK(8, 6))
0545 #define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_M GENMASK(8, 6)
0546 #define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_X(x) (((x) & GENMASK(8, 6)) >> 6)
0547 #define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(x) (((x) << 3) & GENMASK(5, 3))
0548 #define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL_M GENMASK(5, 3)
0549 #define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL_X(x) (((x) & GENMASK(5, 3)) >> 3)
0550 #define ANA_CPUQ_8021_CFG_CPUQ_CCM_VAL(x) ((x) & GENMASK(2, 0))
0551 #define ANA_CPUQ_8021_CFG_CPUQ_CCM_VAL_M GENMASK(2, 0)
0552
0553 #define ANA_DSCP_CFG_RSZ 0x4
0554
0555 #define ANA_DSCP_CFG_DP_DSCP_VAL BIT(11)
0556 #define ANA_DSCP_CFG_QOS_DSCP_VAL(x) (((x) << 8) & GENMASK(10, 8))
0557 #define ANA_DSCP_CFG_QOS_DSCP_VAL_M GENMASK(10, 8)
0558 #define ANA_DSCP_CFG_QOS_DSCP_VAL_X(x) (((x) & GENMASK(10, 8)) >> 8)
0559 #define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL(x) (((x) << 2) & GENMASK(7, 2))
0560 #define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_M GENMASK(7, 2)
0561 #define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_X(x) (((x) & GENMASK(7, 2)) >> 2)
0562 #define ANA_DSCP_CFG_DSCP_TRUST_ENA BIT(1)
0563 #define ANA_DSCP_CFG_DSCP_REWR_ENA BIT(0)
0564
0565 #define ANA_DSCP_REWR_CFG_RSZ 0x4
0566
0567 #define ANA_VCAP_RNG_TYPE_CFG_RSZ 0x4
0568
0569 #define ANA_VCAP_RNG_VAL_CFG_RSZ 0x4
0570
0571 #define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL(x) (((x) << 16) & GENMASK(31, 16))
0572 #define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL_M GENMASK(31, 16)
0573 #define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL_X(x) (((x) & GENMASK(31, 16)) >> 16)
0574 #define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MAX_VAL(x) ((x) & GENMASK(15, 0))
0575 #define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MAX_VAL_M GENMASK(15, 0)
0576
0577 #define ANA_VRAP_CFG_VRAP_VLAN_AWARE_ENA BIT(12)
0578 #define ANA_VRAP_CFG_VRAP_VID(x) ((x) & GENMASK(11, 0))
0579 #define ANA_VRAP_CFG_VRAP_VID_M GENMASK(11, 0)
0580
0581 #define ANA_DISCARD_CFG_DROP_TAGGING_ISDX0 BIT(3)
0582 #define ANA_DISCARD_CFG_DROP_CTRLPROT_ISDX0 BIT(2)
0583 #define ANA_DISCARD_CFG_DROP_TAGGING_S2_ENA BIT(1)
0584 #define ANA_DISCARD_CFG_DROP_CTRLPROT_S2_ENA BIT(0)
0585
0586 #define ANA_FID_CFG_VID_MC_ENA BIT(0)
0587
0588 #define ANA_POL_PIR_CFG_GSZ 0x20
0589
0590 #define ANA_POL_PIR_CFG_PIR_RATE(x) (((x) << 6) & GENMASK(20, 6))
0591 #define ANA_POL_PIR_CFG_PIR_RATE_M GENMASK(20, 6)
0592 #define ANA_POL_PIR_CFG_PIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6)
0593 #define ANA_POL_PIR_CFG_PIR_BURST(x) ((x) & GENMASK(5, 0))
0594 #define ANA_POL_PIR_CFG_PIR_BURST_M GENMASK(5, 0)
0595
0596 #define ANA_POL_CIR_CFG_GSZ 0x20
0597
0598 #define ANA_POL_CIR_CFG_CIR_RATE(x) (((x) << 6) & GENMASK(20, 6))
0599 #define ANA_POL_CIR_CFG_CIR_RATE_M GENMASK(20, 6)
0600 #define ANA_POL_CIR_CFG_CIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6)
0601 #define ANA_POL_CIR_CFG_CIR_BURST(x) ((x) & GENMASK(5, 0))
0602 #define ANA_POL_CIR_CFG_CIR_BURST_M GENMASK(5, 0)
0603
0604 #define ANA_POL_MODE_CFG_GSZ 0x20
0605
0606 #define ANA_POL_MODE_CFG_IPG_SIZE(x) (((x) << 5) & GENMASK(9, 5))
0607 #define ANA_POL_MODE_CFG_IPG_SIZE_M GENMASK(9, 5)
0608 #define ANA_POL_MODE_CFG_IPG_SIZE_X(x) (((x) & GENMASK(9, 5)) >> 5)
0609 #define ANA_POL_MODE_CFG_FRM_MODE(x) (((x) << 3) & GENMASK(4, 3))
0610 #define ANA_POL_MODE_CFG_FRM_MODE_M GENMASK(4, 3)
0611 #define ANA_POL_MODE_CFG_FRM_MODE_X(x) (((x) & GENMASK(4, 3)) >> 3)
0612 #define ANA_POL_MODE_CFG_DLB_COUPLED BIT(2)
0613 #define ANA_POL_MODE_CFG_CIR_ENA BIT(1)
0614 #define ANA_POL_MODE_CFG_OVERSHOOT_ENA BIT(0)
0615
0616 #define ANA_POL_PIR_STATE_GSZ 0x20
0617
0618 #define ANA_POL_CIR_STATE_GSZ 0x20
0619
0620 #define ANA_POL_STATE_GSZ 0x20
0621
0622 #define ANA_POL_FLOWC_RSZ 0x4
0623
0624 #define ANA_POL_FLOWC_POL_FLOWC BIT(0)
0625
0626 #define ANA_POL_HYST_POL_FC_HYST(x) (((x) << 4) & GENMASK(9, 4))
0627 #define ANA_POL_HYST_POL_FC_HYST_M GENMASK(9, 4)
0628 #define ANA_POL_HYST_POL_FC_HYST_X(x) (((x) & GENMASK(9, 4)) >> 4)
0629 #define ANA_POL_HYST_POL_STOP_HYST(x) ((x) & GENMASK(3, 0))
0630 #define ANA_POL_HYST_POL_STOP_HYST_M GENMASK(3, 0)
0631
0632 #define ANA_POL_MISC_CFG_POL_CLOSE_ALL BIT(1)
0633 #define ANA_POL_MISC_CFG_POL_LEAK_DIS BIT(0)
0634
0635 #endif
