soc/mscc/ocelot.h

0001 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
0002 /* Copyright (c) 2017 Microsemi Corporation
0003  */
0004
0005 #ifndef _SOC_MSCC_OCELOT_H
0006 #define _SOC_MSCC_OCELOT_H
0007
0008 #include <linux/ptp_clock_kernel.h>
0009 #include <linux/net_tstamp.h>
0010 #include <linux/if_vlan.h>
0011 #include <linux/regmap.h>
0012 #include <net/dsa.h>
0013
0014 /* Port Group IDs (PGID) are masks of destination ports.
0015  *
0016  * For L2 forwarding, the switch performs 3 lookups in the PGID table for each
0017  * frame, and forwards the frame to the ports that are present in the logical
0018  * AND of all 3 PGIDs.
0019  *
0020  * These PGID lookups are:
0021  * - In one of PGID[0-63]: for the destination masks. There are 2 paths by
0022  *   which the switch selects a destination PGID:
0023  *     - The {DMAC, VID} is present in the MAC table. In that case, the
0024  *       destination PGID is given by the DEST_IDX field of the MAC table entry
0025  *       that matched.
0026  *     - The {DMAC, VID} is not present in the MAC table (it is unknown). The
0027  *       frame is disseminated as being either unicast, multicast or broadcast,
0028  *       and according to that, the destination PGID is chosen as being the
0029  *       value contained by ANA_FLOODING_FLD_UNICAST,
0030  *       ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST.
0031  *   The destination PGID can be an unicast set: the first PGIDs, 0 to
0032  *   ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from
0033  *   ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to
0034  *   a physical port and has a single bit set in the destination ports mask:
0035  *   that corresponding to the port number itself. In contrast, a multicast
0036  *   PGID will have potentially more than one single bit set in the destination
0037  *   ports mask.
0038  * - In one of PGID[64-79]: for the aggregation mask. The switch classifier
0039  *   dissects each frame and generates a 4-bit Link Aggregation Code which is
0040  *   used for this second PGID table lookup. The goal of link aggregation is to
0041  *   hash multiple flows within the same LAG on to different destination ports.
0042  *   The first lookup will result in a PGID with all the LAG members present in
0043  *   the destination ports mask, and the second lookup, by Link Aggregation
0044  *   Code, will ensure that each flow gets forwarded only to a single port out
0045  *   of that mask (there are no duplicates).
0046  * - In one of PGID[80-90]: for the source mask. The third time, the PGID table
0047  *   is indexed with the ingress port (plus 80). These PGIDs answer the
0048  *   question "is port i allowed to forward traffic to port j?" If yes, then
0049  *   BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used
0050  *   to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge.
0051  */
0052
0053 /* Reserve some destination PGIDs at the end of the range:
0054  * PGID_BLACKHOLE: used for not forwarding the frames
0055  * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses
0056  *           of the switch port net devices, towards the CPU port module.
0057  * PGID_UC: the flooding destinations for unknown unicast traffic.
0058  * PGID_MC: the flooding destinations for non-IP multicast traffic.
0059  * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic.
0060  * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic.
0061  * PGID_BC: the flooding destinations for broadcast traffic.
0062  */
0063 #define PGID_BLACKHOLE          57
0064 #define PGID_CPU            58
0065 #define PGID_UC             59
0066 #define PGID_MC             60
0067 #define PGID_MCIPV4         61
0068 #define PGID_MCIPV6         62
0069 #define PGID_BC             63
0070
0071 #define for_each_unicast_dest_pgid(ocelot, pgid)        \
0072     for ((pgid) = 0;                    \
0073          (pgid) < (ocelot)->num_phys_ports;         \
0074          (pgid)++)
0075
0076 #define for_each_nonreserved_multicast_dest_pgid(ocelot, pgid)  \
0077     for ((pgid) = (ocelot)->num_phys_ports + 1;     \
0078          (pgid) < PGID_BLACKHOLE;               \
0079          (pgid)++)
0080
0081 #define for_each_aggr_pgid(ocelot, pgid)            \
0082     for ((pgid) = PGID_AGGR;                \
0083          (pgid) < PGID_SRC;                 \
0084          (pgid)++)
0085
0086 /* Aggregation PGIDs, one per Link Aggregation Code */
0087 #define PGID_AGGR           64
0088
0089 /* Source PGIDs, one per physical port */
0090 #define PGID_SRC            80
0091
0092 #define OCELOT_NUM_TC           8
0093
0094 #define OCELOT_SPEED_2500       0
0095 #define OCELOT_SPEED_1000       1
0096 #define OCELOT_SPEED_100        2
0097 #define OCELOT_SPEED_10         3
0098
0099 #define OCELOT_PTP_PINS_NUM     4
0100
0101 #define TARGET_OFFSET           24
0102 #define REG_MASK            GENMASK(TARGET_OFFSET - 1, 0)
0103 #define REG(reg, offset)        [reg & REG_MASK] = offset
0104
0105 #define REG_RESERVED_ADDR       0xffffffff
0106 #define REG_RESERVED(reg)       REG(reg, REG_RESERVED_ADDR)
0107
0108 enum ocelot_target {
0109     ANA = 1,
0110     QS,
0111     QSYS,
0112     REW,
0113     SYS,
0114     S0,
0115     S1,
0116     S2,
0117     HSIO,
0118     PTP,
0119     FDMA,
0120     GCB,
0121     DEV_GMII,
0122     TARGET_MAX,
0123 };
0124
0125 enum ocelot_reg {
0126     ANA_ADVLEARN = ANA << TARGET_OFFSET,
0127     ANA_VLANMASK,
0128     ANA_PORT_B_DOMAIN,
0129     ANA_ANAGEFIL,
0130     ANA_ANEVENTS,
0131     ANA_STORMLIMIT_BURST,
0132     ANA_STORMLIMIT_CFG,
0133     ANA_ISOLATED_PORTS,
0134     ANA_COMMUNITY_PORTS,
0135     ANA_AUTOAGE,
0136     ANA_MACTOPTIONS,
0137     ANA_LEARNDISC,
0138     ANA_AGENCTRL,
0139     ANA_MIRRORPORTS,
0140     ANA_EMIRRORPORTS,
0141     ANA_FLOODING,
0142     ANA_FLOODING_IPMC,
0143     ANA_SFLOW_CFG,
0144     ANA_PORT_MODE,
0145     ANA_CUT_THRU_CFG,
0146     ANA_PGID_PGID,
0147     ANA_TABLES_ANMOVED,
0148     ANA_TABLES_MACHDATA,
0149     ANA_TABLES_MACLDATA,
0150     ANA_TABLES_STREAMDATA,
0151     ANA_TABLES_MACACCESS,
0152     ANA_TABLES_MACTINDX,
0153     ANA_TABLES_VLANACCESS,
0154     ANA_TABLES_VLANTIDX,
0155     ANA_TABLES_ISDXACCESS,
0156     ANA_TABLES_ISDXTIDX,
0157     ANA_TABLES_ENTRYLIM,
0158     ANA_TABLES_PTP_ID_HIGH,
0159     ANA_TABLES_PTP_ID_LOW,
0160     ANA_TABLES_STREAMACCESS,
0161     ANA_TABLES_STREAMTIDX,
0162     ANA_TABLES_SEQ_HISTORY,
0163     ANA_TABLES_SEQ_MASK,
0164     ANA_TABLES_SFID_MASK,
0165     ANA_TABLES_SFIDACCESS,
0166     ANA_TABLES_SFIDTIDX,
0167     ANA_MSTI_STATE,
0168     ANA_OAM_UPM_LM_CNT,
0169     ANA_SG_ACCESS_CTRL,
0170     ANA_SG_CONFIG_REG_1,
0171     ANA_SG_CONFIG_REG_2,
0172     ANA_SG_CONFIG_REG_3,
0173     ANA_SG_CONFIG_REG_4,
0174     ANA_SG_CONFIG_REG_5,
0175     ANA_SG_GCL_GS_CONFIG,
0176     ANA_SG_GCL_TI_CONFIG,
0177     ANA_SG_STATUS_REG_1,
0178     ANA_SG_STATUS_REG_2,
0179     ANA_SG_STATUS_REG_3,
0180     ANA_PORT_VLAN_CFG,
0181     ANA_PORT_DROP_CFG,
0182     ANA_PORT_QOS_CFG,
0183     ANA_PORT_VCAP_CFG,
0184     ANA_PORT_VCAP_S1_KEY_CFG,
0185     ANA_PORT_VCAP_S2_CFG,
0186     ANA_PORT_PCP_DEI_MAP,
0187     ANA_PORT_CPU_FWD_CFG,
0188     ANA_PORT_CPU_FWD_BPDU_CFG,
0189     ANA_PORT_CPU_FWD_GARP_CFG,
0190     ANA_PORT_CPU_FWD_CCM_CFG,
0191     ANA_PORT_PORT_CFG,
0192     ANA_PORT_POL_CFG,
0193     ANA_PORT_PTP_CFG,
0194     ANA_PORT_PTP_DLY1_CFG,
0195     ANA_PORT_PTP_DLY2_CFG,
0196     ANA_PORT_SFID_CFG,
0197     ANA_PFC_PFC_CFG,
0198     ANA_PFC_PFC_TIMER,
0199     ANA_IPT_OAM_MEP_CFG,
0200     ANA_IPT_IPT,
0201     ANA_PPT_PPT,
0202     ANA_FID_MAP_FID_MAP,
0203     ANA_AGGR_CFG,
0204     ANA_CPUQ_CFG,
0205     ANA_CPUQ_CFG2,
0206     ANA_CPUQ_8021_CFG,
0207     ANA_DSCP_CFG,
0208     ANA_DSCP_REWR_CFG,
0209     ANA_VCAP_RNG_TYPE_CFG,
0210     ANA_VCAP_RNG_VAL_CFG,
0211     ANA_VRAP_CFG,
0212     ANA_VRAP_HDR_DATA,
0213     ANA_VRAP_HDR_MASK,
0214     ANA_DISCARD_CFG,
0215     ANA_FID_CFG,
0216     ANA_POL_PIR_CFG,
0217     ANA_POL_CIR_CFG,
0218     ANA_POL_MODE_CFG,
0219     ANA_POL_PIR_STATE,
0220     ANA_POL_CIR_STATE,
0221     ANA_POL_STATE,
0222     ANA_POL_FLOWC,
0223     ANA_POL_HYST,
0224     ANA_POL_MISC_CFG,
0225     QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
0226     QS_XTR_RD,
0227     QS_XTR_FRM_PRUNING,
0228     QS_XTR_FLUSH,
0229     QS_XTR_DATA_PRESENT,
0230     QS_XTR_CFG,
0231     QS_INJ_GRP_CFG,
0232     QS_INJ_WR,
0233     QS_INJ_CTRL,
0234     QS_INJ_STATUS,
0235     QS_INJ_ERR,
0236     QS_INH_DBG,
0237     QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
0238     QSYS_SWITCH_PORT_MODE,
0239     QSYS_STAT_CNT_CFG,
0240     QSYS_EEE_CFG,
0241     QSYS_EEE_THRES,
0242     QSYS_IGR_NO_SHARING,
0243     QSYS_EGR_NO_SHARING,
0244     QSYS_SW_STATUS,
0245     QSYS_EXT_CPU_CFG,
0246     QSYS_PAD_CFG,
0247     QSYS_CPU_GROUP_MAP,
0248     QSYS_QMAP,
0249     QSYS_ISDX_SGRP,
0250     QSYS_TIMED_FRAME_ENTRY,
0251     QSYS_TFRM_MISC,
0252     QSYS_TFRM_PORT_DLY,
0253     QSYS_TFRM_TIMER_CFG_1,
0254     QSYS_TFRM_TIMER_CFG_2,
0255     QSYS_TFRM_TIMER_CFG_3,
0256     QSYS_TFRM_TIMER_CFG_4,
0257     QSYS_TFRM_TIMER_CFG_5,
0258     QSYS_TFRM_TIMER_CFG_6,
0259     QSYS_TFRM_TIMER_CFG_7,
0260     QSYS_TFRM_TIMER_CFG_8,
0261     QSYS_RED_PROFILE,
0262     QSYS_RES_QOS_MODE,
0263     QSYS_RES_CFG,
0264     QSYS_RES_STAT,
0265     QSYS_EGR_DROP_MODE,
0266     QSYS_EQ_CTRL,
0267     QSYS_EVENTS_CORE,
0268     QSYS_QMAXSDU_CFG_0,
0269     QSYS_QMAXSDU_CFG_1,
0270     QSYS_QMAXSDU_CFG_2,
0271     QSYS_QMAXSDU_CFG_3,
0272     QSYS_QMAXSDU_CFG_4,
0273     QSYS_QMAXSDU_CFG_5,
0274     QSYS_QMAXSDU_CFG_6,
0275     QSYS_QMAXSDU_CFG_7,
0276     QSYS_PREEMPTION_CFG,
0277     QSYS_CIR_CFG,
0278     QSYS_EIR_CFG,
0279     QSYS_SE_CFG,
0280     QSYS_SE_DWRR_CFG,
0281     QSYS_SE_CONNECT,
0282     QSYS_SE_DLB_SENSE,
0283     QSYS_CIR_STATE,
0284     QSYS_EIR_STATE,
0285     QSYS_SE_STATE,
0286     QSYS_HSCH_MISC_CFG,
0287     QSYS_TAG_CONFIG,
0288     QSYS_TAS_PARAM_CFG_CTRL,
0289     QSYS_PORT_MAX_SDU,
0290     QSYS_PARAM_CFG_REG_1,
0291     QSYS_PARAM_CFG_REG_2,
0292     QSYS_PARAM_CFG_REG_3,
0293     QSYS_PARAM_CFG_REG_4,
0294     QSYS_PARAM_CFG_REG_5,
0295     QSYS_GCL_CFG_REG_1,
0296     QSYS_GCL_CFG_REG_2,
0297     QSYS_PARAM_STATUS_REG_1,
0298     QSYS_PARAM_STATUS_REG_2,
0299     QSYS_PARAM_STATUS_REG_3,
0300     QSYS_PARAM_STATUS_REG_4,
0301     QSYS_PARAM_STATUS_REG_5,
0302     QSYS_PARAM_STATUS_REG_6,
0303     QSYS_PARAM_STATUS_REG_7,
0304     QSYS_PARAM_STATUS_REG_8,
0305     QSYS_PARAM_STATUS_REG_9,
0306     QSYS_GCL_STATUS_REG_1,
0307     QSYS_GCL_STATUS_REG_2,
0308     REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
0309     REW_TAG_CFG,
0310     REW_PORT_CFG,
0311     REW_DSCP_CFG,
0312     REW_PCP_DEI_QOS_MAP_CFG,
0313     REW_PTP_CFG,
0314     REW_PTP_DLY1_CFG,
0315     REW_RED_TAG_CFG,
0316     REW_DSCP_REMAP_DP1_CFG,
0317     REW_DSCP_REMAP_CFG,
0318     REW_STAT_CFG,
0319     REW_REW_STICKY,
0320     REW_PPT,
0321     SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
0322     SYS_COUNT_RX_UNICAST,
0323     SYS_COUNT_RX_MULTICAST,
0324     SYS_COUNT_RX_BROADCAST,
0325     SYS_COUNT_RX_SHORTS,
0326     SYS_COUNT_RX_FRAGMENTS,
0327     SYS_COUNT_RX_JABBERS,
0328     SYS_COUNT_RX_CRC_ALIGN_ERRS,
0329     SYS_COUNT_RX_SYM_ERRS,
0330     SYS_COUNT_RX_64,
0331     SYS_COUNT_RX_65_127,
0332     SYS_COUNT_RX_128_255,
0333     SYS_COUNT_RX_256_511,
0334     SYS_COUNT_RX_512_1023,
0335     SYS_COUNT_RX_1024_1526,
0336     SYS_COUNT_RX_1527_MAX,
0337     SYS_COUNT_RX_PAUSE,
0338     SYS_COUNT_RX_CONTROL,
0339     SYS_COUNT_RX_LONGS,
0340     SYS_COUNT_RX_CLASSIFIED_DROPS,
0341     SYS_COUNT_RX_RED_PRIO_0,
0342     SYS_COUNT_RX_RED_PRIO_1,
0343     SYS_COUNT_RX_RED_PRIO_2,
0344     SYS_COUNT_RX_RED_PRIO_3,
0345     SYS_COUNT_RX_RED_PRIO_4,
0346     SYS_COUNT_RX_RED_PRIO_5,
0347     SYS_COUNT_RX_RED_PRIO_6,
0348     SYS_COUNT_RX_RED_PRIO_7,
0349     SYS_COUNT_RX_YELLOW_PRIO_0,
0350     SYS_COUNT_RX_YELLOW_PRIO_1,
0351     SYS_COUNT_RX_YELLOW_PRIO_2,
0352     SYS_COUNT_RX_YELLOW_PRIO_3,
0353     SYS_COUNT_RX_YELLOW_PRIO_4,
0354     SYS_COUNT_RX_YELLOW_PRIO_5,
0355     SYS_COUNT_RX_YELLOW_PRIO_6,
0356     SYS_COUNT_RX_YELLOW_PRIO_7,
0357     SYS_COUNT_RX_GREEN_PRIO_0,
0358     SYS_COUNT_RX_GREEN_PRIO_1,
0359     SYS_COUNT_RX_GREEN_PRIO_2,
0360     SYS_COUNT_RX_GREEN_PRIO_3,
0361     SYS_COUNT_RX_GREEN_PRIO_4,
0362     SYS_COUNT_RX_GREEN_PRIO_5,
0363     SYS_COUNT_RX_GREEN_PRIO_6,
0364     SYS_COUNT_RX_GREEN_PRIO_7,
0365     SYS_COUNT_TX_OCTETS,
0366     SYS_COUNT_TX_UNICAST,
0367     SYS_COUNT_TX_MULTICAST,
0368     SYS_COUNT_TX_BROADCAST,
0369     SYS_COUNT_TX_COLLISION,
0370     SYS_COUNT_TX_DROPS,
0371     SYS_COUNT_TX_PAUSE,
0372     SYS_COUNT_TX_64,
0373     SYS_COUNT_TX_65_127,
0374     SYS_COUNT_TX_128_255,
0375     SYS_COUNT_TX_256_511,
0376     SYS_COUNT_TX_512_1023,
0377     SYS_COUNT_TX_1024_1526,
0378     SYS_COUNT_TX_1527_MAX,
0379     SYS_COUNT_TX_YELLOW_PRIO_0,
0380     SYS_COUNT_TX_YELLOW_PRIO_1,
0381     SYS_COUNT_TX_YELLOW_PRIO_2,
0382     SYS_COUNT_TX_YELLOW_PRIO_3,
0383     SYS_COUNT_TX_YELLOW_PRIO_4,
0384     SYS_COUNT_TX_YELLOW_PRIO_5,
0385     SYS_COUNT_TX_YELLOW_PRIO_6,
0386     SYS_COUNT_TX_YELLOW_PRIO_7,
0387     SYS_COUNT_TX_GREEN_PRIO_0,
0388     SYS_COUNT_TX_GREEN_PRIO_1,
0389     SYS_COUNT_TX_GREEN_PRIO_2,
0390     SYS_COUNT_TX_GREEN_PRIO_3,
0391     SYS_COUNT_TX_GREEN_PRIO_4,
0392     SYS_COUNT_TX_GREEN_PRIO_5,
0393     SYS_COUNT_TX_GREEN_PRIO_6,
0394     SYS_COUNT_TX_GREEN_PRIO_7,
0395     SYS_COUNT_TX_AGING,
0396     SYS_COUNT_DROP_LOCAL,
0397     SYS_COUNT_DROP_TAIL,
0398     SYS_COUNT_DROP_YELLOW_PRIO_0,
0399     SYS_COUNT_DROP_YELLOW_PRIO_1,
0400     SYS_COUNT_DROP_YELLOW_PRIO_2,
0401     SYS_COUNT_DROP_YELLOW_PRIO_3,
0402     SYS_COUNT_DROP_YELLOW_PRIO_4,
0403     SYS_COUNT_DROP_YELLOW_PRIO_5,
0404     SYS_COUNT_DROP_YELLOW_PRIO_6,
0405     SYS_COUNT_DROP_YELLOW_PRIO_7,
0406     SYS_COUNT_DROP_GREEN_PRIO_0,
0407     SYS_COUNT_DROP_GREEN_PRIO_1,
0408     SYS_COUNT_DROP_GREEN_PRIO_2,
0409     SYS_COUNT_DROP_GREEN_PRIO_3,
0410     SYS_COUNT_DROP_GREEN_PRIO_4,
0411     SYS_COUNT_DROP_GREEN_PRIO_5,
0412     SYS_COUNT_DROP_GREEN_PRIO_6,
0413     SYS_COUNT_DROP_GREEN_PRIO_7,
0414     SYS_RESET_CFG,
0415     SYS_SR_ETYPE_CFG,
0416     SYS_VLAN_ETYPE_CFG,
0417     SYS_PORT_MODE,
0418     SYS_FRONT_PORT_MODE,
0419     SYS_FRM_AGING,
0420     SYS_STAT_CFG,
0421     SYS_SW_STATUS,
0422     SYS_MISC_CFG,
0423     SYS_REW_MAC_HIGH_CFG,
0424     SYS_REW_MAC_LOW_CFG,
0425     SYS_TIMESTAMP_OFFSET,
0426     SYS_CMID,
0427     SYS_PAUSE_CFG,
0428     SYS_PAUSE_TOT_CFG,
0429     SYS_ATOP,
0430     SYS_ATOP_TOT_CFG,
0431     SYS_MAC_FC_CFG,
0432     SYS_MMGT,
0433     SYS_MMGT_FAST,
0434     SYS_EVENTS_DIF,
0435     SYS_EVENTS_CORE,
0436     SYS_CNT,
0437     SYS_PTP_STATUS,
0438     SYS_PTP_TXSTAMP,
0439     SYS_PTP_NXT,
0440     SYS_PTP_CFG,
0441     SYS_RAM_INIT,
0442     SYS_CM_ADDR,
0443     SYS_CM_DATA_WR,
0444     SYS_CM_DATA_RD,
0445     SYS_CM_OP,
0446     SYS_CM_DATA,
0447     PTP_PIN_CFG = PTP << TARGET_OFFSET,
0448     PTP_PIN_TOD_SEC_MSB,
0449     PTP_PIN_TOD_SEC_LSB,
0450     PTP_PIN_TOD_NSEC,
0451     PTP_PIN_WF_HIGH_PERIOD,
0452     PTP_PIN_WF_LOW_PERIOD,
0453     PTP_CFG_MISC,
0454     PTP_CLK_CFG_ADJ_CFG,
0455     PTP_CLK_CFG_ADJ_FREQ,
0456     GCB_SOFT_RST = GCB << TARGET_OFFSET,
0457     GCB_MIIM_MII_STATUS,
0458     GCB_MIIM_MII_CMD,
0459     GCB_MIIM_MII_DATA,
0460     DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET,
0461     DEV_PORT_MISC,
0462     DEV_EVENTS,
0463     DEV_EEE_CFG,
0464     DEV_RX_PATH_DELAY,
0465     DEV_TX_PATH_DELAY,
0466     DEV_PTP_PREDICT_CFG,
0467     DEV_MAC_ENA_CFG,
0468     DEV_MAC_MODE_CFG,
0469     DEV_MAC_MAXLEN_CFG,
0470     DEV_MAC_TAGS_CFG,
0471     DEV_MAC_ADV_CHK_CFG,
0472     DEV_MAC_IFG_CFG,
0473     DEV_MAC_HDX_CFG,
0474     DEV_MAC_DBG_CFG,
0475     DEV_MAC_FC_MAC_LOW_CFG,
0476     DEV_MAC_FC_MAC_HIGH_CFG,
0477     DEV_MAC_STICKY,
0478     PCS1G_CFG,
0479     PCS1G_MODE_CFG,
0480     PCS1G_SD_CFG,
0481     PCS1G_ANEG_CFG,
0482     PCS1G_ANEG_NP_CFG,
0483     PCS1G_LB_CFG,
0484     PCS1G_DBG_CFG,
0485     PCS1G_CDET_CFG,
0486     PCS1G_ANEG_STATUS,
0487     PCS1G_ANEG_NP_STATUS,
0488     PCS1G_LINK_STATUS,
0489     PCS1G_LINK_DOWN_CNT,
0490     PCS1G_STICKY,
0491     PCS1G_DEBUG_STATUS,
0492     PCS1G_LPI_CFG,
0493     PCS1G_LPI_WAKE_ERROR_CNT,
0494     PCS1G_LPI_STATUS,
0495     PCS1G_TSTPAT_MODE_CFG,
0496     PCS1G_TSTPAT_STATUS,
0497     DEV_PCS_FX100_CFG,
0498     DEV_PCS_FX100_STATUS,
0499 };
0500
0501 enum ocelot_regfield {
0502     ANA_ADVLEARN_VLAN_CHK,
0503     ANA_ADVLEARN_LEARN_MIRROR,
0504     ANA_ANEVENTS_FLOOD_DISCARD,
0505     ANA_ANEVENTS_MSTI_DROP,
0506     ANA_ANEVENTS_ACLKILL,
0507     ANA_ANEVENTS_ACLUSED,
0508     ANA_ANEVENTS_AUTOAGE,
0509     ANA_ANEVENTS_VS2TTL1,
0510     ANA_ANEVENTS_STORM_DROP,
0511     ANA_ANEVENTS_LEARN_DROP,
0512     ANA_ANEVENTS_AGED_ENTRY,
0513     ANA_ANEVENTS_CPU_LEARN_FAILED,
0514     ANA_ANEVENTS_AUTO_LEARN_FAILED,
0515     ANA_ANEVENTS_LEARN_REMOVE,
0516     ANA_ANEVENTS_AUTO_LEARNED,
0517     ANA_ANEVENTS_AUTO_MOVED,
0518     ANA_ANEVENTS_DROPPED,
0519     ANA_ANEVENTS_CLASSIFIED_DROP,
0520     ANA_ANEVENTS_CLASSIFIED_COPY,
0521     ANA_ANEVENTS_VLAN_DISCARD,
0522     ANA_ANEVENTS_FWD_DISCARD,
0523     ANA_ANEVENTS_MULTICAST_FLOOD,
0524     ANA_ANEVENTS_UNICAST_FLOOD,
0525     ANA_ANEVENTS_DEST_KNOWN,
0526     ANA_ANEVENTS_BUCKET3_MATCH,
0527     ANA_ANEVENTS_BUCKET2_MATCH,
0528     ANA_ANEVENTS_BUCKET1_MATCH,
0529     ANA_ANEVENTS_BUCKET0_MATCH,
0530     ANA_ANEVENTS_CPU_OPERATION,
0531     ANA_ANEVENTS_DMAC_LOOKUP,
0532     ANA_ANEVENTS_SMAC_LOOKUP,
0533     ANA_ANEVENTS_SEQ_GEN_ERR_0,
0534     ANA_ANEVENTS_SEQ_GEN_ERR_1,
0535     ANA_TABLES_MACACCESS_B_DOM,
0536     ANA_TABLES_MACTINDX_BUCKET,
0537     ANA_TABLES_MACTINDX_M_INDEX,
0538     QSYS_SWITCH_PORT_MODE_PORT_ENA,
0539     QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG,
0540     QSYS_SWITCH_PORT_MODE_YEL_RSRVD,
0541     QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE,
0542     QSYS_SWITCH_PORT_MODE_TX_PFC_ENA,
0543     QSYS_SWITCH_PORT_MODE_TX_PFC_MODE,
0544     QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
0545     QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
0546     QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
0547     QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
0548     QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
0549     SYS_PORT_MODE_DATA_WO_TS,
0550     SYS_PORT_MODE_INCL_INJ_HDR,
0551     SYS_PORT_MODE_INCL_XTR_HDR,
0552     SYS_PORT_MODE_INCL_HDR_ERR,
0553     SYS_RESET_CFG_CORE_ENA,
0554     SYS_RESET_CFG_MEM_ENA,
0555     SYS_RESET_CFG_MEM_INIT,
0556     GCB_SOFT_RST_SWC_RST,
0557     GCB_MIIM_MII_STATUS_PENDING,
0558     GCB_MIIM_MII_STATUS_BUSY,
0559     SYS_PAUSE_CFG_PAUSE_START,
0560     SYS_PAUSE_CFG_PAUSE_STOP,
0561     SYS_PAUSE_CFG_PAUSE_ENA,
0562     REGFIELD_MAX
0563 };
0564
0565 enum {
0566     /* VCAP_CORE_CFG */
0567     VCAP_CORE_UPDATE_CTRL,
0568     VCAP_CORE_MV_CFG,
0569     /* VCAP_CORE_CACHE */
0570     VCAP_CACHE_ENTRY_DAT,
0571     VCAP_CACHE_MASK_DAT,
0572     VCAP_CACHE_ACTION_DAT,
0573     VCAP_CACHE_CNT_DAT,
0574     VCAP_CACHE_TG_DAT,
0575     /* VCAP_CONST */
0576     VCAP_CONST_VCAP_VER,
0577     VCAP_CONST_ENTRY_WIDTH,
0578     VCAP_CONST_ENTRY_CNT,
0579     VCAP_CONST_ENTRY_SWCNT,
0580     VCAP_CONST_ENTRY_TG_WIDTH,
0581     VCAP_CONST_ACTION_DEF_CNT,
0582     VCAP_CONST_ACTION_WIDTH,
0583     VCAP_CONST_CNT_WIDTH,
0584     VCAP_CONST_CORE_CNT,
0585     VCAP_CONST_IF_CNT,
0586 };
0587
0588 enum ocelot_ptp_pins {
0589     PTP_PIN_0,
0590     PTP_PIN_1,
0591     PTP_PIN_2,
0592     PTP_PIN_3,
0593     TOD_ACC_PIN
0594 };
0595
0596 enum ocelot_stat {
0597     OCELOT_STAT_RX_OCTETS,
0598     OCELOT_STAT_RX_UNICAST,
0599     OCELOT_STAT_RX_MULTICAST,
0600     OCELOT_STAT_RX_BROADCAST,
0601     OCELOT_STAT_RX_SHORTS,
0602     OCELOT_STAT_RX_FRAGMENTS,
0603     OCELOT_STAT_RX_JABBERS,
0604     OCELOT_STAT_RX_CRC_ALIGN_ERRS,
0605     OCELOT_STAT_RX_SYM_ERRS,
0606     OCELOT_STAT_RX_64,
0607     OCELOT_STAT_RX_65_127,
0608     OCELOT_STAT_RX_128_255,
0609     OCELOT_STAT_RX_256_511,
0610     OCELOT_STAT_RX_512_1023,
0611     OCELOT_STAT_RX_1024_1526,
0612     OCELOT_STAT_RX_1527_MAX,
0613     OCELOT_STAT_RX_PAUSE,
0614     OCELOT_STAT_RX_CONTROL,
0615     OCELOT_STAT_RX_LONGS,
0616     OCELOT_STAT_RX_CLASSIFIED_DROPS,
0617     OCELOT_STAT_RX_RED_PRIO_0,
0618     OCELOT_STAT_RX_RED_PRIO_1,
0619     OCELOT_STAT_RX_RED_PRIO_2,
0620     OCELOT_STAT_RX_RED_PRIO_3,
0621     OCELOT_STAT_RX_RED_PRIO_4,
0622     OCELOT_STAT_RX_RED_PRIO_5,
0623     OCELOT_STAT_RX_RED_PRIO_6,
0624     OCELOT_STAT_RX_RED_PRIO_7,
0625     OCELOT_STAT_RX_YELLOW_PRIO_0,
0626     OCELOT_STAT_RX_YELLOW_PRIO_1,
0627     OCELOT_STAT_RX_YELLOW_PRIO_2,
0628     OCELOT_STAT_RX_YELLOW_PRIO_3,
0629     OCELOT_STAT_RX_YELLOW_PRIO_4,
0630     OCELOT_STAT_RX_YELLOW_PRIO_5,
0631     OCELOT_STAT_RX_YELLOW_PRIO_6,
0632     OCELOT_STAT_RX_YELLOW_PRIO_7,
0633     OCELOT_STAT_RX_GREEN_PRIO_0,
0634     OCELOT_STAT_RX_GREEN_PRIO_1,
0635     OCELOT_STAT_RX_GREEN_PRIO_2,
0636     OCELOT_STAT_RX_GREEN_PRIO_3,
0637     OCELOT_STAT_RX_GREEN_PRIO_4,
0638     OCELOT_STAT_RX_GREEN_PRIO_5,
0639     OCELOT_STAT_RX_GREEN_PRIO_6,
0640     OCELOT_STAT_RX_GREEN_PRIO_7,
0641     OCELOT_STAT_TX_OCTETS,
0642     OCELOT_STAT_TX_UNICAST,
0643     OCELOT_STAT_TX_MULTICAST,
0644     OCELOT_STAT_TX_BROADCAST,
0645     OCELOT_STAT_TX_COLLISION,
0646     OCELOT_STAT_TX_DROPS,
0647     OCELOT_STAT_TX_PAUSE,
0648     OCELOT_STAT_TX_64,
0649     OCELOT_STAT_TX_65_127,
0650     OCELOT_STAT_TX_128_255,
0651     OCELOT_STAT_TX_256_511,
0652     OCELOT_STAT_TX_512_1023,
0653     OCELOT_STAT_TX_1024_1526,
0654     OCELOT_STAT_TX_1527_MAX,
0655     OCELOT_STAT_TX_YELLOW_PRIO_0,
0656     OCELOT_STAT_TX_YELLOW_PRIO_1,
0657     OCELOT_STAT_TX_YELLOW_PRIO_2,
0658     OCELOT_STAT_TX_YELLOW_PRIO_3,
0659     OCELOT_STAT_TX_YELLOW_PRIO_4,
0660     OCELOT_STAT_TX_YELLOW_PRIO_5,
0661     OCELOT_STAT_TX_YELLOW_PRIO_6,
0662     OCELOT_STAT_TX_YELLOW_PRIO_7,
0663     OCELOT_STAT_TX_GREEN_PRIO_0,
0664     OCELOT_STAT_TX_GREEN_PRIO_1,
0665     OCELOT_STAT_TX_GREEN_PRIO_2,
0666     OCELOT_STAT_TX_GREEN_PRIO_3,
0667     OCELOT_STAT_TX_GREEN_PRIO_4,
0668     OCELOT_STAT_TX_GREEN_PRIO_5,
0669     OCELOT_STAT_TX_GREEN_PRIO_6,
0670     OCELOT_STAT_TX_GREEN_PRIO_7,
0671     OCELOT_STAT_TX_AGED,
0672     OCELOT_STAT_DROP_LOCAL,
0673     OCELOT_STAT_DROP_TAIL,
0674     OCELOT_STAT_DROP_YELLOW_PRIO_0,
0675     OCELOT_STAT_DROP_YELLOW_PRIO_1,
0676     OCELOT_STAT_DROP_YELLOW_PRIO_2,
0677     OCELOT_STAT_DROP_YELLOW_PRIO_3,
0678     OCELOT_STAT_DROP_YELLOW_PRIO_4,
0679     OCELOT_STAT_DROP_YELLOW_PRIO_5,
0680     OCELOT_STAT_DROP_YELLOW_PRIO_6,
0681     OCELOT_STAT_DROP_YELLOW_PRIO_7,
0682     OCELOT_STAT_DROP_GREEN_PRIO_0,
0683     OCELOT_STAT_DROP_GREEN_PRIO_1,
0684     OCELOT_STAT_DROP_GREEN_PRIO_2,
0685     OCELOT_STAT_DROP_GREEN_PRIO_3,
0686     OCELOT_STAT_DROP_GREEN_PRIO_4,
0687     OCELOT_STAT_DROP_GREEN_PRIO_5,
0688     OCELOT_STAT_DROP_GREEN_PRIO_6,
0689     OCELOT_STAT_DROP_GREEN_PRIO_7,
0690     OCELOT_NUM_STATS,
0691 };
0692
0693 struct ocelot_stat_layout {
0694     u32 reg;
0695     char name[ETH_GSTRING_LEN];
0696 };
0697
0698 struct ocelot_stats_region {
0699     struct list_head node;
0700     u32 base;
0701     int count;
0702     u32 *buf;
0703 };
0704
0705 enum ocelot_tag_prefix {
0706     OCELOT_TAG_PREFIX_DISABLED  = 0,
0707     OCELOT_TAG_PREFIX_NONE,
0708     OCELOT_TAG_PREFIX_SHORT,
0709     OCELOT_TAG_PREFIX_LONG,
0710 };
0711
0712 struct ocelot;
0713
0714 struct ocelot_ops {
0715     struct net_device *(*port_to_netdev)(struct ocelot *ocelot, int port);
0716     int (*netdev_to_port)(struct net_device *dev);
0717     int (*reset)(struct ocelot *ocelot);
0718     u16 (*wm_enc)(u16 value);
0719     u16 (*wm_dec)(u16 value);
0720     void (*wm_stat)(u32 val, u32 *inuse, u32 *maxuse);
0721     void (*psfp_init)(struct ocelot *ocelot);
0722     int (*psfp_filter_add)(struct ocelot *ocelot, int port,
0723                    struct flow_cls_offload *f);
0724     int (*psfp_filter_del)(struct ocelot *ocelot, struct flow_cls_offload *f);
0725     int (*psfp_stats_get)(struct ocelot *ocelot, struct flow_cls_offload *f,
0726                   struct flow_stats *stats);
0727     void (*cut_through_fwd)(struct ocelot *ocelot);
0728     void (*tas_clock_adjust)(struct ocelot *ocelot);
0729 };
0730
0731 struct ocelot_vcap_policer {
0732     struct list_head pol_list;
0733     u16 base;
0734     u16 max;
0735     u16 base2;
0736     u16 max2;
0737 };
0738
0739 struct ocelot_vcap_block {
0740     struct list_head rules;
0741     int count;
0742 };
0743
0744 struct ocelot_bridge_vlan {
0745     u16 vid;
0746     unsigned long portmask;
0747     unsigned long untagged;
0748     struct list_head list;
0749 };
0750
0751 enum ocelot_port_tag_config {
0752     /* all VLANs are egress-untagged */
0753     OCELOT_PORT_TAG_DISABLED = 0,
0754     /* all VLANs except the native VLAN and VID 0 are egress-tagged */
0755     OCELOT_PORT_TAG_NATIVE = 1,
0756     /* all VLANs except VID 0 are egress-tagged */
0757     OCELOT_PORT_TAG_TRUNK_NO_VID0 = 2,
0758     /* all VLANs are egress-tagged */
0759     OCELOT_PORT_TAG_TRUNK = 3,
0760 };
0761
0762 struct ocelot_psfp_list {
0763     struct list_head stream_list;
0764     struct list_head sfi_list;
0765     struct list_head sgi_list;
0766 };
0767
0768 enum ocelot_sb {
0769     OCELOT_SB_BUF,
0770     OCELOT_SB_REF,
0771     OCELOT_SB_NUM,
0772 };
0773
0774 enum ocelot_sb_pool {
0775     OCELOT_SB_POOL_ING,
0776     OCELOT_SB_POOL_EGR,
0777     OCELOT_SB_POOL_NUM,
0778 };
0779
0780 /* MAC table entry types.
0781  * ENTRYTYPE_NORMAL is subject to aging.
0782  * ENTRYTYPE_LOCKED is not subject to aging.
0783  * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast.
0784  * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast.
0785  */
0786 enum macaccess_entry_type {
0787     ENTRYTYPE_NORMAL = 0,
0788     ENTRYTYPE_LOCKED,
0789     ENTRYTYPE_MACv4,
0790     ENTRYTYPE_MACv6,
0791 };
0792
0793 #define OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION   BIT(0)
0794 #define OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP        BIT(1)
0795
0796 struct ocelot_lag_fdb {
0797     unsigned char addr[ETH_ALEN];
0798     u16 vid;
0799     struct net_device *bond;
0800     struct list_head list;
0801 };
0802
0803 struct ocelot_mirror {
0804     refcount_t refcount;
0805     int to;
0806 };
0807
0808 struct ocelot_port;
0809
0810 struct ocelot_port {
0811     struct ocelot           *ocelot;
0812
0813     struct regmap           *target;
0814
0815     struct net_device       *bond;
0816     struct net_device       *bridge;
0817
0818     struct ocelot_port      *dsa_8021q_cpu;
0819
0820     /* VLAN that untagged frames are classified to, on ingress */
0821     const struct ocelot_bridge_vlan *pvid_vlan;
0822
0823     struct tc_taprio_qopt_offload   *taprio;
0824
0825     phy_interface_t         phy_mode;
0826
0827     unsigned int            ptp_skbs_in_flight;
0828     struct sk_buff_head     tx_skbs;
0829
0830     u16             mrp_ring_id;
0831
0832     u8              ptp_cmd;
0833     u8              ts_id;
0834
0835     u8              index;
0836
0837     u8              stp_state;
0838     bool                vlan_aware;
0839     bool                is_dsa_8021q_cpu;
0840     bool                learn_ena;
0841
0842     bool                lag_tx_active;
0843
0844     int             bridge_num;
0845
0846     int             speed;
0847 };
0848
0849 struct ocelot {
0850     struct device           *dev;
0851     struct devlink          *devlink;
0852     struct devlink_port     *devlink_ports;
0853
0854     const struct ocelot_ops     *ops;
0855     struct regmap           *targets[TARGET_MAX];
0856     struct regmap_field     *regfields[REGFIELD_MAX];
0857     const u32 *const        *map;
0858     const struct ocelot_stat_layout *stats_layout;
0859     struct list_head        stats_regions;
0860
0861     u32             pool_size[OCELOT_SB_NUM][OCELOT_SB_POOL_NUM];
0862     int             packet_buffer_size;
0863     int             num_frame_refs;
0864     int             num_mact_rows;
0865
0866     struct ocelot_port      **ports;
0867
0868     u8              base_mac[ETH_ALEN];
0869
0870     struct list_head        vlans;
0871     struct list_head        traps;
0872     struct list_head        lag_fdbs;
0873
0874     /* Switches like VSC9959 have flooding per traffic class */
0875     int             num_flooding_pgids;
0876
0877     /* In tables like ANA:PORT and the ANA:PGID:PGID mask,
0878      * the CPU is located after the physical ports (at the
0879      * num_phys_ports index).
0880      */
0881     u8              num_phys_ports;
0882
0883     int             npi;
0884
0885     enum ocelot_tag_prefix      npi_inj_prefix;
0886     enum ocelot_tag_prefix      npi_xtr_prefix;
0887
0888     unsigned long           bridges;
0889
0890     struct list_head        multicast;
0891     struct list_head        pgids;
0892
0893     struct list_head        dummy_rules;
0894     struct ocelot_vcap_block    block[3];
0895     struct ocelot_vcap_policer  vcap_pol;
0896     struct vcap_props       *vcap;
0897     struct ocelot_mirror        *mirror;
0898
0899     struct ocelot_psfp_list     psfp;
0900
0901     /* Workqueue to check statistics for overflow with its lock */
0902     spinlock_t          stats_lock;
0903     u64             *stats;
0904     struct delayed_work     stats_work;
0905     struct workqueue_struct     *stats_queue;
0906
0907     /* Lock for serializing access to the MAC table */
0908     struct mutex            mact_lock;
0909     /* Lock for serializing forwarding domain changes */
0910     struct mutex            fwd_domain_lock;
0911
0912     /* Lock for serializing Time-Aware Shaper changes */
0913     struct mutex            tas_lock;
0914
0915     struct workqueue_struct     *owq;
0916
0917     u8              ptp:1;
0918     struct ptp_clock        *ptp_clock;
0919     struct ptp_clock_info       ptp_info;
0920     struct hwtstamp_config      hwtstamp_config;
0921     unsigned int            ptp_skbs_in_flight;
0922     /* Protects the 2-step TX timestamp ID logic */
0923     spinlock_t          ts_id_lock;
0924     /* Protects the PTP interface state */
0925     struct mutex            ptp_lock;
0926     /* Protects the PTP clock */
0927     spinlock_t          ptp_clock_lock;
0928     struct ptp_pin_desc     ptp_pins[OCELOT_PTP_PINS_NUM];
0929
0930     struct ocelot_fdma      *fdma;
0931 };
0932
0933 struct ocelot_policer {
0934     u32 rate; /* kilobit per second */
0935     u32 burst; /* bytes */
0936 };
0937
0938 #define ocelot_bulk_read(ocelot, reg, buf, count) \
0939     __ocelot_bulk_read_ix(ocelot, reg, 0, buf, count)
0940
0941 #define ocelot_read_ix(ocelot, reg, gi, ri) \
0942     __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
0943 #define ocelot_read_gix(ocelot, reg, gi) \
0944     __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
0945 #define ocelot_read_rix(ocelot, reg, ri) \
0946     __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
0947 #define ocelot_read(ocelot, reg) \
0948     __ocelot_read_ix(ocelot, reg, 0)
0949
0950 #define ocelot_write_ix(ocelot, val, reg, gi, ri) \
0951     __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
0952 #define ocelot_write_gix(ocelot, val, reg, gi) \
0953     __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
0954 #define ocelot_write_rix(ocelot, val, reg, ri) \
0955     __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
0956 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
0957
0958 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) \
0959     __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
0960 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) \
0961     __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
0962 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) \
0963     __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
0964 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
0965
0966 #define ocelot_field_write(ocelot, reg, val) \
0967     regmap_field_write((ocelot)->regfields[(reg)], (val))
0968 #define ocelot_field_read(ocelot, reg, val) \
0969     regmap_field_read((ocelot)->regfields[(reg)], (val))
0970 #define ocelot_fields_write(ocelot, id, reg, val) \
0971     regmap_fields_write((ocelot)->regfields[(reg)], (id), (val))
0972 #define ocelot_fields_read(ocelot, id, reg, val) \
0973     regmap_fields_read((ocelot)->regfields[(reg)], (id), (val))
0974
0975 #define ocelot_target_read_ix(ocelot, target, reg, gi, ri) \
0976     __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
0977 #define ocelot_target_read_gix(ocelot, target, reg, gi) \
0978     __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi))
0979 #define ocelot_target_read_rix(ocelot, target, reg, ri) \
0980     __ocelot_target_read_ix(ocelot, target, reg, reg##_RSZ * (ri))
0981 #define ocelot_target_read(ocelot, target, reg) \
0982     __ocelot_target_read_ix(ocelot, target, reg, 0)
0983
0984 #define ocelot_target_write_ix(ocelot, target, val, reg, gi, ri) \
0985     __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
0986 #define ocelot_target_write_gix(ocelot, target, val, reg, gi) \
0987     __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi))
0988 #define ocelot_target_write_rix(ocelot, target, val, reg, ri) \
0989     __ocelot_target_write_ix(ocelot, target, val, reg, reg##_RSZ * (ri))
0990 #define ocelot_target_write(ocelot, target, val, reg) \
0991     __ocelot_target_write_ix(ocelot, target, val, reg, 0)
0992
0993 /* I/O */
0994 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
0995 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
0996 void ocelot_port_rmwl(struct ocelot_port *port, u32 val, u32 mask, u32 reg);
0997 int __ocelot_bulk_read_ix(struct ocelot *ocelot, u32 reg, u32 offset, void *buf,
0998               int count);
0999 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
1000 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
1001 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
1002              u32 offset);
1003 u32 __ocelot_target_read_ix(struct ocelot *ocelot, enum ocelot_target target,
1004                 u32 reg, u32 offset);
1005 void __ocelot_target_write_ix(struct ocelot *ocelot, enum ocelot_target target,
1006                   u32 val, u32 reg, u32 offset);
1007
1008 /* Packet I/O */
1009 bool ocelot_can_inject(struct ocelot *ocelot, int grp);
1010 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp,
1011                   u32 rew_op, struct sk_buff *skb);
1012 void ocelot_ifh_port_set(void *ifh, int port, u32 rew_op, u32 vlan_tag);
1013 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **skb);
1014 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp);
1015 void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb,
1016                  u64 timestamp);
1017
1018 /* Hardware initialization */
1019 int ocelot_regfields_init(struct ocelot *ocelot,
1020               const struct reg_field *const regfields);
1021 struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res);
1022 int ocelot_init(struct ocelot *ocelot);
1023 void ocelot_deinit(struct ocelot *ocelot);
1024 void ocelot_init_port(struct ocelot *ocelot, int port);
1025 void ocelot_deinit_port(struct ocelot *ocelot, int port);
1026
1027 void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port, int cpu);
1028 void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port);
1029 u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port);
1030
1031 /* DSA callbacks */
1032 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data);
1033 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data);
1034 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset);
1035 int ocelot_get_ts_info(struct ocelot *ocelot, int port,
1036                struct ethtool_ts_info *info);
1037 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs);
1038 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, bool enabled,
1039                    struct netlink_ext_ack *extack);
1040 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state);
1041 u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port);
1042 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port,
1043                  struct switchdev_brport_flags val);
1044 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port,
1045                   struct switchdev_brport_flags val);
1046 int ocelot_port_get_default_prio(struct ocelot *ocelot, int port);
1047 int ocelot_port_set_default_prio(struct ocelot *ocelot, int port, u8 prio);
1048 int ocelot_port_get_dscp_prio(struct ocelot *ocelot, int port, u8 dscp);
1049 int ocelot_port_add_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio);
1050 int ocelot_port_del_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio);
1051 int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
1052                 struct net_device *bridge, int bridge_num,
1053                 struct netlink_ext_ack *extack);
1054 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
1055                   struct net_device *bridge);
1056 int ocelot_mact_flush(struct ocelot *ocelot, int port);
1057 int ocelot_fdb_dump(struct ocelot *ocelot, int port,
1058             dsa_fdb_dump_cb_t *cb, void *data);
1059 int ocelot_fdb_add(struct ocelot *ocelot, int port, const unsigned char *addr,
1060            u16 vid, const struct net_device *bridge);
1061 int ocelot_fdb_del(struct ocelot *ocelot, int port, const unsigned char *addr,
1062            u16 vid, const struct net_device *bridge);
1063 int ocelot_lag_fdb_add(struct ocelot *ocelot, struct net_device *bond,
1064                const unsigned char *addr, u16 vid,
1065                const struct net_device *bridge);
1066 int ocelot_lag_fdb_del(struct ocelot *ocelot, struct net_device *bond,
1067                const unsigned char *addr, u16 vid,
1068                const struct net_device *bridge);
1069 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid,
1070             bool untagged, struct netlink_ext_ack *extack);
1071 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
1072             bool untagged);
1073 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid);
1074 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr);
1075 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr);
1076 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port,
1077                  struct sk_buff *skb,
1078                  struct sk_buff **clone);
1079 void ocelot_get_txtstamp(struct ocelot *ocelot);
1080 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu);
1081 int ocelot_get_max_mtu(struct ocelot *ocelot, int port);
1082 int ocelot_port_policer_add(struct ocelot *ocelot, int port,
1083                 struct ocelot_policer *pol);
1084 int ocelot_port_policer_del(struct ocelot *ocelot, int port);
1085 int ocelot_port_mirror_add(struct ocelot *ocelot, int from, int to,
1086                bool ingress, struct netlink_ext_ack *extack);
1087 void ocelot_port_mirror_del(struct ocelot *ocelot, int from, bool ingress);
1088 int ocelot_cls_flower_replace(struct ocelot *ocelot, int port,
1089                   struct flow_cls_offload *f, bool ingress);
1090 int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port,
1091                   struct flow_cls_offload *f, bool ingress);
1092 int ocelot_cls_flower_stats(struct ocelot *ocelot, int port,
1093                 struct flow_cls_offload *f, bool ingress);
1094 int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
1095             const struct switchdev_obj_port_mdb *mdb,
1096             const struct net_device *bridge);
1097 int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
1098             const struct switchdev_obj_port_mdb *mdb,
1099             const struct net_device *bridge);
1100 int ocelot_port_lag_join(struct ocelot *ocelot, int port,
1101              struct net_device *bond,
1102              struct netdev_lag_upper_info *info);
1103 void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
1104                struct net_device *bond);
1105 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active);
1106
1107 int ocelot_devlink_sb_register(struct ocelot *ocelot);
1108 void ocelot_devlink_sb_unregister(struct ocelot *ocelot);
1109 int ocelot_sb_pool_get(struct ocelot *ocelot, unsigned int sb_index,
1110                u16 pool_index,
1111                struct devlink_sb_pool_info *pool_info);
1112 int ocelot_sb_pool_set(struct ocelot *ocelot, unsigned int sb_index,
1113                u16 pool_index, u32 size,
1114                enum devlink_sb_threshold_type threshold_type,
1115                struct netlink_ext_ack *extack);
1116 int ocelot_sb_port_pool_get(struct ocelot *ocelot, int port,
1117                 unsigned int sb_index, u16 pool_index,
1118                 u32 *p_threshold);
1119 int ocelot_sb_port_pool_set(struct ocelot *ocelot, int port,
1120                 unsigned int sb_index, u16 pool_index,
1121                 u32 threshold, struct netlink_ext_ack *extack);
1122 int ocelot_sb_tc_pool_bind_get(struct ocelot *ocelot, int port,
1123                    unsigned int sb_index, u16 tc_index,
1124                    enum devlink_sb_pool_type pool_type,
1125                    u16 *p_pool_index, u32 *p_threshold);
1126 int ocelot_sb_tc_pool_bind_set(struct ocelot *ocelot, int port,
1127                    unsigned int sb_index, u16 tc_index,
1128                    enum devlink_sb_pool_type pool_type,
1129                    u16 pool_index, u32 threshold,
1130                    struct netlink_ext_ack *extack);
1131 int ocelot_sb_occ_snapshot(struct ocelot *ocelot, unsigned int sb_index);
1132 int ocelot_sb_occ_max_clear(struct ocelot *ocelot, unsigned int sb_index);
1133 int ocelot_sb_occ_port_pool_get(struct ocelot *ocelot, int port,
1134                 unsigned int sb_index, u16 pool_index,
1135                 u32 *p_cur, u32 *p_max);
1136 int ocelot_sb_occ_tc_port_bind_get(struct ocelot *ocelot, int port,
1137                    unsigned int sb_index, u16 tc_index,
1138                    enum devlink_sb_pool_type pool_type,
1139                    u32 *p_cur, u32 *p_max);
1140
1141 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port,
1142                   unsigned int link_an_mode,
1143                   phy_interface_t interface,
1144                   unsigned long quirks);
1145 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port,
1146                 struct phy_device *phydev,
1147                 unsigned int link_an_mode,
1148                 phy_interface_t interface,
1149                 int speed, int duplex,
1150                 bool tx_pause, bool rx_pause,
1151                 unsigned long quirks);
1152
1153 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx,
1154                const unsigned char mac[ETH_ALEN],
1155                unsigned int vid, enum macaccess_entry_type *type);
1156 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx,
1157                  const unsigned char mac[ETH_ALEN],
1158                  unsigned int vid,
1159                  enum macaccess_entry_type type,
1160                  int sfid, int ssid);
1161
1162 int ocelot_migrate_mdbs(struct ocelot *ocelot, unsigned long from_mask,
1163             unsigned long to_mask);
1164
1165 int ocelot_vcap_policer_add(struct ocelot *ocelot, u32 pol_ix,
1166                 struct ocelot_policer *pol);
1167 int ocelot_vcap_policer_del(struct ocelot *ocelot, u32 pol_ix);
1168
1169 #if IS_ENABLED(CONFIG_BRIDGE_MRP)
1170 int ocelot_mrp_add(struct ocelot *ocelot, int port,
1171            const struct switchdev_obj_mrp *mrp);
1172 int ocelot_mrp_del(struct ocelot *ocelot, int port,
1173            const struct switchdev_obj_mrp *mrp);
1174 int ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port,
1175                  const struct switchdev_obj_ring_role_mrp *mrp);
1176 int ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port,
1177                  const struct switchdev_obj_ring_role_mrp *mrp);
1178 #else
1179 static inline int ocelot_mrp_add(struct ocelot *ocelot, int port,
1180                  const struct switchdev_obj_mrp *mrp)
1181 {
1182     return -EOPNOTSUPP;
1183 }
1184
1185 static inline int ocelot_mrp_del(struct ocelot *ocelot, int port,
1186                  const struct switchdev_obj_mrp *mrp)
1187 {
1188     return -EOPNOTSUPP;
1189 }
1190
1191 static inline int
1192 ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port,
1193              const struct switchdev_obj_ring_role_mrp *mrp)
1194 {
1195     return -EOPNOTSUPP;
1196 }
1197
1198 static inline int
1199 ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port,
1200              const struct switchdev_obj_ring_role_mrp *mrp)
1201 {
1202     return -EOPNOTSUPP;
1203 }
1204 #endif
1205
1206 #endif