fsl/qe/ucc_slow.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
0004  *
0005  * Authors:     Shlomi Gridish <gridish@freescale.com>
0006  *      Li Yang <leoli@freescale.com>
0007  *
0008  * Description:
0009  * Internal header file for UCC SLOW unit routines.
0010  */
0011 #ifndef __UCC_SLOW_H__
0012 #define __UCC_SLOW_H__
0013
0014 #include <linux/types.h>
0015
0016 #include <soc/fsl/qe/immap_qe.h>
0017 #include <soc/fsl/qe/qe.h>
0018
0019 #include <soc/fsl/qe/ucc.h>
0020
0021 /* transmit BD's status */
0022 #define T_R 0x80000000  /* ready bit */
0023 #define T_PAD   0x40000000  /* add pads to short frames */
0024 #define T_W 0x20000000  /* wrap bit */
0025 #define T_I 0x10000000  /* interrupt on completion */
0026 #define T_L 0x08000000  /* last */
0027
0028 #define T_A 0x04000000  /* Address - the data transmitted as address
0029                    chars */
0030 #define T_TC    0x04000000  /* transmit CRC */
0031 #define T_CM    0x02000000  /* continuous mode */
0032 #define T_DEF   0x02000000  /* collision on previous attempt to transmit */
0033 #define T_P 0x01000000  /* Preamble - send Preamble sequence before
0034                    data */
0035 #define T_HB    0x01000000  /* heartbeat */
0036 #define T_NS    0x00800000  /* No Stop */
0037 #define T_LC    0x00800000  /* late collision */
0038 #define T_RL    0x00400000  /* retransmission limit */
0039 #define T_UN    0x00020000  /* underrun */
0040 #define T_CT    0x00010000  /* CTS lost */
0041 #define T_CSL   0x00010000  /* carrier sense lost */
0042 #define T_RC    0x003c0000  /* retry count */
0043
0044 /* Receive BD's status */
0045 #define R_E 0x80000000  /* buffer empty */
0046 #define R_W 0x20000000  /* wrap bit */
0047 #define R_I 0x10000000  /* interrupt on reception */
0048 #define R_L 0x08000000  /* last */
0049 #define R_C 0x08000000  /* the last byte in this buffer is a cntl
0050                    char */
0051 #define R_F 0x04000000  /* first */
0052 #define R_A 0x04000000  /* the first byte in this buffer is address
0053                    byte */
0054 #define R_CM    0x02000000  /* continuous mode */
0055 #define R_ID    0x01000000  /* buffer close on reception of idles */
0056 #define R_M 0x01000000  /* Frame received because of promiscuous
0057                    mode */
0058 #define R_AM    0x00800000  /* Address match */
0059 #define R_DE    0x00800000  /* Address match */
0060 #define R_LG    0x00200000  /* Break received */
0061 #define R_BR    0x00200000  /* Frame length violation */
0062 #define R_NO    0x00100000  /* Rx Non Octet Aligned Packet */
0063 #define R_FR    0x00100000  /* Framing Error (no stop bit) character
0064                    received */
0065 #define R_PR    0x00080000  /* Parity Error character received */
0066 #define R_AB    0x00080000  /* Frame Aborted */
0067 #define R_SH    0x00080000  /* frame is too short */
0068 #define R_CR    0x00040000  /* CRC Error */
0069 #define R_OV    0x00020000  /* Overrun */
0070 #define R_CD    0x00010000  /* CD lost */
0071 #define R_CL    0x00010000  /* this frame is closed because of a
0072                    collision */
0073
0074 /* Rx Data buffer must be 4 bytes aligned in most cases.*/
0075 #define UCC_SLOW_RX_ALIGN       4
0076 #define UCC_SLOW_MRBLR_ALIGNMENT    4
0077 #define UCC_SLOW_PRAM_SIZE      0x100
0078 #define ALIGNMENT_OF_UCC_SLOW_PRAM  64
0079
0080 /* UCC Slow Channel Protocol Mode */
0081 enum ucc_slow_channel_protocol_mode {
0082     UCC_SLOW_CHANNEL_PROTOCOL_MODE_QMC = 0x00000002,
0083     UCC_SLOW_CHANNEL_PROTOCOL_MODE_UART = 0x00000004,
0084     UCC_SLOW_CHANNEL_PROTOCOL_MODE_BISYNC = 0x00000008,
0085 };
0086
0087 /* UCC Slow Transparent Transmit CRC (TCRC) */
0088 enum ucc_slow_transparent_tcrc {
0089     /* 16-bit CCITT CRC (HDLC).  (X16 + X12 + X5 + 1) */
0090     UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC16 = 0x00000000,
0091     /* CRC16 (BISYNC).  (X16 + X15 + X2 + 1) */
0092     UCC_SLOW_TRANSPARENT_TCRC_CRC16 = 0x00004000,
0093     /* 32-bit CCITT CRC (Ethernet and HDLC) */
0094     UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC32 = 0x00008000,
0095 };
0096
0097 /* UCC Slow oversampling rate for transmitter (TDCR) */
0098 enum ucc_slow_tx_oversampling_rate {
0099     /* 1x clock mode */
0100     UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_1 = 0x00000000,
0101     /* 8x clock mode */
0102     UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_8 = 0x00010000,
0103     /* 16x clock mode */
0104     UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_16 = 0x00020000,
0105     /* 32x clock mode */
0106     UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_32 = 0x00030000,
0107 };
0108
0109 /* UCC Slow Oversampling rate for receiver (RDCR)
0110 */
0111 enum ucc_slow_rx_oversampling_rate {
0112     /* 1x clock mode */
0113     UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_1 = 0x00000000,
0114     /* 8x clock mode */
0115     UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_8 = 0x00004000,
0116     /* 16x clock mode */
0117     UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_16 = 0x00008000,
0118     /* 32x clock mode */
0119     UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_32 = 0x0000c000,
0120 };
0121
0122 /* UCC Slow Transmitter encoding method (TENC)
0123 */
0124 enum ucc_slow_tx_encoding_method {
0125     UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZ = 0x00000000,
0126     UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZI = 0x00000100
0127 };
0128
0129 /* UCC Slow Receiver decoding method (RENC)
0130 */
0131 enum ucc_slow_rx_decoding_method {
0132     UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZ = 0x00000000,
0133     UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZI = 0x00000800
0134 };
0135
0136 /* UCC Slow Diagnostic mode (DIAG)
0137 */
0138 enum ucc_slow_diag_mode {
0139     UCC_SLOW_DIAG_MODE_NORMAL = 0x00000000,
0140     UCC_SLOW_DIAG_MODE_LOOPBACK = 0x00000040,
0141     UCC_SLOW_DIAG_MODE_ECHO = 0x00000080,
0142     UCC_SLOW_DIAG_MODE_LOOPBACK_ECHO = 0x000000c0
0143 };
0144
0145 struct ucc_slow_info {
0146     int ucc_num;
0147     int protocol;           /* QE_CR_PROTOCOL_xxx */
0148     enum qe_clock rx_clock;
0149     enum qe_clock tx_clock;
0150     phys_addr_t regs;
0151     int irq;
0152     u16 uccm_mask;
0153     int data_mem_part;
0154     int init_tx;
0155     int init_rx;
0156     u32 tx_bd_ring_len;
0157     u32 rx_bd_ring_len;
0158     int rx_interrupts;
0159     int brkpt_support;
0160     int grant_support;
0161     int tsa;
0162     int cdp;
0163     int cds;
0164     int ctsp;
0165     int ctss;
0166     int rinv;
0167     int tinv;
0168     int rtsm;
0169     int rfw;
0170     int tci;
0171     int tend;
0172     int tfl;
0173     int txsy;
0174     u16 max_rx_buf_length;
0175     enum ucc_slow_transparent_tcrc tcrc;
0176     enum ucc_slow_channel_protocol_mode mode;
0177     enum ucc_slow_diag_mode diag;
0178     enum ucc_slow_tx_oversampling_rate tdcr;
0179     enum ucc_slow_rx_oversampling_rate rdcr;
0180     enum ucc_slow_tx_encoding_method tenc;
0181     enum ucc_slow_rx_decoding_method renc;
0182 };
0183
0184 struct ucc_slow_private {
0185     struct ucc_slow_info *us_info;
0186     struct ucc_slow __iomem *us_regs; /* Ptr to memory map of UCC regs */
0187     struct ucc_slow_pram __iomem *us_pram;  /* a pointer to the parameter RAM */
0188     s32 us_pram_offset;
0189     int enabled_tx;     /* Whether channel is enabled for Tx (ENT) */
0190     int enabled_rx;     /* Whether channel is enabled for Rx (ENR) */
0191     int stopped_tx;     /* Whether channel has been stopped for Tx
0192                    (STOP_TX, etc.) */
0193     int stopped_rx;     /* Whether channel has been stopped for Rx */
0194     struct list_head confQ; /* frames passed to chip waiting for tx */
0195     u32 first_tx_bd_mask;   /* mask is used in Tx routine to save status
0196                    and length for first BD in a frame */
0197     s32 tx_base_offset; /* first BD in Tx BD table offset (In MURAM) */
0198     s32 rx_base_offset; /* first BD in Rx BD table offset (In MURAM) */
0199     struct qe_bd __iomem *confBd;   /* next BD for confirm after Tx */
0200     struct qe_bd __iomem *tx_bd;    /* next BD for new Tx request */
0201     struct qe_bd __iomem *rx_bd;    /* next BD to collect after Rx */
0202     void *p_rx_frame;   /* accumulating receive frame */
0203     __be16 __iomem *p_ucce; /* a pointer to the event register in memory */
0204     __be16 __iomem *p_uccm; /* a pointer to the mask register in memory */
0205     u16 saved_uccm;     /* a saved mask for the RX Interrupt bits */
0206 #ifdef STATISTICS
0207     u32 tx_frames;      /* Transmitted frames counters */
0208     u32 rx_frames;      /* Received frames counters (only frames
0209                    passed to application) */
0210     u32 rx_discarded;   /* Discarded frames counters (frames that
0211                    were discarded by the driver due to
0212                    errors) */
0213 #endif              /* STATISTICS */
0214 };
0215
0216 /* ucc_slow_init
0217  * Initializes Slow UCC according to provided parameters.
0218  *
0219  * us_info  - (In) pointer to the slow UCC info structure.
0220  * uccs_ret - (Out) pointer to the slow UCC structure.
0221  */
0222 int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret);
0223
0224 /* ucc_slow_free
0225  * Frees all resources for slow UCC.
0226  *
0227  * uccs - (In) pointer to the slow UCC structure.
0228  */
0229 void ucc_slow_free(struct ucc_slow_private * uccs);
0230
0231 /* ucc_slow_enable
0232  * Enables a fast UCC port.
0233  * This routine enables Tx and/or Rx through the General UCC Mode Register.
0234  *
0235  * uccs - (In) pointer to the slow UCC structure.
0236  * mode - (In) TX, RX, or both.
0237  */
0238 void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode);
0239
0240 /* ucc_slow_disable
0241  * Disables a fast UCC port.
0242  * This routine disables Tx and/or Rx through the General UCC Mode Register.
0243  *
0244  * uccs - (In) pointer to the slow UCC structure.
0245  * mode - (In) TX, RX, or both.
0246  */
0247 void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode);
0248
0249 /* ucc_slow_graceful_stop_tx
0250  * Smoothly stops transmission on a specified slow UCC.
0251  *
0252  * uccs - (In) pointer to the slow UCC structure.
0253  */
0254 void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs);
0255
0256 /* ucc_slow_stop_tx
0257  * Stops transmission on a specified slow UCC.
0258  *
0259  * uccs - (In) pointer to the slow UCC structure.
0260  */
0261 void ucc_slow_stop_tx(struct ucc_slow_private * uccs);
0262
0263 /* ucc_slow_restart_tx
0264  * Restarts transmitting on a specified slow UCC.
0265  *
0266  * uccs - (In) pointer to the slow UCC structure.
0267  */
0268 void ucc_slow_restart_tx(struct ucc_slow_private *uccs);
0269
0270 u32 ucc_slow_get_qe_cr_subblock(int uccs_num);
0271
0272 #endif              /* __UCC_SLOW_H__ */