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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * QUICC Engine (QE) Internal Memory Map.
0004  * The Internal Memory Map for devices with QE on them. This
0005  * is the superset of all QE devices (8360, etc.).
0006 
0007  * Copyright (C) 2006. Freescale Semiconductor, Inc. All rights reserved.
0008  *
0009  * Authors:     Shlomi Gridish <gridish@freescale.com>
0010  *      Li Yang <leoli@freescale.com>
0011  */
0012 #ifndef _ASM_POWERPC_IMMAP_QE_H
0013 #define _ASM_POWERPC_IMMAP_QE_H
0014 #ifdef __KERNEL__
0015 
0016 #include <linux/types.h>
0017 
0018 #include <asm/io.h>
0019 
0020 #define QE_IMMAP_SIZE   (1024 * 1024)   /* 1MB from 1MB+IMMR */
0021 
0022 /* QE I-RAM */
0023 struct qe_iram {
0024     __be32  iadd;       /* I-RAM Address Register */
0025     __be32  idata;      /* I-RAM Data Register */
0026     u8  res0[0x04];
0027     __be32  iready;     /* I-RAM Ready Register */
0028     u8  res1[0x70];
0029 } __attribute__ ((packed));
0030 
0031 /* QE Interrupt Controller */
0032 struct qe_ic_regs {
0033     __be32  qicr;
0034     __be32  qivec;
0035     __be32  qripnr;
0036     __be32  qipnr;
0037     __be32  qipxcc;
0038     __be32  qipycc;
0039     __be32  qipwcc;
0040     __be32  qipzcc;
0041     __be32  qimr;
0042     __be32  qrimr;
0043     __be32  qicnr;
0044     u8  res0[0x4];
0045     __be32  qiprta;
0046     __be32  qiprtb;
0047     u8  res1[0x4];
0048     __be32  qricr;
0049     u8  res2[0x20];
0050     __be32  qhivec;
0051     u8  res3[0x1C];
0052 } __attribute__ ((packed));
0053 
0054 /* Communications Processor */
0055 struct cp_qe {
0056     __be32  cecr;       /* QE command register */
0057     __be32  ceccr;      /* QE controller configuration register */
0058     __be32  cecdr;      /* QE command data register */
0059     u8  res0[0xA];
0060     __be16  ceter;      /* QE timer event register */
0061     u8  res1[0x2];
0062     __be16  cetmr;      /* QE timers mask register */
0063     __be32  cetscr;     /* QE time-stamp timer control register */
0064     __be32  cetsr1;     /* QE time-stamp register 1 */
0065     __be32  cetsr2;     /* QE time-stamp register 2 */
0066     u8  res2[0x8];
0067     __be32  cevter;     /* QE virtual tasks event register */
0068     __be32  cevtmr;     /* QE virtual tasks mask register */
0069     __be16  cercr;      /* QE RAM control register */
0070     u8  res3[0x2];
0071     u8  res4[0x24];
0072     __be16  ceexe1;     /* QE external request 1 event register */
0073     u8  res5[0x2];
0074     __be16  ceexm1;     /* QE external request 1 mask register */
0075     u8  res6[0x2];
0076     __be16  ceexe2;     /* QE external request 2 event register */
0077     u8  res7[0x2];
0078     __be16  ceexm2;     /* QE external request 2 mask register */
0079     u8  res8[0x2];
0080     __be16  ceexe3;     /* QE external request 3 event register */
0081     u8  res9[0x2];
0082     __be16  ceexm3;     /* QE external request 3 mask register */
0083     u8  res10[0x2];
0084     __be16  ceexe4;     /* QE external request 4 event register */
0085     u8  res11[0x2];
0086     __be16  ceexm4;     /* QE external request 4 mask register */
0087     u8  res12[0x3A];
0088     __be32  ceurnr;     /* QE microcode revision number register */
0089     u8  res13[0x244];
0090 } __attribute__ ((packed));
0091 
0092 /* QE Multiplexer */
0093 struct qe_mux {
0094     __be32  cmxgcr;     /* CMX general clock route register */
0095     __be32  cmxsi1cr_l; /* CMX SI1 clock route low register */
0096     __be32  cmxsi1cr_h; /* CMX SI1 clock route high register */
0097     __be32  cmxsi1syr;  /* CMX SI1 SYNC route register */
0098     __be32  cmxucr[4];  /* CMX UCCx clock route registers */
0099     __be32  cmxupcr;    /* CMX UPC clock route register */
0100     u8  res0[0x1C];
0101 } __attribute__ ((packed));
0102 
0103 /* QE Timers */
0104 struct qe_timers {
0105     u8  gtcfr1;     /* Timer 1 and Timer 2 global config register*/
0106     u8  res0[0x3];
0107     u8  gtcfr2;     /* Timer 3 and timer 4 global config register*/
0108     u8  res1[0xB];
0109     __be16  gtmdr1;     /* Timer 1 mode register */
0110     __be16  gtmdr2;     /* Timer 2 mode register */
0111     __be16  gtrfr1;     /* Timer 1 reference register */
0112     __be16  gtrfr2;     /* Timer 2 reference register */
0113     __be16  gtcpr1;     /* Timer 1 capture register */
0114     __be16  gtcpr2;     /* Timer 2 capture register */
0115     __be16  gtcnr1;     /* Timer 1 counter */
0116     __be16  gtcnr2;     /* Timer 2 counter */
0117     __be16  gtmdr3;     /* Timer 3 mode register */
0118     __be16  gtmdr4;     /* Timer 4 mode register */
0119     __be16  gtrfr3;     /* Timer 3 reference register */
0120     __be16  gtrfr4;     /* Timer 4 reference register */
0121     __be16  gtcpr3;     /* Timer 3 capture register */
0122     __be16  gtcpr4;     /* Timer 4 capture register */
0123     __be16  gtcnr3;     /* Timer 3 counter */
0124     __be16  gtcnr4;     /* Timer 4 counter */
0125     __be16  gtevr1;     /* Timer 1 event register */
0126     __be16  gtevr2;     /* Timer 2 event register */
0127     __be16  gtevr3;     /* Timer 3 event register */
0128     __be16  gtevr4;     /* Timer 4 event register */
0129     __be16  gtps;       /* Timer 1 prescale register */
0130     u8 res2[0x46];
0131 } __attribute__ ((packed));
0132 
0133 /* BRG */
0134 struct qe_brg {
0135     __be32  brgc[16];   /* BRG configuration registers */
0136     u8  res0[0x40];
0137 } __attribute__ ((packed));
0138 
0139 /* SPI */
0140 struct spi {
0141     u8  res0[0x20];
0142     __be32  spmode;     /* SPI mode register */
0143     u8  res1[0x2];
0144     u8  spie;       /* SPI event register */
0145     u8  res2[0x1];
0146     u8  res3[0x2];
0147     u8  spim;       /* SPI mask register */
0148     u8  res4[0x1];
0149     u8  res5[0x1];
0150     u8  spcom;      /* SPI command register */
0151     u8  res6[0x2];
0152     __be32  spitd;      /* SPI transmit data register (cpu mode) */
0153     __be32  spird;      /* SPI receive data register (cpu mode) */
0154     u8  res7[0x8];
0155 } __attribute__ ((packed));
0156 
0157 /* SI */
0158 struct si1 {
0159     __be16  sixmr1[4];  /* SI1 TDMx (x = A B C D) mode register */
0160     u8  siglmr1_h;  /* SI1 global mode register high */
0161     u8  res0[0x1];
0162     u8  sicmdr1_h;  /* SI1 command register high */
0163     u8  res2[0x1];
0164     u8  sistr1_h;   /* SI1 status register high */
0165     u8  res3[0x1];
0166     __be16  sirsr1_h;   /* SI1 RAM shadow address register high */
0167     u8  sitarc1;    /* SI1 RAM counter Tx TDMA */
0168     u8  sitbrc1;    /* SI1 RAM counter Tx TDMB */
0169     u8  sitcrc1;    /* SI1 RAM counter Tx TDMC */
0170     u8  sitdrc1;    /* SI1 RAM counter Tx TDMD */
0171     u8  sirarc1;    /* SI1 RAM counter Rx TDMA */
0172     u8  sirbrc1;    /* SI1 RAM counter Rx TDMB */
0173     u8  sircrc1;    /* SI1 RAM counter Rx TDMC */
0174     u8  sirdrc1;    /* SI1 RAM counter Rx TDMD */
0175     u8  res4[0x8];
0176     __be16  siemr1;     /* SI1 TDME mode register 16 bits */
0177     __be16  sifmr1;     /* SI1 TDMF mode register 16 bits */
0178     __be16  sigmr1;     /* SI1 TDMG mode register 16 bits */
0179     __be16  sihmr1;     /* SI1 TDMH mode register 16 bits */
0180     u8  siglmg1_l;  /* SI1 global mode register low 8 bits */
0181     u8  res5[0x1];
0182     u8  sicmdr1_l;  /* SI1 command register low 8 bits */
0183     u8  res6[0x1];
0184     u8  sistr1_l;   /* SI1 status register low 8 bits */
0185     u8  res7[0x1];
0186     __be16  sirsr1_l;   /* SI1 RAM shadow address register low 16 bits*/
0187     u8  siterc1;    /* SI1 RAM counter Tx TDME 8 bits */
0188     u8  sitfrc1;    /* SI1 RAM counter Tx TDMF 8 bits */
0189     u8  sitgrc1;    /* SI1 RAM counter Tx TDMG 8 bits */
0190     u8  sithrc1;    /* SI1 RAM counter Tx TDMH 8 bits */
0191     u8  sirerc1;    /* SI1 RAM counter Rx TDME 8 bits */
0192     u8  sirfrc1;    /* SI1 RAM counter Rx TDMF 8 bits */
0193     u8  sirgrc1;    /* SI1 RAM counter Rx TDMG 8 bits */
0194     u8  sirhrc1;    /* SI1 RAM counter Rx TDMH 8 bits */
0195     u8  res8[0x8];
0196     __be32  siml1;      /* SI1 multiframe limit register */
0197     u8  siedm1;     /* SI1 extended diagnostic mode register */
0198     u8  res9[0xBB];
0199 } __attribute__ ((packed));
0200 
0201 /* SI Routing Tables */
0202 struct sir {
0203     u8  tx[0x400];
0204     u8  rx[0x400];
0205     u8  res0[0x800];
0206 } __attribute__ ((packed));
0207 
0208 /* USB Controller */
0209 struct qe_usb_ctlr {
0210     u8  usb_usmod;
0211     u8  usb_usadr;
0212     u8  usb_uscom;
0213     u8  res1[1];
0214     __be16  usb_usep[4];
0215     u8  res2[4];
0216     __be16  usb_usber;
0217     u8  res3[2];
0218     __be16  usb_usbmr;
0219     u8  res4[1];
0220     u8  usb_usbs;
0221     __be16  usb_ussft;
0222     u8  res5[2];
0223     __be16  usb_usfrn;
0224     u8  res6[0x22];
0225 } __attribute__ ((packed));
0226 
0227 /* MCC */
0228 struct qe_mcc {
0229     __be32  mcce;       /* MCC event register */
0230     __be32  mccm;       /* MCC mask register */
0231     __be32  mccf;       /* MCC configuration register */
0232     __be32  merl;       /* MCC emergency request level register */
0233     u8  res0[0xF0];
0234 } __attribute__ ((packed));
0235 
0236 /* QE UCC Slow */
0237 struct ucc_slow {
0238     __be32  gumr_l;     /* UCCx general mode register (low) */
0239     __be32  gumr_h;     /* UCCx general mode register (high) */
0240     __be16  upsmr;      /* UCCx protocol-specific mode register */
0241     u8  res0[0x2];
0242     __be16  utodr;      /* UCCx transmit on demand register */
0243     __be16  udsr;       /* UCCx data synchronization register */
0244     __be16  ucce;       /* UCCx event register */
0245     u8  res1[0x2];
0246     __be16  uccm;       /* UCCx mask register */
0247     u8  res2[0x1];
0248     u8  uccs;       /* UCCx status register */
0249     u8  res3[0x24];
0250     __be16  utpt;
0251     u8  res4[0x52];
0252     u8  guemr;      /* UCC general extended mode register */
0253 } __attribute__ ((packed));
0254 
0255 /* QE UCC Fast */
0256 struct ucc_fast {
0257     __be32  gumr;       /* UCCx general mode register */
0258     __be32  upsmr;      /* UCCx protocol-specific mode register */
0259     __be16  utodr;      /* UCCx transmit on demand register */
0260     u8  res0[0x2];
0261     __be16  udsr;       /* UCCx data synchronization register */
0262     u8  res1[0x2];
0263     __be32  ucce;       /* UCCx event register */
0264     __be32  uccm;       /* UCCx mask register */
0265     u8  uccs;       /* UCCx status register */
0266     u8  res2[0x7];
0267     __be32  urfb;       /* UCC receive FIFO base */
0268     __be16  urfs;       /* UCC receive FIFO size */
0269     u8  res3[0x2];
0270     __be16  urfet;      /* UCC receive FIFO emergency threshold */
0271     __be16  urfset;     /* UCC receive FIFO special emergency
0272                    threshold */
0273     __be32  utfb;       /* UCC transmit FIFO base */
0274     __be16  utfs;       /* UCC transmit FIFO size */
0275     u8  res4[0x2];
0276     __be16  utfet;      /* UCC transmit FIFO emergency threshold */
0277     u8  res5[0x2];
0278     __be16  utftt;      /* UCC transmit FIFO transmit threshold */
0279     u8  res6[0x2];
0280     __be16  utpt;       /* UCC transmit polling timer */
0281     u8  res7[0x2];
0282     __be32  urtry;      /* UCC retry counter register */
0283     u8  res8[0x4C];
0284     u8  guemr;      /* UCC general extended mode register */
0285 } __attribute__ ((packed));
0286 
0287 struct ucc {
0288     union {
0289         struct  ucc_slow slow;
0290         struct  ucc_fast fast;
0291         u8  res[0x200]; /* UCC blocks are 512 bytes each */
0292     };
0293 } __attribute__ ((packed));
0294 
0295 /* MultiPHY UTOPIA POS Controllers (UPC) */
0296 struct upc {
0297     __be32  upgcr;      /* UTOPIA/POS general configuration register */
0298     __be32  uplpa;      /* UTOPIA/POS last PHY address */
0299     __be32  uphec;      /* ATM HEC register */
0300     __be32  upuc;       /* UTOPIA/POS UCC configuration */
0301     __be32  updc1;      /* UTOPIA/POS device 1 configuration */
0302     __be32  updc2;      /* UTOPIA/POS device 2 configuration */
0303     __be32  updc3;      /* UTOPIA/POS device 3 configuration */
0304     __be32  updc4;      /* UTOPIA/POS device 4 configuration */
0305     __be32  upstpa;     /* UTOPIA/POS STPA threshold */
0306     u8  res0[0xC];
0307     __be32  updrs1_h;   /* UTOPIA/POS device 1 rate select */
0308     __be32  updrs1_l;   /* UTOPIA/POS device 1 rate select */
0309     __be32  updrs2_h;   /* UTOPIA/POS device 2 rate select */
0310     __be32  updrs2_l;   /* UTOPIA/POS device 2 rate select */
0311     __be32  updrs3_h;   /* UTOPIA/POS device 3 rate select */
0312     __be32  updrs3_l;   /* UTOPIA/POS device 3 rate select */
0313     __be32  updrs4_h;   /* UTOPIA/POS device 4 rate select */
0314     __be32  updrs4_l;   /* UTOPIA/POS device 4 rate select */
0315     __be32  updrp1;     /* UTOPIA/POS device 1 receive priority low */
0316     __be32  updrp2;     /* UTOPIA/POS device 2 receive priority low */
0317     __be32  updrp3;     /* UTOPIA/POS device 3 receive priority low */
0318     __be32  updrp4;     /* UTOPIA/POS device 4 receive priority low */
0319     __be32  upde1;      /* UTOPIA/POS device 1 event */
0320     __be32  upde2;      /* UTOPIA/POS device 2 event */
0321     __be32  upde3;      /* UTOPIA/POS device 3 event */
0322     __be32  upde4;      /* UTOPIA/POS device 4 event */
0323     __be16  uprp1;
0324     __be16  uprp2;
0325     __be16  uprp3;
0326     __be16  uprp4;
0327     u8  res1[0x8];
0328     __be16  uptirr1_0;  /* Device 1 transmit internal rate 0 */
0329     __be16  uptirr1_1;  /* Device 1 transmit internal rate 1 */
0330     __be16  uptirr1_2;  /* Device 1 transmit internal rate 2 */
0331     __be16  uptirr1_3;  /* Device 1 transmit internal rate 3 */
0332     __be16  uptirr2_0;  /* Device 2 transmit internal rate 0 */
0333     __be16  uptirr2_1;  /* Device 2 transmit internal rate 1 */
0334     __be16  uptirr2_2;  /* Device 2 transmit internal rate 2 */
0335     __be16  uptirr2_3;  /* Device 2 transmit internal rate 3 */
0336     __be16  uptirr3_0;  /* Device 3 transmit internal rate 0 */
0337     __be16  uptirr3_1;  /* Device 3 transmit internal rate 1 */
0338     __be16  uptirr3_2;  /* Device 3 transmit internal rate 2 */
0339     __be16  uptirr3_3;  /* Device 3 transmit internal rate 3 */
0340     __be16  uptirr4_0;  /* Device 4 transmit internal rate 0 */
0341     __be16  uptirr4_1;  /* Device 4 transmit internal rate 1 */
0342     __be16  uptirr4_2;  /* Device 4 transmit internal rate 2 */
0343     __be16  uptirr4_3;  /* Device 4 transmit internal rate 3 */
0344     __be32  uper1;      /* Device 1 port enable register */
0345     __be32  uper2;      /* Device 2 port enable register */
0346     __be32  uper3;      /* Device 3 port enable register */
0347     __be32  uper4;      /* Device 4 port enable register */
0348     u8  res2[0x150];
0349 } __attribute__ ((packed));
0350 
0351 /* SDMA */
0352 struct sdma {
0353     __be32  sdsr;       /* Serial DMA status register */
0354     __be32  sdmr;       /* Serial DMA mode register */
0355     __be32  sdtr1;      /* SDMA system bus threshold register */
0356     __be32  sdtr2;      /* SDMA secondary bus threshold register */
0357     __be32  sdhy1;      /* SDMA system bus hysteresis register */
0358     __be32  sdhy2;      /* SDMA secondary bus hysteresis register */
0359     __be32  sdta1;      /* SDMA system bus address register */
0360     __be32  sdta2;      /* SDMA secondary bus address register */
0361     __be32  sdtm1;      /* SDMA system bus MSNUM register */
0362     __be32  sdtm2;      /* SDMA secondary bus MSNUM register */
0363     u8  res0[0x10];
0364     __be32  sdaqr;      /* SDMA address bus qualify register */
0365     __be32  sdaqmr;     /* SDMA address bus qualify mask register */
0366     u8  res1[0x4];
0367     __be32  sdebcr;     /* SDMA CAM entries base register */
0368     u8  res2[0x38];
0369 } __attribute__ ((packed));
0370 
0371 /* Debug Space */
0372 struct dbg {
0373     __be32  bpdcr;      /* Breakpoint debug command register */
0374     __be32  bpdsr;      /* Breakpoint debug status register */
0375     __be32  bpdmr;      /* Breakpoint debug mask register */
0376     __be32  bprmrr0;    /* Breakpoint request mode risc register 0 */
0377     __be32  bprmrr1;    /* Breakpoint request mode risc register 1 */
0378     u8  res0[0x8];
0379     __be32  bprmtr0;    /* Breakpoint request mode trb register 0 */
0380     __be32  bprmtr1;    /* Breakpoint request mode trb register 1 */
0381     u8  res1[0x8];
0382     __be32  bprmir;     /* Breakpoint request mode immediate register */
0383     __be32  bprmsr;     /* Breakpoint request mode serial register */
0384     __be32  bpemr;      /* Breakpoint exit mode register */
0385     u8  res2[0x48];
0386 } __attribute__ ((packed));
0387 
0388 /*
0389  * RISC Special Registers (Trap and Breakpoint).  These are described in
0390  * the QE Developer's Handbook.
0391  */
0392 struct rsp {
0393     __be32 tibcr[16];   /* Trap/instruction breakpoint control regs */
0394     u8 res0[64];
0395     __be32 ibcr0;
0396     __be32 ibs0;
0397     __be32 ibcnr0;
0398     u8 res1[4];
0399     __be32 ibcr1;
0400     __be32 ibs1;
0401     __be32 ibcnr1;
0402     __be32 npcr;
0403     __be32 dbcr;
0404     __be32 dbar;
0405     __be32 dbamr;
0406     __be32 dbsr;
0407     __be32 dbcnr;
0408     u8 res2[12];
0409     __be32 dbdr_h;
0410     __be32 dbdr_l;
0411     __be32 dbdmr_h;
0412     __be32 dbdmr_l;
0413     __be32 bsr;
0414     __be32 bor;
0415     __be32 bior;
0416     u8 res3[4];
0417     __be32 iatr[4];
0418     __be32 eccr;        /* Exception control configuration register */
0419     __be32 eicr;
0420     u8 res4[0x100-0xf8];
0421 } __attribute__ ((packed));
0422 
0423 struct qe_immap {
0424     struct qe_iram      iram;       /* I-RAM */
0425     struct qe_ic_regs   ic;     /* Interrupt Controller */
0426     struct cp_qe        cp;     /* Communications Processor */
0427     struct qe_mux       qmx;        /* QE Multiplexer */
0428     struct qe_timers    qet;        /* QE Timers */
0429     struct spi      spi[0x2];   /* spi */
0430     struct qe_mcc       mcc;        /* mcc */
0431     struct qe_brg       brg;        /* brg */
0432     struct qe_usb_ctlr  usb;        /* USB */
0433     struct si1      si1;        /* SI */
0434     u8          res11[0x800];
0435     struct sir      sir;        /* SI Routing Tables */
0436     struct ucc      ucc1;       /* ucc1 */
0437     struct ucc      ucc3;       /* ucc3 */
0438     struct ucc      ucc5;       /* ucc5 */
0439     struct ucc      ucc7;       /* ucc7 */
0440     u8          res12[0x600];
0441     struct upc      upc1;       /* MultiPHY UTOPIA POS Ctrlr 1*/
0442     struct ucc      ucc2;       /* ucc2 */
0443     struct ucc      ucc4;       /* ucc4 */
0444     struct ucc      ucc6;       /* ucc6 */
0445     struct ucc      ucc8;       /* ucc8 */
0446     u8          res13[0x600];
0447     struct upc      upc2;       /* MultiPHY UTOPIA POS Ctrlr 2*/
0448     struct sdma     sdma;       /* SDMA */
0449     struct dbg      dbg;        /* 0x104080 - 0x1040FF
0450                            Debug Space */
0451     struct rsp      rsp[0x2];   /* 0x104100 - 0x1042FF
0452                            RISC Special Registers
0453                            (Trap and Breakpoint) */
0454     u8          res14[0x300];   /* 0x104300 - 0x1045FF */
0455     u8          res15[0x3A00];  /* 0x104600 - 0x107FFF */
0456     u8          res16[0x8000];  /* 0x108000 - 0x110000 */
0457     u8          muram[0xC000];  /* 0x110000 - 0x11C000
0458                            Multi-user RAM */
0459     u8          res17[0x24000]; /* 0x11C000 - 0x140000 */
0460     u8          res18[0xC0000]; /* 0x140000 - 0x200000 */
0461 } __attribute__ ((packed));
0462 
0463 extern struct qe_immap __iomem *qe_immr;
0464 
0465 #endif /* __KERNEL__ */
0466 #endif /* _ASM_POWERPC_IMMAP_QE_H */
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