soc/fsl/cpm.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __CPM_H
0003 #define __CPM_H
0004
0005 #include <linux/compiler.h>
0006 #include <linux/types.h>
0007 #include <linux/errno.h>
0008 #include <linux/of.h>
0009 #include <soc/fsl/qe/qe.h>
0010
0011 /*
0012  * SPI Parameter RAM common to QE and CPM.
0013  */
0014 struct spi_pram {
0015     __be16  rbase;  /* Rx Buffer descriptor base address */
0016     __be16  tbase;  /* Tx Buffer descriptor base address */
0017     u8  rfcr;   /* Rx function code */
0018     u8  tfcr;   /* Tx function code */
0019     __be16  mrblr;  /* Max receive buffer length */
0020     __be32  rstate; /* Internal */
0021     __be32  rdp;    /* Internal */
0022     __be16  rbptr;  /* Internal */
0023     __be16  rbc;    /* Internal */
0024     __be32  rxtmp;  /* Internal */
0025     __be32  tstate; /* Internal */
0026     __be32  tdp;    /* Internal */
0027     __be16  tbptr;  /* Internal */
0028     __be16  tbc;    /* Internal */
0029     __be32  txtmp;  /* Internal */
0030     __be32  res;    /* Tx temp. */
0031     __be16  rpbase; /* Relocation pointer (CPM1 only) */
0032     __be16  res1;   /* Reserved */
0033 };
0034
0035 /*
0036  * USB Controller pram common to QE and CPM.
0037  */
0038 struct usb_ctlr {
0039     u8  usb_usmod;
0040     u8  usb_usadr;
0041     u8  usb_uscom;
0042     u8  res1[1];
0043     __be16  usb_usep[4];
0044     u8  res2[4];
0045     __be16  usb_usber;
0046     u8  res3[2];
0047     __be16  usb_usbmr;
0048     u8  res4[1];
0049     u8  usb_usbs;
0050     /* Fields down below are QE-only */
0051     __be16  usb_ussft;
0052     u8  res5[2];
0053     __be16  usb_usfrn;
0054     u8  res6[0x22];
0055 } __attribute__ ((packed));
0056
0057 /*
0058  * Function code bits, usually generic to devices.
0059  */
0060 #ifdef CONFIG_CPM1
0061 #define CPMFCR_GBL  ((u_char)0x00)  /* Flag doesn't exist in CPM1 */
0062 #define CPMFCR_TC2  ((u_char)0x00)  /* Flag doesn't exist in CPM1 */
0063 #define CPMFCR_DTB  ((u_char)0x00)  /* Flag doesn't exist in CPM1 */
0064 #define CPMFCR_BDB  ((u_char)0x00)  /* Flag doesn't exist in CPM1 */
0065 #else
0066 #define CPMFCR_GBL  ((u_char)0x20)  /* Set memory snooping */
0067 #define CPMFCR_TC2  ((u_char)0x04)  /* Transfer code 2 value */
0068 #define CPMFCR_DTB  ((u_char)0x02)  /* Use local bus for data when set */
0069 #define CPMFCR_BDB  ((u_char)0x01)  /* Use local bus for BD when set */
0070 #endif
0071 #define CPMFCR_EB   ((u_char)0x10)  /* Set big endian byte order */
0072
0073 /* Opcodes common to CPM1 and CPM2
0074 */
0075 #define CPM_CR_INIT_TRX     ((ushort)0x0000)
0076 #define CPM_CR_INIT_RX      ((ushort)0x0001)
0077 #define CPM_CR_INIT_TX      ((ushort)0x0002)
0078 #define CPM_CR_HUNT_MODE    ((ushort)0x0003)
0079 #define CPM_CR_STOP_TX      ((ushort)0x0004)
0080 #define CPM_CR_GRA_STOP_TX  ((ushort)0x0005)
0081 #define CPM_CR_RESTART_TX   ((ushort)0x0006)
0082 #define CPM_CR_CLOSE_RX_BD  ((ushort)0x0007)
0083 #define CPM_CR_SET_GADDR    ((ushort)0x0008)
0084 #define CPM_CR_SET_TIMER    ((ushort)0x0008)
0085 #define CPM_CR_STOP_IDMA    ((ushort)0x000b)
0086
0087 /* Buffer descriptors used by many of the CPM protocols. */
0088 typedef struct cpm_buf_desc {
0089     ushort  cbd_sc;     /* Status and Control */
0090     ushort  cbd_datlen; /* Data length in buffer */
0091     uint    cbd_bufaddr;    /* Buffer address in host memory */
0092 } cbd_t;
0093
0094 /* Buffer descriptor control/status used by serial
0095  */
0096
0097 #define BD_SC_EMPTY (0x8000)    /* Receive is empty */
0098 #define BD_SC_READY (0x8000)    /* Transmit is ready */
0099 #define BD_SC_WRAP  (0x2000)    /* Last buffer descriptor */
0100 #define BD_SC_INTRPT    (0x1000)    /* Interrupt on change */
0101 #define BD_SC_LAST  (0x0800)    /* Last buffer in frame */
0102 #define BD_SC_TC    (0x0400)    /* Transmit CRC */
0103 #define BD_SC_CM    (0x0200)    /* Continuous mode */
0104 #define BD_SC_ID    (0x0100)    /* Rec'd too many idles */
0105 #define BD_SC_P     (0x0100)    /* xmt preamble */
0106 #define BD_SC_BR    (0x0020)    /* Break received */
0107 #define BD_SC_FR    (0x0010)    /* Framing error */
0108 #define BD_SC_PR    (0x0008)    /* Parity error */
0109 #define BD_SC_NAK   (0x0004)    /* NAK - did not respond */
0110 #define BD_SC_OV    (0x0002)    /* Overrun */
0111 #define BD_SC_UN    (0x0002)    /* Underrun */
0112 #define BD_SC_CD    (0x0001)    /* */
0113 #define BD_SC_CL    (0x0001)    /* Collision */
0114
0115 /* Buffer descriptor control/status used by Ethernet receive.
0116  * Common to SCC and FCC.
0117  */
0118 #define BD_ENET_RX_EMPTY    (0x8000)
0119 #define BD_ENET_RX_WRAP     (0x2000)
0120 #define BD_ENET_RX_INTR     (0x1000)
0121 #define BD_ENET_RX_LAST     (0x0800)
0122 #define BD_ENET_RX_FIRST    (0x0400)
0123 #define BD_ENET_RX_MISS     (0x0100)
0124 #define BD_ENET_RX_BC       (0x0080)    /* FCC Only */
0125 #define BD_ENET_RX_MC       (0x0040)    /* FCC Only */
0126 #define BD_ENET_RX_LG       (0x0020)
0127 #define BD_ENET_RX_NO       (0x0010)
0128 #define BD_ENET_RX_SH       (0x0008)
0129 #define BD_ENET_RX_CR       (0x0004)
0130 #define BD_ENET_RX_OV       (0x0002)
0131 #define BD_ENET_RX_CL       (0x0001)
0132 #define BD_ENET_RX_STATS    (0x01ff)    /* All status bits */
0133
0134 /* Buffer descriptor control/status used by Ethernet transmit.
0135  * Common to SCC and FCC.
0136  */
0137 #define BD_ENET_TX_READY    (0x8000)
0138 #define BD_ENET_TX_PAD      (0x4000)
0139 #define BD_ENET_TX_WRAP     (0x2000)
0140 #define BD_ENET_TX_INTR     (0x1000)
0141 #define BD_ENET_TX_LAST     (0x0800)
0142 #define BD_ENET_TX_TC       (0x0400)
0143 #define BD_ENET_TX_DEF      (0x0200)
0144 #define BD_ENET_TX_HB       (0x0100)
0145 #define BD_ENET_TX_LC       (0x0080)
0146 #define BD_ENET_TX_RL       (0x0040)
0147 #define BD_ENET_TX_RCMASK   (0x003c)
0148 #define BD_ENET_TX_UN       (0x0002)
0149 #define BD_ENET_TX_CSL      (0x0001)
0150 #define BD_ENET_TX_STATS    (0x03ff)    /* All status bits */
0151
0152 /* Buffer descriptor control/status used by Transparent mode SCC.
0153  */
0154 #define BD_SCC_TX_LAST      (0x0800)
0155
0156 /* Buffer descriptor control/status used by I2C.
0157  */
0158 #define BD_I2C_START        (0x0400)
0159
0160 #ifdef CONFIG_CPM
0161 int cpm_command(u32 command, u8 opcode);
0162 #else
0163 static inline int cpm_command(u32 command, u8 opcode)
0164 {
0165     return -ENOSYS;
0166 }
0167 #endif /* CONFIG_CPM */
0168
0169 int cpm2_gpiochip_add32(struct device *dev);
0170
0171 #endif