soc/at91/sama7-sfrbu.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Microchip SAMA7 SFRBU registers offsets and bit definitions.
0004  *
0005  * Copyright (C) [2020] Microchip Technology Inc. and its subsidiaries
0006  *
0007  * Author: Claudu Beznea <claudiu.beznea@microchip.com>
0008  */
0009
0010 #ifndef __SAMA7_SFRBU_H__
0011 #define __SAMA7_SFRBU_H__
0012
0013 #ifdef CONFIG_SOC_SAMA7
0014
0015 #define AT91_SFRBU_PSWBU            (0x00)      /* SFRBU Power Switch BU Control Register */
0016 #define     AT91_SFRBU_PSWBU_PSWKEY     (0x4BD20C << 8) /* Specific value mandatory to allow writing of other register bits */
0017 #define     AT91_SFRBU_PSWBU_STATE      (1 << 2)    /* Power switch BU state */
0018 #define     AT91_SFRBU_PSWBU_SOFTSWITCH (1 << 1)    /* Power switch BU source selection */
0019 #define     AT91_SFRBU_PSWBU_CTRL       (1 << 0)    /* Power switch BU control */
0020
0021 #define AT91_SFRBU_25LDOCR          (0x0C)      /* SFRBU 2.5V LDO Control Register */
0022 #define     AT91_SFRBU_25LDOCR_LDOANAKEY    (0x3B6E18 << 8) /* Specific value mandatory to allow writing of other register bits. */
0023 #define     AT91_SFRBU_25LDOCR_STATE    (1 << 3)    /* LDOANA Switch On/Off Control */
0024 #define     AT91_SFRBU_25LDOCR_LP       (1 << 2)    /* LDOANA Low-Power Mode Control */
0025 #define     AT91_SFRBU_PD_VALUE_MSK     (0x3)
0026 #define     AT91_SFRBU_25LDOCR_PD_VALUE(v)  ((v) & AT91_SFRBU_PD_VALUE_MSK) /* LDOANA Pull-down value */
0027
0028 #define AT91_FRBU_DDRPWR            (0x10)      /* SFRBU DDR Power Control Register */
0029 #define     AT91_FRBU_DDRPWR_STATE      (1 << 0)    /* DDR Power Mode State */
0030
0031 #endif /* CONFIG_SOC_SAMA7 */
0032
0033 #endif /* __SAMA7_SFRBU_H__ */
0034