soc/at91/sama7-ddr.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Microchip SAMA7 UDDR Controller and DDR3 PHY Controller registers offsets
0004  * and bit definitions.
0005  *
0006  * Copyright (C) [2020] Microchip Technology Inc. and its subsidiaries
0007  *
0008  * Author: Claudu Beznea <claudiu.beznea@microchip.com>
0009  */
0010
0011 #ifndef __SAMA7_DDR_H__
0012 #define __SAMA7_DDR_H__
0013
0014 /* DDR3PHY */
0015 #define DDR3PHY_PIR             (0x04)      /* DDR3PHY PHY Initialization Register  */
0016 #define DDR3PHY_PIR_DLLBYP          (1 << 17)   /* DLL Bypass */
0017 #define     DDR3PHY_PIR_ITMSRST     (1 << 4)    /* Interface Timing Module Soft Reset */
0018 #define DDR3PHY_PIR_DLLLOCK         (1 << 2)    /* DLL Lock */
0019 #define     DDR3PHY_PIR_DLLSRST     (1 << 1)    /* DLL Soft Rest */
0020 #define DDR3PHY_PIR_INIT            (1 << 0)    /* Initialization Trigger */
0021
0022 #define DDR3PHY_PGCR                (0x08)      /* DDR3PHY PHY General Configuration Register */
0023 #define     DDR3PHY_PGCR_CKDV1      (1 << 13)   /* CK# Disable Value */
0024 #define     DDR3PHY_PGCR_CKDV0      (1 << 12)   /* CK Disable Value */
0025
0026 #define DDR3PHY_PGSR                (0x0C)      /* DDR3PHY PHY General Status Register */
0027 #define     DDR3PHY_PGSR_IDONE      (1 << 0)    /* Initialization Done */
0028
0029 #define DDR3PHY_ACIOCR              (0x24)      /*  DDR3PHY AC I/O Configuration Register */
0030 #define     DDR3PHY_ACIOCR_CSPDD_CS0    (1 << 18)   /* CS#[0] Power Down Driver */
0031 #define     DDR3PHY_ACIOCR_CKPDD_CK0    (1 << 8)    /* CK[0] Power Down Driver */
0032 #define     DDR3PHY_ACIORC_ACPDD        (1 << 3)    /* AC Power Down Driver */
0033
0034 #define DDR3PHY_DXCCR               (0x28)      /* DDR3PHY DATX8 Common Configuration Register */
0035 #define     DDR3PHY_DXCCR_DXPDR     (1 << 3)    /* Data Power Down Receiver */
0036
0037 #define DDR3PHY_DSGCR               (0x2C)      /* DDR3PHY DDR System General Configuration Register */
0038 #define     DDR3PHY_DSGCR_ODTPDD_ODT0   (1 << 20)   /* ODT[0] Power Down Driver */
0039
0040 #define DDR3PHY_ZQ0SR0              (0x188)     /* ZQ status register 0 */
0041 #define DDR3PHY_ZQ0SR0_PDO_OFF          (0)     /* Pull-down output impedance select offset */
0042 #define DDR3PHY_ZQ0SR0_PUO_OFF          (5)     /* Pull-up output impedance select offset */
0043 #define DDR3PHY_ZQ0SR0_PDODT_OFF        (10)        /* Pull-down on-die termination impedance select offset */
0044 #define DDR3PHY_ZQ0SRO_PUODT_OFF        (15)        /* Pull-up on-die termination impedance select offset */
0045
0046 #define DDR3PHY_DX0DLLCR            (0x1CC)     /* DDR3PHY DATX8 DLL Control Register */
0047 #define DDR3PHY_DX1DLLCR            (0x20C)     /* DDR3PHY DATX8 DLL Control Register */
0048 #define     DDR3PHY_DXDLLCR_DLLDIS      (1 << 31)   /* DLL Disable */
0049
0050 /* UDDRC */
0051 #define UDDRC_STAT              (0x04)      /* UDDRC Operating Mode Status Register */
0052 #define     UDDRC_STAT_SELFREF_TYPE_DIS (0x0 << 4)  /* SDRAM is not in Self-refresh */
0053 #define     UDDRC_STAT_SELFREF_TYPE_PHY (0x1 << 4)  /* SDRAM is in Self-refresh, which was caused by PHY Master Request */
0054 #define     UDDRC_STAT_SELFREF_TYPE_SW  (0x2 << 4)  /* SDRAM is in Self-refresh, which was not caused solely under Automatic Self-refresh control */
0055 #define     UDDRC_STAT_SELFREF_TYPE_AUTO    (0x3 << 4)  /* SDRAM is in Self-refresh, which was caused by Automatic Self-refresh only */
0056 #define     UDDRC_STAT_SELFREF_TYPE_MSK (0x3 << 4)  /* Self-refresh type mask */
0057 #define     UDDRC_STAT_OPMODE_INIT      (0x0 << 0)  /* Init */
0058 #define     UDDRC_STAT_OPMODE_NORMAL    (0x1 << 0)  /* Normal */
0059 #define     UDDRC_STAT_OPMODE_PWRDOWN   (0x2 << 0)  /* Power-down */
0060 #define     UDDRC_STAT_OPMODE_SELF_REFRESH  (0x3 << 0)  /* Self-refresh */
0061 #define     UDDRC_STAT_OPMODE_MSK       (0x7 << 0)  /* Operating mode mask */
0062
0063 #define UDDRC_PWRCTL                (0x30)      /* UDDRC Low Power Control Register */
0064 #define     UDDRC_PWRCTL_SELFREF_EN     (1 << 0)    /* Automatic self-refresh */
0065 #define     UDDRC_PWRCTL_SELFREF_SW     (1 << 5)    /* Software self-refresh */
0066
0067 #define UDDRC_DFIMISC               (0x1B0)     /* UDDRC DFI Miscellaneous Control Register */
0068 #define     UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN (1 << 0) /* PHY initialization complete enable signal */
0069
0070 #define UDDRC_SWCTRL                (0x320)     /* UDDRC Software Register Programming Control Enable */
0071 #define     UDDRC_SWCTRL_SW_DONE        (1 << 0)    /* Enable quasi-dynamic register programming outside reset */
0072
0073 #define UDDRC_SWSTAT                (0x324)     /* UDDRC Software Register Programming Control Status */
0074 #define     UDDRC_SWSTAT_SW_DONE_ACK    (1 << 0)    /* Register programming done */
0075
0076 #define UDDRC_PSTAT             (0x3FC)     /* UDDRC Port Status Register */
0077 #define UDDRC_PSTAT_ALL_PORTS           (0x1F001F)  /* Read + writes outstanding transactions on all ports */
0078
0079 #define UDDRC_PCTRL_0               (0x490)     /* UDDRC Port 0 Control Register */
0080 #define UDDRC_PCTRL_1               (0x540)     /* UDDRC Port 1 Control Register */
0081 #define UDDRC_PCTRL_2               (0x5F0)     /* UDDRC Port 2 Control Register */
0082 #define UDDRC_PCTRL_3               (0x6A0)     /* UDDRC Port 3 Control Register */
0083 #define UDDRC_PCTRL_4               (0x750)     /* UDDRC Port 4 Control Register */
0084
0085 #endif /* __SAMA7_DDR_H__ */