soc/at91/at91sam9_sdramc.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
0004  *
0005  * Copyright (C) 2007 Andrew Victor
0006  * Copyright (C) 2007 Atmel Corporation.
0007  *
0008  * SDRAM Controllers (SDRAMC) - System peripherals registers.
0009  * Based on AT91SAM9261 datasheet revision D.
0010  */
0011
0012 #ifndef AT91SAM9_SDRAMC_H
0013 #define AT91SAM9_SDRAMC_H
0014
0015 /* SDRAM Controller (SDRAMC) registers */
0016 #define AT91_SDRAMC_MR      0x00    /* SDRAM Controller Mode Register */
0017 #define     AT91_SDRAMC_MODE    (0xf << 0)      /* Command Mode */
0018 #define         AT91_SDRAMC_MODE_NORMAL     0
0019 #define         AT91_SDRAMC_MODE_NOP        1
0020 #define         AT91_SDRAMC_MODE_PRECHARGE  2
0021 #define         AT91_SDRAMC_MODE_LMR        3
0022 #define         AT91_SDRAMC_MODE_REFRESH    4
0023 #define         AT91_SDRAMC_MODE_EXT_LMR    5
0024 #define         AT91_SDRAMC_MODE_DEEP       6
0025
0026 #define AT91_SDRAMC_TR      0x04    /* SDRAM Controller Refresh Timer Register */
0027 #define     AT91_SDRAMC_COUNT   (0xfff << 0)        /* Refresh Timer Counter */
0028
0029 #define AT91_SDRAMC_CR      0x08    /* SDRAM Controller Configuration Register */
0030 #define     AT91_SDRAMC_NC      (3 << 0)        /* Number of Column Bits */
0031 #define         AT91_SDRAMC_NC_8    (0 << 0)
0032 #define         AT91_SDRAMC_NC_9    (1 << 0)
0033 #define         AT91_SDRAMC_NC_10   (2 << 0)
0034 #define         AT91_SDRAMC_NC_11   (3 << 0)
0035 #define     AT91_SDRAMC_NR      (3 << 2)        /* Number of Row Bits */
0036 #define         AT91_SDRAMC_NR_11   (0 << 2)
0037 #define         AT91_SDRAMC_NR_12   (1 << 2)
0038 #define         AT91_SDRAMC_NR_13   (2 << 2)
0039 #define     AT91_SDRAMC_NB      (1 << 4)        /* Number of Banks */
0040 #define         AT91_SDRAMC_NB_2    (0 << 4)
0041 #define         AT91_SDRAMC_NB_4    (1 << 4)
0042 #define     AT91_SDRAMC_CAS     (3 << 5)        /* CAS Latency */
0043 #define         AT91_SDRAMC_CAS_1   (1 << 5)
0044 #define         AT91_SDRAMC_CAS_2   (2 << 5)
0045 #define         AT91_SDRAMC_CAS_3   (3 << 5)
0046 #define     AT91_SDRAMC_DBW     (1 << 7)        /* Data Bus Width */
0047 #define         AT91_SDRAMC_DBW_32  (0 << 7)
0048 #define         AT91_SDRAMC_DBW_16  (1 << 7)
0049 #define     AT91_SDRAMC_TWR     (0xf <<  8)     /* Write Recovery Delay */
0050 #define     AT91_SDRAMC_TRC     (0xf << 12)     /* Row Cycle Delay */
0051 #define     AT91_SDRAMC_TRP     (0xf << 16)     /* Row Precharge Delay */
0052 #define     AT91_SDRAMC_TRCD    (0xf << 20)     /* Row to Column Delay */
0053 #define     AT91_SDRAMC_TRAS    (0xf << 24)     /* Active to Precharge Delay */
0054 #define     AT91_SDRAMC_TXSR    (0xf << 28)     /* Exit Self Refresh to Active Delay */
0055
0056 #define AT91_SDRAMC_LPR     0x10    /* SDRAM Controller Low Power Register */
0057 #define     AT91_SDRAMC_LPCB        (3 << 0)    /* Low-power Configurations */
0058 #define         AT91_SDRAMC_LPCB_DISABLE        0
0059 #define         AT91_SDRAMC_LPCB_SELF_REFRESH       1
0060 #define         AT91_SDRAMC_LPCB_POWER_DOWN     2
0061 #define         AT91_SDRAMC_LPCB_DEEP_POWER_DOWN    3
0062 #define     AT91_SDRAMC_PASR        (7 << 4)    /* Partial Array Self Refresh */
0063 #define     AT91_SDRAMC_TCSR        (3 << 8)    /* Temperature Compensated Self Refresh */
0064 #define     AT91_SDRAMC_DS          (3 << 10)   /* Drive Strength */
0065 #define     AT91_SDRAMC_TIMEOUT     (3 << 12)   /* Time to define when Low Power Mode is enabled */
0066 #define         AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES    (0 << 12)
0067 #define         AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES   (1 << 12)
0068 #define         AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES  (2 << 12)
0069
0070 #define AT91_SDRAMC_IER     0x14    /* SDRAM Controller Interrupt Enable Register */
0071 #define AT91_SDRAMC_IDR     0x18    /* SDRAM Controller Interrupt Disable Register */
0072 #define AT91_SDRAMC_IMR     0x1C    /* SDRAM Controller Interrupt Mask Register */
0073 #define AT91_SDRAMC_ISR     0x20    /* SDRAM Controller Interrupt Status Register */
0074 #define     AT91_SDRAMC_RES     (1 << 0)        /* Refresh Error Status */
0075
0076 #define AT91_SDRAMC_MDR     0x24    /* SDRAM Memory Device Register */
0077 #define     AT91_SDRAMC_MD      (3 << 0)        /* Memory Device Type */
0078 #define         AT91_SDRAMC_MD_SDRAM        0
0079 #define         AT91_SDRAMC_MD_LOW_POWER_SDRAM  1
0080
0081 #endif