soc/at91/at91sam9_ddrsdr.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Header file for the Atmel DDR/SDR SDRAM Controller
0004  *
0005  * Copyright (C) 2010 Atmel Corporation
0006  *  Nicolas Ferre <nicolas.ferre@atmel.com>
0007  */
0008 #ifndef AT91SAM9_DDRSDR_H
0009 #define AT91SAM9_DDRSDR_H
0010
0011 #define AT91_DDRSDRC_MR     0x00    /* Mode Register */
0012 #define     AT91_DDRSDRC_MODE   (0x7 << 0)      /* Command Mode */
0013 #define         AT91_DDRSDRC_MODE_NORMAL    0
0014 #define         AT91_DDRSDRC_MODE_NOP       1
0015 #define         AT91_DDRSDRC_MODE_PRECHARGE 2
0016 #define         AT91_DDRSDRC_MODE_LMR       3
0017 #define         AT91_DDRSDRC_MODE_REFRESH   4
0018 #define         AT91_DDRSDRC_MODE_EXT_LMR   5
0019 #define         AT91_DDRSDRC_MODE_DEEP      6
0020
0021 #define AT91_DDRSDRC_RTR    0x04    /* Refresh Timer Register */
0022 #define     AT91_DDRSDRC_COUNT  (0xfff << 0)        /* Refresh Timer Counter */
0023
0024 #define AT91_DDRSDRC_CR     0x08    /* Configuration Register */
0025 #define     AT91_DDRSDRC_NC     (3 << 0)        /* Number of Column Bits */
0026 #define         AT91_DDRSDRC_NC_SDR8    (0 << 0)
0027 #define         AT91_DDRSDRC_NC_SDR9    (1 << 0)
0028 #define         AT91_DDRSDRC_NC_SDR10   (2 << 0)
0029 #define         AT91_DDRSDRC_NC_SDR11   (3 << 0)
0030 #define         AT91_DDRSDRC_NC_DDR9    (0 << 0)
0031 #define         AT91_DDRSDRC_NC_DDR10   (1 << 0)
0032 #define         AT91_DDRSDRC_NC_DDR11   (2 << 0)
0033 #define         AT91_DDRSDRC_NC_DDR12   (3 << 0)
0034 #define     AT91_DDRSDRC_NR     (3 << 2)        /* Number of Row Bits */
0035 #define         AT91_DDRSDRC_NR_11  (0 << 2)
0036 #define         AT91_DDRSDRC_NR_12  (1 << 2)
0037 #define         AT91_DDRSDRC_NR_13  (2 << 2)
0038 #define         AT91_DDRSDRC_NR_14  (3 << 2)
0039 #define     AT91_DDRSDRC_CAS    (7 << 4)        /* CAS Latency */
0040 #define         AT91_DDRSDRC_CAS_2  (2 << 4)
0041 #define         AT91_DDRSDRC_CAS_3  (3 << 4)
0042 #define         AT91_DDRSDRC_CAS_25 (6 << 4)
0043 #define     AT91_DDRSDRC_RST_DLL    (1 << 7)        /* Reset DLL */
0044 #define     AT91_DDRSDRC_DICDS  (1 << 8)        /* Output impedance control */
0045 #define     AT91_DDRSDRC_DIS_DLL    (1 << 9)        /* Disable DLL [SAM9 Only] */
0046 #define     AT91_DDRSDRC_OCD    (1 << 12)       /* Off-Chip Driver [SAM9 Only] */
0047 #define     AT91_DDRSDRC_DQMS   (1 << 16)       /* Mask Data is Shared [SAM9 Only] */
0048 #define     AT91_DDRSDRC_ACTBST (1 << 18)       /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */
0049
0050 #define AT91_DDRSDRC_T0PR   0x0C    /* Timing 0 Register */
0051 #define     AT91_DDRSDRC_TRAS   (0xf <<  0)     /* Active to Precharge delay */
0052 #define     AT91_DDRSDRC_TRCD   (0xf <<  4)     /* Row to Column delay */
0053 #define     AT91_DDRSDRC_TWR    (0xf <<  8)     /* Write recovery delay */
0054 #define     AT91_DDRSDRC_TRC    (0xf << 12)     /* Row cycle delay */
0055 #define     AT91_DDRSDRC_TRP    (0xf << 16)     /* Row precharge delay */
0056 #define     AT91_DDRSDRC_TRRD   (0xf << 20)     /* Active BankA to BankB */
0057 #define     AT91_DDRSDRC_TWTR   (0x7 << 24)     /* Internal Write to Read delay */
0058 #define     AT91_DDRSDRC_RED_WRRD   (0x1 << 27)     /* Reduce Write to Read Delay [SAM9 Only] */
0059 #define     AT91_DDRSDRC_TMRD   (0xf << 28)     /* Load mode to active/refresh delay */
0060
0061 #define AT91_DDRSDRC_T1PR   0x10    /* Timing 1 Register */
0062 #define     AT91_DDRSDRC_TRFC   (0x1f << 0)     /* Row Cycle Delay */
0063 #define     AT91_DDRSDRC_TXSNR  (0xff << 8)     /* Exit self-refresh to non-read */
0064 #define     AT91_DDRSDRC_TXSRD  (0xff << 16)        /* Exit self-refresh to read */
0065 #define     AT91_DDRSDRC_TXP    (0xf  << 24)        /* Exit power-down delay */
0066
0067 #define AT91_DDRSDRC_T2PR   0x14    /* Timing 2 Register [SAM9 Only] */
0068 #define     AT91_DDRSDRC_TXARD  (0xf  << 0)     /* Exit active power down delay to read command in mode "Fast Exit" */
0069 #define     AT91_DDRSDRC_TXARDS (0xf  << 4)     /* Exit active power down delay to read command in mode "Slow Exit" */
0070 #define     AT91_DDRSDRC_TRPA   (0xf  << 8)     /* Row Precharge All delay */
0071 #define     AT91_DDRSDRC_TRTP   (0x7  << 12)        /* Read to Precharge delay */
0072
0073 #define AT91_DDRSDRC_LPR    0x1C    /* Low Power Register */
0074 #define     AT91_DDRSDRC_LPCB   (3 << 0)        /* Low-power Configurations */
0075 #define         AT91_DDRSDRC_LPCB_DISABLE       0
0076 #define         AT91_DDRSDRC_LPCB_SELF_REFRESH      1
0077 #define         AT91_DDRSDRC_LPCB_POWER_DOWN        2
0078 #define         AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN   3
0079 #define     AT91_DDRSDRC_CLKFR  (1 << 2)    /* Clock Frozen */
0080 #define     AT91_DDRSDRC_LPDDR2_PWOFF   (1 << 3)    /* LPDDR Power Off */
0081 #define     AT91_DDRSDRC_PASR   (7 << 4)    /* Partial Array Self Refresh */
0082 #define     AT91_DDRSDRC_TCSR   (3 << 8)    /* Temperature Compensated Self Refresh */
0083 #define     AT91_DDRSDRC_DS     (3 << 10)   /* Drive Strength */
0084 #define     AT91_DDRSDRC_TIMEOUT    (3 << 12)   /* Time to define when Low Power Mode is enabled */
0085 #define         AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES   (0 << 12)
0086 #define         AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES  (1 << 12)
0087 #define         AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
0088 #define     AT91_DDRSDRC_APDE   (1 << 16)    /* Active power down exit time */
0089 #define     AT91_DDRSDRC_UPD_MR (3 << 20)    /* Update load mode register and extended mode register */
0090
0091 #define AT91_DDRSDRC_MDR    0x20    /* Memory Device Register */
0092 #define     AT91_DDRSDRC_MD     (7 << 0)    /* Memory Device Type */
0093 #define         AT91_DDRSDRC_MD_SDR     0
0094 #define         AT91_DDRSDRC_MD_LOW_POWER_SDR   1
0095 #define         AT91_DDRSDRC_MD_LOW_POWER_DDR   3
0096 #define         AT91_DDRSDRC_MD_LPDDR3      5
0097 #define         AT91_DDRSDRC_MD_DDR2        6   /* [SAM9 Only] */
0098 #define         AT91_DDRSDRC_MD_LPDDR2      7
0099 #define     AT91_DDRSDRC_DBW    (1 << 4)        /* Data Bus Width */
0100 #define         AT91_DDRSDRC_DBW_32BITS     (0 <<  4)
0101 #define         AT91_DDRSDRC_DBW_16BITS     (1 <<  4)
0102
0103 #define AT91_DDRSDRC_DLL    0x24    /* DLL Information Register */
0104 #define     AT91_DDRSDRC_MDINC  (1 << 0)        /* Master Delay increment */
0105 #define     AT91_DDRSDRC_MDDEC  (1 << 1)        /* Master Delay decrement */
0106 #define     AT91_DDRSDRC_MDOVF  (1 << 2)        /* Master Delay Overflow */
0107 #define     AT91_DDRSDRC_MDVAL  (0xff <<  8)        /* Master Delay value */
0108
0109 #define AT91_DDRSDRC_HS     0x2C    /* High Speed Register [SAM9 Only] */
0110 #define     AT91_DDRSDRC_DIS_ATCP_RD    (1 << 2)    /* Anticip read access is disabled */
0111
0112 #define AT91_DDRSDRC_DELAY(n)   (0x30 + (0x4 * (n)))    /* Delay I/O Register n */
0113
0114 #define AT91_DDRSDRC_WPMR   0xE4    /* Write Protect Mode Register [SAM9 Only] */
0115 #define     AT91_DDRSDRC_WP     (1 << 0)        /* Write protect enable */
0116 #define     AT91_DDRSDRC_WPKEY  (0xffffff << 8)     /* Write protect key */
0117 #define     AT91_DDRSDRC_KEY    (0x444452 << 8)     /* Write protect key = "DDR" */
0118
0119 #define AT91_DDRSDRC_WPSR   0xE8    /* Write Protect Status Register [SAM9 Only] */
0120 #define     AT91_DDRSDRC_WPVS   (1 << 0)        /* Write protect violation status */
0121 #define     AT91_DDRSDRC_WPVSRC (0xffff << 8)       /* Write protect violation source */
0122
0123 #endif