soc/arc/timers.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
0004  */
0005
0006 #ifndef __SOC_ARC_TIMERS_H
0007 #define __SOC_ARC_TIMERS_H
0008
0009 #include <soc/arc/aux.h>
0010
0011 /* Timer related Aux registers */
0012 #define ARC_REG_TIMER0_LIMIT    0x23    /* timer 0 limit */
0013 #define ARC_REG_TIMER0_CTRL 0x22    /* timer 0 control */
0014 #define ARC_REG_TIMER0_CNT  0x21    /* timer 0 count */
0015 #define ARC_REG_TIMER1_LIMIT    0x102   /* timer 1 limit */
0016 #define ARC_REG_TIMER1_CTRL 0x101   /* timer 1 control */
0017 #define ARC_REG_TIMER1_CNT  0x100   /* timer 1 count */
0018
0019 /* CTRL reg bits */
0020 #define ARC_TIMER_CTRL_IE   (1 << 0) /* Interrupt when Count reaches limit */
0021 #define ARC_TIMER_CTRL_NH   (1 << 1) /* Count only when CPU NOT halted */
0022
0023 #define ARC_TIMERN_MAX      0xFFFFFFFF
0024
0025 #define ARC_REG_TIMERS_BCR  0x75
0026
0027 struct bcr_timer {
0028 #ifdef CONFIG_CPU_BIG_ENDIAN
0029     unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8;
0030 #else
0031     unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15;
0032 #endif
0033 };
0034
0035 #endif