soc/arc/mcip.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * ARConnect IP Support (Multi core enabler: Cross core IPI, RTC ...)
0004  *
0005  * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
0006  */
0007
0008 #ifndef __SOC_ARC_MCIP_H
0009 #define __SOC_ARC_MCIP_H
0010
0011 #include <soc/arc/aux.h>
0012
0013 #define ARC_REG_MCIP_BCR    0x0d0
0014 #define ARC_REG_MCIP_IDU_BCR    0x0D5
0015 #define ARC_REG_GFRC_BUILD  0x0D6
0016 #define ARC_REG_MCIP_CMD    0x600
0017 #define ARC_REG_MCIP_WDATA  0x601
0018 #define ARC_REG_MCIP_READBACK   0x602
0019
0020 struct mcip_cmd {
0021 #ifdef CONFIG_CPU_BIG_ENDIAN
0022     unsigned int pad:8, param:16, cmd:8;
0023 #else
0024     unsigned int cmd:8, param:16, pad:8;
0025 #endif
0026
0027 #define CMD_INTRPT_GENERATE_IRQ     0x01
0028 #define CMD_INTRPT_GENERATE_ACK     0x02
0029 #define CMD_INTRPT_READ_STATUS      0x03
0030 #define CMD_INTRPT_CHECK_SOURCE     0x04
0031
0032 /* Semaphore Commands */
0033 #define CMD_SEMA_CLAIM_AND_READ     0x11
0034 #define CMD_SEMA_RELEASE        0x12
0035
0036 #define CMD_DEBUG_SET_MASK      0x34
0037 #define CMD_DEBUG_READ_MASK     0x35
0038 #define CMD_DEBUG_SET_SELECT        0x36
0039 #define CMD_DEBUG_READ_SELECT       0x37
0040
0041 #define CMD_GFRC_READ_LO        0x42
0042 #define CMD_GFRC_READ_HI        0x43
0043 #define CMD_GFRC_SET_CORE       0x47
0044 #define CMD_GFRC_READ_CORE      0x48
0045
0046 #define CMD_IDU_ENABLE          0x71
0047 #define CMD_IDU_DISABLE         0x72
0048 #define CMD_IDU_SET_MODE        0x74
0049 #define CMD_IDU_READ_MODE       0x75
0050 #define CMD_IDU_SET_DEST        0x76
0051 #define CMD_IDU_ACK_CIRQ        0x79
0052 #define CMD_IDU_SET_MASK        0x7C
0053
0054 #define IDU_M_TRIG_LEVEL        0x0
0055 #define IDU_M_TRIG_EDGE         0x1
0056
0057 #define IDU_M_DISTRI_RR         0x0
0058 #define IDU_M_DISTRI_DEST       0x2
0059 };
0060
0061 struct mcip_bcr {
0062 #ifdef CONFIG_CPU_BIG_ENDIAN
0063         unsigned int pad4:6, pw_dom:1, pad3:1,
0064                  idu:1, pad2:1, num_cores:6,
0065                  pad:1,  gfrc:1, dbg:1, pw:1,
0066                  msg:1, sem:1, ipi:1, slv:1,
0067                  ver:8;
0068 #else
0069         unsigned int ver:8,
0070                  slv:1, ipi:1, sem:1, msg:1,
0071                  pw:1, dbg:1, gfrc:1, pad:1,
0072                  num_cores:6, pad2:1, idu:1,
0073                  pad3:1, pw_dom:1, pad4:6;
0074 #endif
0075 };
0076
0077 struct mcip_idu_bcr {
0078 #ifdef CONFIG_CPU_BIG_ENDIAN
0079     unsigned int pad:21, cirqnum:3, ver:8;
0080 #else
0081     unsigned int ver:8, cirqnum:3, pad:21;
0082 #endif
0083 };
0084
0085
0086 /*
0087  * Build register for IDU contains not an actual number of supported common
0088  * interrupts but an exponent of 2 which must be multiplied by 4 to
0089  * get a number of supported common interrupts.
0090  */
0091 #define mcip_idu_bcr_to_nr_irqs(bcr) (4 * (1 << (bcr).cirqnum))
0092
0093 /*
0094  * MCIP programming model
0095  *
0096  * - Simple commands write {cmd:8,param:16} to MCIP_CMD aux reg
0097  *   (param could be irq, common_irq, core_id ...)
0098  * - More involved commands setup MCIP_WDATA with cmd specific data
0099  *   before invoking the simple command
0100  */
0101 static inline void __mcip_cmd(unsigned int cmd, unsigned int param)
0102 {
0103     struct mcip_cmd buf;
0104
0105     buf.pad = 0;
0106     buf.cmd = cmd;
0107     buf.param = param;
0108
0109     WRITE_AUX(ARC_REG_MCIP_CMD, buf);
0110 }
0111
0112 /*
0113  * Setup additional data for a cmd
0114  * Callers need to lock to ensure atomicity
0115  */
0116 static inline void __mcip_cmd_data(unsigned int cmd, unsigned int param,
0117                    unsigned int data)
0118 {
0119     write_aux_reg(ARC_REG_MCIP_WDATA, data);
0120
0121     __mcip_cmd(cmd, param);
0122 }
0123
0124 /*
0125  * Read MCIP register
0126  */
0127 static inline unsigned int __mcip_cmd_read(unsigned int cmd, unsigned int param)
0128 {
0129     __mcip_cmd(cmd, param);
0130     return read_aux_reg(ARC_REG_MCIP_READBACK);
0131 }
0132
0133 #endif