include/rdma/opa_port_info.h

0001 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
0002 /*
0003  * Copyright (c) 2014-2020 Intel Corporation.  All rights reserved.
0004  */
0005
0006 #ifndef OPA_PORT_INFO_H
0007 #define OPA_PORT_INFO_H
0008
0009 #include <rdma/opa_smi.h>
0010
0011 #define OPA_PORT_LINK_MODE_NOP  0       /* No change */
0012 #define OPA_PORT_LINK_MODE_OPA  4       /* Port mode is OPA */
0013
0014 #define OPA_PORT_PACKET_FORMAT_NOP  0       /* No change */
0015 #define OPA_PORT_PACKET_FORMAT_8B   1       /* Format 8B */
0016 #define OPA_PORT_PACKET_FORMAT_9B   2       /* Format 9B */
0017 #define OPA_PORT_PACKET_FORMAT_10B  4       /* Format 10B */
0018 #define OPA_PORT_PACKET_FORMAT_16B  8       /* Format 16B */
0019
0020 #define OPA_PORT_LTP_CRC_MODE_NONE  0   /* No change */
0021 #define OPA_PORT_LTP_CRC_MODE_14    1   /* 14-bit LTP CRC mode (optional) */
0022 #define OPA_PORT_LTP_CRC_MODE_16    2   /* 16-bit LTP CRC mode */
0023 #define OPA_PORT_LTP_CRC_MODE_48    4   /* 48-bit LTP CRC mode (optional) */
0024 #define OPA_PORT_LTP_CRC_MODE_PER_LANE  8   /* 12/16-bit per lane LTP CRC mode */
0025
0026 /* Link Down / Neighbor Link Down Reason; indicated as follows: */
0027 #define OPA_LINKDOWN_REASON_NONE                0   /* No specified reason */
0028 #define OPA_LINKDOWN_REASON_RCV_ERROR_0             1
0029 #define OPA_LINKDOWN_REASON_BAD_PKT_LEN             2
0030 #define OPA_LINKDOWN_REASON_PKT_TOO_LONG            3
0031 #define OPA_LINKDOWN_REASON_PKT_TOO_SHORT           4
0032 #define OPA_LINKDOWN_REASON_BAD_SLID                5
0033 #define OPA_LINKDOWN_REASON_BAD_DLID                6
0034 #define OPA_LINKDOWN_REASON_BAD_L2              7
0035 #define OPA_LINKDOWN_REASON_BAD_SC              8
0036 #define OPA_LINKDOWN_REASON_RCV_ERROR_8             9
0037 #define OPA_LINKDOWN_REASON_BAD_MID_TAIL            10
0038 #define OPA_LINKDOWN_REASON_RCV_ERROR_10            11
0039 #define OPA_LINKDOWN_REASON_PREEMPT_ERROR           12
0040 #define OPA_LINKDOWN_REASON_PREEMPT_VL15            13
0041 #define OPA_LINKDOWN_REASON_BAD_VL_MARKER           14
0042 #define OPA_LINKDOWN_REASON_RCV_ERROR_14            15
0043 #define OPA_LINKDOWN_REASON_RCV_ERROR_15            16
0044 #define OPA_LINKDOWN_REASON_BAD_HEAD_DIST           17
0045 #define OPA_LINKDOWN_REASON_BAD_TAIL_DIST           18
0046 #define OPA_LINKDOWN_REASON_BAD_CTRL_DIST           19
0047 #define OPA_LINKDOWN_REASON_BAD_CREDIT_ACK          20
0048 #define OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER       21
0049 #define OPA_LINKDOWN_REASON_BAD_PREEMPT             22
0050 #define OPA_LINKDOWN_REASON_BAD_CONTROL_FLIT            23
0051 #define OPA_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT      24
0052 #define OPA_LINKDOWN_REASON_RCV_ERROR_24            25
0053 #define OPA_LINKDOWN_REASON_RCV_ERROR_25            26
0054 #define OPA_LINKDOWN_REASON_RCV_ERROR_26            27
0055 #define OPA_LINKDOWN_REASON_RCV_ERROR_27            28
0056 #define OPA_LINKDOWN_REASON_RCV_ERROR_28            29
0057 #define OPA_LINKDOWN_REASON_RCV_ERROR_29            30
0058 #define OPA_LINKDOWN_REASON_RCV_ERROR_30            31
0059 #define OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN        32
0060 #define OPA_LINKDOWN_REASON_UNKNOWN             33
0061 /* 34 -reserved */
0062 #define OPA_LINKDOWN_REASON_REBOOT              35
0063 #define OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN            36
0064 /* 37-38 reserved */
0065 #define OPA_LINKDOWN_REASON_FM_BOUNCE               39
0066 #define OPA_LINKDOWN_REASON_SPEED_POLICY            40
0067 #define OPA_LINKDOWN_REASON_WIDTH_POLICY            41
0068 /* 42-48 reserved */
0069 #define OPA_LINKDOWN_REASON_DISCONNECTED            49
0070 #define OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED       50
0071 #define OPA_LINKDOWN_REASON_NOT_INSTALLED           51
0072 #define OPA_LINKDOWN_REASON_CHASSIS_CONFIG          52
0073 /* 53 reserved */
0074 #define OPA_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED        54
0075 /* 55 reserved */
0076 #define OPA_LINKDOWN_REASON_POWER_POLICY            56
0077 #define OPA_LINKDOWN_REASON_LINKSPEED_POLICY            57
0078 #define OPA_LINKDOWN_REASON_LINKWIDTH_POLICY            58
0079 /* 59 reserved */
0080 #define OPA_LINKDOWN_REASON_SWITCH_MGMT             60
0081 #define OPA_LINKDOWN_REASON_SMA_DISABLED            61
0082 /* 62 reserved */
0083 #define OPA_LINKDOWN_REASON_TRANSIENT               63
0084 /* 64-255 reserved */
0085
0086 /* OPA Link Init reason; indicated as follows: */
0087 /* 3-7; 11-15 reserved; 8-15 cleared on Polling->LinkUp */
0088 #define OPA_LINKINIT_REASON_NOP                 0
0089 #define OPA_LINKINIT_REASON_LINKUP              (1 << 4)
0090 #define OPA_LINKINIT_REASON_FLAPPING            (2 << 4)
0091 #define OPA_LINKINIT_REASON_CLEAR               (8 << 4)
0092 #define OPA_LINKINIT_OUTSIDE_POLICY             (8 << 4)
0093 #define OPA_LINKINIT_QUARANTINED                (9 << 4)
0094 #define OPA_LINKINIT_INSUFIC_CAPABILITY         (10 << 4)
0095
0096 #define OPA_LINK_SPEED_NOP              0x0000  /*  Reserved (1-5 Gbps) */
0097 #define OPA_LINK_SPEED_12_5G            0x0001  /*  12.5 Gbps */
0098 #define OPA_LINK_SPEED_25G              0x0002  /*  25.78125?  Gbps (EDR) */
0099
0100 #define OPA_LINK_WIDTH_1X            0x0001
0101 #define OPA_LINK_WIDTH_2X            0x0002
0102 #define OPA_LINK_WIDTH_3X            0x0004
0103 #define OPA_LINK_WIDTH_4X            0x0008
0104
0105 #define OPA_CAP_MASK3_IsEthOnFabricSupported      (1 << 13)
0106 #define OPA_CAP_MASK3_IsSnoopSupported            (1 << 7)
0107 #define OPA_CAP_MASK3_IsAsyncSC2VLSupported       (1 << 6)
0108 #define OPA_CAP_MASK3_IsAddrRangeConfigSupported  (1 << 5)
0109 #define OPA_CAP_MASK3_IsPassThroughSupported      (1 << 4)
0110 #define OPA_CAP_MASK3_IsSharedSpaceSupported      (1 << 3)
0111 /* reserved (1 << 2) */
0112 #define OPA_CAP_MASK3_IsVLMarkerSupported         (1 << 1)
0113 #define OPA_CAP_MASK3_IsVLrSupported              (1 << 0)
0114
0115 enum {
0116     OPA_PORT_PHYS_CONF_DISCONNECTED = 0,
0117     OPA_PORT_PHYS_CONF_STANDARD     = 1,
0118     OPA_PORT_PHYS_CONF_FIXED        = 2,
0119     OPA_PORT_PHYS_CONF_VARIABLE     = 3,
0120     OPA_PORT_PHYS_CONF_SI_PHOTO     = 4
0121 };
0122
0123 enum port_info_field_masks {
0124     /* vl.cap */
0125     OPA_PI_MASK_VL_CAP                        = 0x1F,
0126     /* port_states.ledenable_offlinereason */
0127     OPA_PI_MASK_OFFLINE_REASON                = 0x0F,
0128     OPA_PI_MASK_LED_ENABLE                    = 0x40,
0129     /* port_states.unsleepstate_downdefstate */
0130     OPA_PI_MASK_UNSLEEP_STATE                 = 0xF0,
0131     OPA_PI_MASK_DOWNDEF_STATE                 = 0x0F,
0132     /* port_states.portphysstate_portstate */
0133     OPA_PI_MASK_PORT_PHYSICAL_STATE           = 0xF0,
0134     OPA_PI_MASK_PORT_STATE                    = 0x0F,
0135     /* port_phys_conf */
0136     OPA_PI_MASK_PORT_PHYSICAL_CONF            = 0x0F,
0137     /* collectivemask_multicastmask */
0138     OPA_PI_MASK_COLLECT_MASK                  = 0x38,
0139     OPA_PI_MASK_MULTICAST_MASK                = 0x07,
0140     /* mkeyprotect_lmc */
0141     OPA_PI_MASK_MKEY_PROT_BIT                 = 0xC0,
0142     OPA_PI_MASK_LMC                           = 0x0F,
0143     /* smsl */
0144     OPA_PI_MASK_SMSL                          = 0x1F,
0145     /* partenforce_filterraw */
0146     /* Filter Raw In/Out bits 1 and 2 were removed */
0147     OPA_PI_MASK_LINKINIT_REASON               = 0xF0,
0148     OPA_PI_MASK_PARTITION_ENFORCE_IN          = 0x08,
0149     OPA_PI_MASK_PARTITION_ENFORCE_OUT         = 0x04,
0150     /* operational_vls */
0151     OPA_PI_MASK_OPERATIONAL_VL                = 0x1F,
0152     /* sa_qp */
0153     OPA_PI_MASK_SA_QP                         = 0x00FFFFFF,
0154     /* sm_trap_qp */
0155     OPA_PI_MASK_SM_TRAP_QP                    = 0x00FFFFFF,
0156     /* localphy_overrun_errors */
0157     OPA_PI_MASK_LOCAL_PHY_ERRORS              = 0xF0,
0158     OPA_PI_MASK_OVERRUN_ERRORS                = 0x0F,
0159     /* clientrereg_subnettimeout */
0160     OPA_PI_MASK_CLIENT_REREGISTER             = 0x80,
0161     OPA_PI_MASK_SUBNET_TIMEOUT                = 0x1F,
0162     /* port_link_mode */
0163     OPA_PI_MASK_PORT_LINK_SUPPORTED           = (0x001F << 10),
0164     OPA_PI_MASK_PORT_LINK_ENABLED             = (0x001F <<  5),
0165     OPA_PI_MASK_PORT_LINK_ACTIVE              = (0x001F <<  0),
0166     /* port_link_crc_mode */
0167     OPA_PI_MASK_PORT_LINK_CRC_SUPPORTED       = 0x0F00,
0168     OPA_PI_MASK_PORT_LINK_CRC_ENABLED         = 0x00F0,
0169     OPA_PI_MASK_PORT_LINK_CRC_ACTIVE          = 0x000F,
0170     /* port_mode */
0171     OPA_PI_MASK_PORT_MODE_SECURITY_CHECK      = 0x0001,
0172     OPA_PI_MASK_PORT_MODE_16B_TRAP_QUERY      = 0x0002,
0173     OPA_PI_MASK_PORT_MODE_PKEY_CONVERT        = 0x0004,
0174     OPA_PI_MASK_PORT_MODE_SC2SC_MAPPING       = 0x0008,
0175     OPA_PI_MASK_PORT_MODE_VL_MARKER           = 0x0010,
0176     OPA_PI_MASK_PORT_PASS_THROUGH             = 0x0020,
0177     OPA_PI_MASK_PORT_ACTIVE_OPTOMIZE          = 0x0040,
0178     /* flit_control.interleave */
0179     OPA_PI_MASK_INTERLEAVE_DIST_SUP           = (0x0003 << 12),
0180     OPA_PI_MASK_INTERLEAVE_DIST_ENABLE        = (0x0003 << 10),
0181     OPA_PI_MASK_INTERLEAVE_MAX_NEST_TX        = (0x001F <<  5),
0182     OPA_PI_MASK_INTERLEAVE_MAX_NEST_RX        = (0x001F <<  0),
0183
0184     /* port_error_action */
0185     OPA_PI_MASK_EX_BUFFER_OVERRUN                  = 0x80000000,
0186         /* 7 bits reserved */
0187     OPA_PI_MASK_FM_CFG_ERR_EXCEED_MULTICAST_LIMIT  = 0x00800000,
0188     OPA_PI_MASK_FM_CFG_BAD_CONTROL_FLIT            = 0x00400000,
0189     OPA_PI_MASK_FM_CFG_BAD_PREEMPT                 = 0x00200000,
0190     OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER       = 0x00100000,
0191     OPA_PI_MASK_FM_CFG_BAD_CRDT_ACK                = 0x00080000,
0192     OPA_PI_MASK_FM_CFG_BAD_CTRL_DIST               = 0x00040000,
0193     OPA_PI_MASK_FM_CFG_BAD_TAIL_DIST               = 0x00020000,
0194     OPA_PI_MASK_FM_CFG_BAD_HEAD_DIST               = 0x00010000,
0195         /* 2 bits reserved */
0196     OPA_PI_MASK_PORT_RCV_BAD_VL_MARKER             = 0x00002000,
0197     OPA_PI_MASK_PORT_RCV_PREEMPT_VL15              = 0x00001000,
0198     OPA_PI_MASK_PORT_RCV_PREEMPT_ERROR             = 0x00000800,
0199         /* 1 bit reserved */
0200     OPA_PI_MASK_PORT_RCV_BAD_MidTail               = 0x00000200,
0201         /* 1 bit reserved */
0202     OPA_PI_MASK_PORT_RCV_BAD_SC                    = 0x00000080,
0203     OPA_PI_MASK_PORT_RCV_BAD_L2                    = 0x00000040,
0204     OPA_PI_MASK_PORT_RCV_BAD_DLID                  = 0x00000020,
0205     OPA_PI_MASK_PORT_RCV_BAD_SLID                  = 0x00000010,
0206     OPA_PI_MASK_PORT_RCV_PKTLEN_TOOSHORT           = 0x00000008,
0207     OPA_PI_MASK_PORT_RCV_PKTLEN_TOOLONG            = 0x00000004,
0208     OPA_PI_MASK_PORT_RCV_BAD_PKTLEN                = 0x00000002,
0209     OPA_PI_MASK_PORT_RCV_BAD_LT                    = 0x00000001,
0210
0211     /* pass_through.res_drctl */
0212     OPA_PI_MASK_PASS_THROUGH_DR_CONTROL       = 0x01,
0213
0214     /* buffer_units */
0215     OPA_PI_MASK_BUF_UNIT_VL15_INIT            = (0x00000FFF  << 11),
0216     OPA_PI_MASK_BUF_UNIT_VL15_CREDIT_RATE     = (0x0000001F  <<  6),
0217     OPA_PI_MASK_BUF_UNIT_CREDIT_ACK           = (0x00000003  <<  3),
0218     OPA_PI_MASK_BUF_UNIT_BUF_ALLOC            = (0x00000003  <<  0),
0219
0220     /* neigh_mtu.pvlx_to_mtu */
0221     OPA_PI_MASK_NEIGH_MTU_PVL0                = 0xF0,
0222     OPA_PI_MASK_NEIGH_MTU_PVL1                = 0x0F,
0223
0224     /* neigh_mtu.vlstall_hoq_life */
0225     OPA_PI_MASK_VL_STALL                      = (0x03 << 5),
0226     OPA_PI_MASK_HOQ_LIFE                      = (0x1F << 0),
0227
0228     /* port_neigh_mode */
0229     OPA_PI_MASK_NEIGH_MGMT_ALLOWED            = (0x01 << 3),
0230     OPA_PI_MASK_NEIGH_FW_AUTH_BYPASS          = (0x01 << 2),
0231     OPA_PI_MASK_NEIGH_NODE_TYPE               = (0x03 << 0),
0232
0233     /* resptime_value */
0234     OPA_PI_MASK_RESPONSE_TIME_VALUE           = 0x1F,
0235
0236     /* mtucap */
0237     OPA_PI_MASK_MTU_CAP                       = 0x0F,
0238 };
0239
0240 struct opa_port_states {
0241     u8     reserved;
0242     u8     ledenable_offlinereason;   /* 1 res, 1 bit, 6 bits */
0243     u8     reserved2;
0244     u8     portphysstate_portstate;   /* 4 bits, 4 bits */
0245 };
0246
0247 struct opa_port_state_info {
0248     struct opa_port_states port_states;
0249     __be16 link_width_downgrade_tx_active;
0250     __be16 link_width_downgrade_rx_active;
0251 };
0252
0253 struct opa_port_info {
0254     __be32 lid;
0255     __be32 flow_control_mask;
0256
0257     struct {
0258         u8     res;                       /* was inittype */
0259         u8     cap;                       /* 3 res, 5 bits */
0260         __be16 high_limit;
0261         __be16 preempt_limit;
0262         u8     arb_high_cap;
0263         u8     arb_low_cap;
0264     } vl;
0265
0266     struct opa_port_states  port_states;
0267     u8     port_phys_conf;                    /* 4 res, 4 bits */
0268     u8     collectivemask_multicastmask;      /* 2 res, 3, 3 */
0269     u8     mkeyprotect_lmc;                   /* 2 bits, 2 res, 4 bits */
0270     u8     smsl;                              /* 3 res, 5 bits */
0271
0272     u8     partenforce_filterraw;             /* bit fields */
0273     u8     operational_vls;                    /* 3 res, 5 bits */
0274     __be16 pkey_8b;
0275     __be16 pkey_10b;
0276     __be16 mkey_violations;
0277
0278     __be16 pkey_violations;
0279     __be16 qkey_violations;
0280     __be32 sm_trap_qp;                        /* 8 bits, 24 bits */
0281
0282     __be32 sa_qp;                             /* 8 bits, 24 bits */
0283     u8     neigh_port_num;
0284     u8     link_down_reason;
0285     u8     neigh_link_down_reason;
0286     u8     clientrereg_subnettimeout;     /* 1 bit, 2 bits, 5 */
0287
0288     struct {
0289         __be16 supported;
0290         __be16 enabled;
0291         __be16 active;
0292     } link_speed;
0293     struct {
0294         __be16 supported;
0295         __be16 enabled;
0296         __be16 active;
0297     } link_width;
0298     struct {
0299         __be16 supported;
0300         __be16 enabled;
0301         __be16 tx_active;
0302         __be16 rx_active;
0303     } link_width_downgrade;
0304     __be16 port_link_mode;                  /* 1 res, 5 bits, 5 bits, 5 bits */
0305     __be16 port_ltp_crc_mode;               /* 4 res, 4 bits, 4 bits, 4 bits */
0306
0307     __be16 port_mode;                       /* 9 res, bit fields */
0308     struct {
0309         __be16 supported;
0310         __be16 enabled;
0311     } port_packet_format;
0312     struct {
0313         __be16 interleave;  /* 2 res, 2,2,5,5 */
0314         struct {
0315             __be16 min_initial;
0316             __be16 min_tail;
0317             u8     large_pkt_limit;
0318             u8     small_pkt_limit;
0319             u8     max_small_pkt_limit;
0320             u8     preemption_limit;
0321         } preemption;
0322     } flit_control;
0323
0324     __be32 reserved4;
0325     __be32 port_error_action; /* bit field */
0326
0327     struct {
0328         u8 egress_port;
0329         u8 res_drctl;                    /* 7 res, 1 */
0330     } pass_through;
0331     __be16 mkey_lease_period;
0332     __be32 buffer_units;                     /* 9 res, 12, 5, 3, 3 */
0333
0334     __be32 reserved5;
0335     __be32 sm_lid;
0336
0337     __be64 mkey;
0338
0339     __be64 subnet_prefix;
0340
0341     struct {
0342         u8 pvlx_to_mtu[OPA_MAX_VLS/2]; /* 4 bits, 4 bits */
0343     } neigh_mtu;
0344
0345     struct {
0346         u8 vlstall_hoqlife;             /* 3 bits, 5 bits */
0347     } xmit_q[OPA_MAX_VLS];
0348
0349     struct {
0350         u8 addr[16];
0351     } ipaddr_ipv6;
0352
0353     struct {
0354         u8 addr[4];
0355     } ipaddr_ipv4;
0356
0357     u32    reserved6;
0358     u32    reserved7;
0359     u32    reserved8;
0360
0361     __be64 neigh_node_guid;
0362
0363     __be32 ib_cap_mask;
0364     __be16 reserved9;                    /* was ib_cap_mask2 */
0365     __be16 opa_cap_mask;
0366
0367     __be32 reserved10;                   /* was link_roundtrip_latency */
0368     __be16 overall_buffer_space;
0369     __be16 reserved11;                   /* was max_credit_hint */
0370
0371     __be16 diag_code;
0372     struct {
0373         u8 buffer;
0374         u8 wire;
0375     } replay_depth;
0376     u8     port_neigh_mode;
0377     u8     mtucap;                          /* 4 res, 4 bits */
0378
0379     u8     resptimevalue;               /* 3 res, 5 bits */
0380     u8     local_port_num;
0381     u8     reserved12;
0382     u8     reserved13;                       /* was guid_cap */
0383 } __packed;
0384
0385 #endif /* OPA_PORT_INFO_H */