include/misc/cxllib.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright 2017 IBM Corp.
0004  */
0005
0006 #ifndef _MISC_CXLLIB_H
0007 #define _MISC_CXLLIB_H
0008
0009 #include <linux/pci.h>
0010 #include <asm/reg.h>
0011
0012 /*
0013  * cxl driver exports a in-kernel 'library' API which can be called by
0014  * other drivers to help interacting with an IBM XSL.
0015  */
0016
0017 /*
0018  * tells whether capi is supported on the PCIe slot where the
0019  * device is seated
0020  *
0021  * Input:
0022  *  dev: device whose slot needs to be checked
0023  *  flags: 0 for the time being
0024  */
0025 bool cxllib_slot_is_supported(struct pci_dev *dev, unsigned long flags);
0026
0027
0028 /*
0029  * Returns the configuration parameters to be used by the XSL or device
0030  *
0031  * Input:
0032  *  dev: device, used to find PHB
0033  * Output:
0034  *  struct cxllib_xsl_config:
0035  *      version
0036  *      capi BAR address, i.e. 0x2000000000000-0x2FFFFFFFFFFFF
0037  *      capi BAR size
0038  *      data send control (XSL_DSNCTL)
0039  *      dummy read address (XSL_DRA)
0040  */
0041 #define CXL_XSL_CONFIG_VERSION1     1
0042 struct cxllib_xsl_config {
0043     u32 version;     /* format version for register encoding */
0044     u32 log_bar_size;/* log size of the capi_window */
0045     u64 bar_addr;    /* address of the start of capi window */
0046     u64 dsnctl;      /* matches definition of XSL_DSNCTL */
0047     u64 dra;         /* real address that can be used for dummy read */
0048 };
0049
0050 int cxllib_get_xsl_config(struct pci_dev *dev, struct cxllib_xsl_config *cfg);
0051
0052
0053 /*
0054  * Activate capi for the pci host bridge associated with the device.
0055  * Can be extended to deactivate once we know how to do it.
0056  * Device must be ready to accept messages from the CAPP unit and
0057  * respond accordingly (TLB invalidates, ...)
0058  *
0059  * PHB is switched to capi mode through calls to skiboot.
0060  * CAPP snooping is activated
0061  *
0062  * Input:
0063  *  dev: device whose PHB should switch mode
0064  *  mode: mode to switch to i.e. CAPI or PCI
0065  *  flags: options related to the mode
0066  */
0067 enum cxllib_mode {
0068     CXL_MODE_CXL,
0069     CXL_MODE_PCI,
0070 };
0071
0072 #define CXL_MODE_NO_DMA       0
0073 #define CXL_MODE_DMA_TVT0     1
0074 #define CXL_MODE_DMA_TVT1     2
0075
0076 int cxllib_switch_phb_mode(struct pci_dev *dev, enum cxllib_mode mode,
0077             unsigned long flags);
0078
0079
0080 /*
0081  * Set the device for capi DMA.
0082  * Define its dma_ops and dma offset so that allocations will be using TVT#1
0083  *
0084  * Input:
0085  *  dev: device to set
0086  *  flags: options. CXL_MODE_DMA_TVT1 should be used
0087  */
0088 int cxllib_set_device_dma(struct pci_dev *dev, unsigned long flags);
0089
0090
0091 /*
0092  * Get the Process Element structure for the given thread
0093  *
0094  * Input:
0095  *    task: task_struct for the context of the translation
0096  *    translation_mode: whether addresses should be translated
0097  * Output:
0098  *    attr: attributes to fill up the Process Element structure from CAIA
0099  */
0100 struct cxllib_pe_attributes {
0101     u64 sr;
0102     u32 lpid;
0103     u32 tid;
0104     u32 pid;
0105 };
0106 #define CXL_TRANSLATED_MODE 0
0107 #define CXL_REAL_MODE 1
0108
0109 int cxllib_get_PE_attributes(struct task_struct *task,
0110          unsigned long translation_mode, struct cxllib_pe_attributes *attr);
0111
0112
0113 /*
0114  * Handle memory fault.
0115  * Fault in all the pages of the specified buffer for the permissions
0116  * provided in ‘flags’
0117  *
0118  * Shouldn't be called from interrupt context
0119  *
0120  * Input:
0121  *  mm: struct mm for the thread faulting the pages
0122  *  addr: base address of the buffer to page in
0123  *  size: size of the buffer to page in
0124  *  flags: permission requested (DSISR_ISSTORE...)
0125  */
0126 int cxllib_handle_fault(struct mm_struct *mm, u64 addr, u64 size, u64 flags);
0127
0128
0129 #endif /* _MISC_CXLLIB_H */