media/i2c/tc358743.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * tc358743 - Toshiba HDMI to CSI-2 bridge
0004  *
0005  * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
0006  */
0007
0008 /*
0009  * References (c = chapter, p = page):
0010  * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
0011  * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
0012  */
0013
0014 #ifndef _TC358743_
0015 #define _TC358743_
0016
0017 enum tc358743_ddc5v_delays {
0018     DDC5V_DELAY_0_MS,
0019     DDC5V_DELAY_50_MS,
0020     DDC5V_DELAY_100_MS,
0021     DDC5V_DELAY_200_MS,
0022 };
0023
0024 enum tc358743_hdmi_detection_delay {
0025     HDMI_MODE_DELAY_0_MS,
0026     HDMI_MODE_DELAY_25_MS,
0027     HDMI_MODE_DELAY_50_MS,
0028     HDMI_MODE_DELAY_100_MS,
0029 };
0030
0031 struct tc358743_platform_data {
0032     /* System clock connected to REFCLK (pin H5) */
0033     u32 refclk_hz; /* 26 MHz, 27 MHz or 42 MHz */
0034
0035     /* DDC +5V debounce delay to avoid spurious interrupts when the cable
0036      * is connected.
0037      * Sets DDC5V_MODE in register DDC_CTL.
0038      * Default: DDC5V_DELAY_0_MS
0039      */
0040     enum tc358743_ddc5v_delays ddc5v_delay;
0041
0042     bool enable_hdcp;
0043
0044     /*
0045      * The FIFO size is 512x32, so Toshiba recommend to set the default FIFO
0046      * level to somewhere in the middle (e.g. 300), so it can cover speed
0047      * mismatches in input and output ports.
0048      */
0049     u16 fifo_level;
0050
0051     /* Bps pr lane is (refclk_hz / pll_prd) * pll_fbd */
0052     u16 pll_prd;
0053     u16 pll_fbd;
0054
0055     /* CSI
0056      * Calculate CSI parameters with REF_02 for the highest resolution your
0057      * CSI interface can handle. The driver will adjust the number of CSI
0058      * lanes in use according to the pixel clock.
0059      *
0060      * The values in brackets are calculated with REF_02 when the number of
0061      * bps pr lane is 823.5 MHz, and can serve as a starting point.
0062      */
0063     u32 lineinitcnt;    /* (0x00001770) */
0064     u32 lptxtimecnt;    /* (0x00000005) */
0065     u32 tclk_headercnt; /* (0x00001d04) */
0066     u32 tclk_trailcnt;  /* (0x00000000) */
0067     u32 ths_headercnt;  /* (0x00000505) */
0068     u32 twakeup;        /* (0x00004650) */
0069     u32 tclk_postcnt;   /* (0x00000000) */
0070     u32 ths_trailcnt;   /* (0x00000004) */
0071     u32 hstxvregcnt;    /* (0x00000005) */
0072
0073     /* DVI->HDMI detection delay to avoid unnecessary switching between DVI
0074      * and HDMI mode.
0075      * Sets HDMI_DET_V in register HDMI_DET.
0076      * Default: HDMI_MODE_DELAY_0_MS
0077      */
0078     enum tc358743_hdmi_detection_delay hdmi_detection_delay;
0079
0080     /* Reset PHY automatically when TMDS clock goes from DC to AC.
0081      * Sets PHY_AUTO_RST2 in register PHY_CTL2.
0082      * Default: false
0083      */
0084     bool hdmi_phy_auto_reset_tmds_detected;
0085
0086     /* Reset PHY automatically when TMDS clock passes 21 MHz.
0087      * Sets PHY_AUTO_RST3 in register PHY_CTL2.
0088      * Default: false
0089      */
0090     bool hdmi_phy_auto_reset_tmds_in_range;
0091
0092     /* Reset PHY automatically when TMDS clock is detected.
0093      * Sets PHY_AUTO_RST4 in register PHY_CTL2.
0094      * Default: false
0095      */
0096     bool hdmi_phy_auto_reset_tmds_valid;
0097
0098     /* Reset HDMI PHY automatically when hsync period is out of range.
0099      * Sets H_PI_RST in register HV_RST.
0100      * Default: false
0101      */
0102     bool hdmi_phy_auto_reset_hsync_out_of_range;
0103
0104     /* Reset HDMI PHY automatically when vsync period is out of range.
0105      * Sets V_PI_RST in register HV_RST.
0106      * Default: false
0107      */
0108     bool hdmi_phy_auto_reset_vsync_out_of_range;
0109 };
0110
0111 /* custom controls */
0112 /* Audio sample rate in Hz */
0113 #define TC358743_CID_AUDIO_SAMPLING_RATE (V4L2_CID_USER_TC358743_BASE + 0)
0114 /* Audio present status */
0115 #define TC358743_CID_AUDIO_PRESENT       (V4L2_CID_USER_TC358743_BASE + 1)
0116
0117 #endif