media/i2c/saa7115.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003     saa7115.h - definition for saa7111/3/4/5 inputs and frequency flags
0004
0005     Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)
0006
0007 */
0008
0009 #ifndef _SAA7115_H_
0010 #define _SAA7115_H_
0011
0012 /* s_routing inputs, outputs, and config */
0013
0014 /* SAA7111/3/4/5 HW inputs */
0015 #define SAA7115_COMPOSITE0 0
0016 #define SAA7115_COMPOSITE1 1
0017 #define SAA7115_COMPOSITE2 2
0018 #define SAA7115_COMPOSITE3 3
0019 #define SAA7115_COMPOSITE4 4 /* not available for the saa7111/3 */
0020 #define SAA7115_COMPOSITE5 5 /* not available for the saa7111/3 */
0021 #define SAA7115_SVIDEO0    6
0022 #define SAA7115_SVIDEO1    7
0023 #define SAA7115_SVIDEO2    8
0024 #define SAA7115_SVIDEO3    9
0025
0026 /* outputs */
0027 #define SAA7115_IPORT_ON    1
0028 #define SAA7115_IPORT_OFF   0
0029
0030 /* SAA7111 specific outputs. */
0031 #define SAA7111_VBI_BYPASS  2
0032 #define SAA7111_FMT_YUV422      0x00
0033 #define SAA7111_FMT_RGB     0x40
0034 #define SAA7111_FMT_CCIR    0x80
0035 #define SAA7111_FMT_YUV411  0xc0
0036
0037 /* config flags */
0038 /*
0039  * Register 0x85 should set bit 0 to 0 (it's 1 by default). This bit
0040  * controls the IDQ signal polarity which is set to 'inverted' if the bit
0041  * it 1 and to 'default' if it is 0.
0042  */
0043 #define SAA7115_IDQ_IS_DEFAULT  (1 << 0)
0044
0045 /* s_crystal_freq values and flags */
0046
0047 /* SAA7115 v4l2_crystal_freq frequency values */
0048 #define SAA7115_FREQ_32_11_MHZ  32110000   /* 32.11 MHz crystal, SAA7114/5 only */
0049 #define SAA7115_FREQ_24_576_MHZ 24576000   /* 24.576 MHz crystal */
0050
0051 /* SAA7115 v4l2_crystal_freq audio clock control flags */
0052 #define SAA7115_FREQ_FL_UCGC         (1 << 0) /* SA 3A[7], UCGC, SAA7115 only */
0053 #define SAA7115_FREQ_FL_CGCDIV       (1 << 1) /* SA 3A[6], CGCDIV, SAA7115 only */
0054 #define SAA7115_FREQ_FL_APLL         (1 << 2) /* SA 3A[3], APLL, SAA7114/5 only */
0055 #define SAA7115_FREQ_FL_DOUBLE_ASCLK (1 << 3) /* SA 39, LRDIV, SAA7114/5 only */
0056
0057 /* ===== SAA7113 Config enums ===== */
0058
0059 /* Register 0x08 "Horizontal time constant" [Bit 3..4]:
0060  * Should be set to "Fast Locking Mode" according to the datasheet,
0061  * and that is the default setting in the gm7113c_init table.
0062  * saa7113_init sets this value to "VTR Mode". */
0063 enum saa7113_r08_htc {
0064     SAA7113_HTC_TV_MODE = 0x00,
0065     SAA7113_HTC_VTR_MODE,           /* Default for saa7113_init */
0066     SAA7113_HTC_FAST_LOCKING_MODE = 0x03    /* Default for gm7113c_init */
0067 };
0068
0069 /* Register 0x10 "Output format selection" [Bit 6..7]:
0070  * Defaults to ITU_656 as specified in datasheet. */
0071 enum saa7113_r10_ofts {
0072     SAA7113_OFTS_ITU_656 = 0x0, /* Default */
0073     SAA7113_OFTS_VFLAG_BY_VREF,
0074     SAA7113_OFTS_VFLAG_BY_DATA_TYPE
0075 };
0076
0077 /*
0078  * Register 0x12 "Output control" [Bit 0..3 Or Bit 4..7]:
0079  * This is used to select what data is output on the RTS0 and RTS1 pins.
0080  * RTS1 [Bit 4..7] Defaults to DOT_IN. (This value can not be set for RTS0)
0081  * RTS0 [Bit 0..3] Defaults to VIPB in gm7113c_init as specified
0082  * in the datasheet, but is set to HREF_HS in the saa7113_init table.
0083  */
0084 enum saa7113_r12_rts {
0085     SAA7113_RTS_DOT_IN = 0,     /* OBS: Only for RTS1 (Default RTS1) */
0086     SAA7113_RTS_VIPB,       /* Default RTS0 For gm7113c_init */
0087     SAA7113_RTS_GPSW,
0088     SAA7115_RTS_HL,
0089     SAA7113_RTS_VL,
0090     SAA7113_RTS_DL,
0091     SAA7113_RTS_PLIN,
0092     SAA7113_RTS_HREF_HS,        /* Default RTS0 For saa7113_init */
0093     SAA7113_RTS_HS,
0094     SAA7113_RTS_HQ,
0095     SAA7113_RTS_ODD,
0096     SAA7113_RTS_VS,
0097     SAA7113_RTS_V123,
0098     SAA7113_RTS_VGATE,
0099     SAA7113_RTS_VREF,
0100     SAA7113_RTS_FID
0101 };
0102
0103 /**
0104  * struct saa7115_platform_data - Allow overriding default initialization
0105  *
0106  * @saa7113_force_gm7113c_init: Force the use of the gm7113c_init table
0107  *              instead of saa7113_init table
0108  *              (saa7113 only)
0109  * @saa7113_r08_htc:        [R_08 - Bit 3..4]
0110  * @saa7113_r10_vrln:       [R_10 - Bit 3]
0111  *              default: Disabled for gm7113c_init
0112  *                   Enabled for saa7113c_init
0113  * @saa7113_r10_ofts:       [R_10 - Bit 6..7]
0114  * @saa7113_r12_rts0:       [R_12 - Bit 0..3]
0115  * @saa7113_r12_rts1:       [R_12 - Bit 4..7]
0116  * @saa7113_r13_adlsb:      [R_13 - Bit 7] - default: disabled
0117  */
0118 struct saa7115_platform_data {
0119     bool saa7113_force_gm7113c_init;
0120     enum saa7113_r08_htc *saa7113_r08_htc;
0121     bool *saa7113_r10_vrln;
0122     enum saa7113_r10_ofts *saa7113_r10_ofts;
0123     enum saa7113_r12_rts *saa7113_r12_rts0;
0124     enum saa7113_r12_rts *saa7113_r12_rts1;
0125     bool *saa7113_r13_adlsb;
0126 };
0127
0128 #endif