media/i2c/adv7842.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * adv7842 - Analog Devices ADV7842 video decoder driver
0004  *
0005  * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
0006  */
0007
0008 #ifndef _ADV7842_
0009 #define _ADV7842_
0010
0011 /* Analog input muxing modes (AFE register 0x02, [2:0]) */
0012 enum adv7842_ain_sel {
0013     ADV7842_AIN1_2_3_NC_SYNC_1_2 = 0,
0014     ADV7842_AIN4_5_6_NC_SYNC_2_1 = 1,
0015     ADV7842_AIN7_8_9_NC_SYNC_3_1 = 2,
0016     ADV7842_AIN10_11_12_NC_SYNC_4_1 = 3,
0017     ADV7842_AIN9_4_5_6_SYNC_2_1 = 4,
0018 };
0019
0020 /*
0021  * Bus rotation and reordering. This is used to specify component reordering on
0022  * the board and describes the components order on the bus when the ADV7842
0023  * outputs RGB.
0024  */
0025 enum adv7842_bus_order {
0026     ADV7842_BUS_ORDER_RGB,      /* No operation */
0027     ADV7842_BUS_ORDER_GRB,      /* Swap 1-2 */
0028     ADV7842_BUS_ORDER_RBG,      /* Swap 2-3 */
0029     ADV7842_BUS_ORDER_BGR,      /* Swap 1-3 */
0030     ADV7842_BUS_ORDER_BRG,      /* Rotate right */
0031     ADV7842_BUS_ORDER_GBR,      /* Rotate left  */
0032 };
0033
0034 /* Input Color Space (IO register 0x02, [7:4]) */
0035 enum adv7842_inp_color_space {
0036     ADV7842_INP_COLOR_SPACE_LIM_RGB = 0,
0037     ADV7842_INP_COLOR_SPACE_FULL_RGB = 1,
0038     ADV7842_INP_COLOR_SPACE_LIM_YCbCr_601 = 2,
0039     ADV7842_INP_COLOR_SPACE_LIM_YCbCr_709 = 3,
0040     ADV7842_INP_COLOR_SPACE_XVYCC_601 = 4,
0041     ADV7842_INP_COLOR_SPACE_XVYCC_709 = 5,
0042     ADV7842_INP_COLOR_SPACE_FULL_YCbCr_601 = 6,
0043     ADV7842_INP_COLOR_SPACE_FULL_YCbCr_709 = 7,
0044     ADV7842_INP_COLOR_SPACE_AUTO = 0xf,
0045 };
0046
0047 /* Select output format (IO register 0x03, [4:2]) */
0048 enum adv7842_op_format_mode_sel {
0049     ADV7842_OP_FORMAT_MODE0 = 0x00,
0050     ADV7842_OP_FORMAT_MODE1 = 0x04,
0051     ADV7842_OP_FORMAT_MODE2 = 0x08,
0052 };
0053
0054 /* Mode of operation */
0055 enum adv7842_mode {
0056     ADV7842_MODE_SDP,
0057     ADV7842_MODE_COMP,
0058     ADV7842_MODE_RGB,
0059     ADV7842_MODE_HDMI
0060 };
0061
0062 /* Video standard select (IO register 0x00, [5:0]) */
0063 enum adv7842_vid_std_select {
0064     /* SDP */
0065     ADV7842_SDP_VID_STD_CVBS_SD_4x1 = 0x01,
0066     ADV7842_SDP_VID_STD_YC_SD4_x1 = 0x09,
0067     /* RGB */
0068     ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE = 0x07,
0069     /* HDMI GR */
0070     ADV7842_HDMI_GR_VID_STD_AUTO_GRAPH_MODE = 0x02,
0071     /* HDMI COMP */
0072     ADV7842_HDMI_COMP_VID_STD_HD_1250P = 0x1e,
0073 };
0074
0075 enum adv7842_select_input {
0076     ADV7842_SELECT_HDMI_PORT_A,
0077     ADV7842_SELECT_HDMI_PORT_B,
0078     ADV7842_SELECT_VGA_RGB,
0079     ADV7842_SELECT_VGA_COMP,
0080     ADV7842_SELECT_SDP_CVBS,
0081     ADV7842_SELECT_SDP_YC,
0082 };
0083
0084 enum adv7842_drive_strength {
0085     ADV7842_DR_STR_LOW = 0,
0086     ADV7842_DR_STR_MEDIUM_LOW = 1,
0087     ADV7842_DR_STR_MEDIUM_HIGH = 2,
0088     ADV7842_DR_STR_HIGH = 3,
0089 };
0090
0091 struct adv7842_sdp_csc_coeff {
0092     bool manual;
0093     u16 scaling;
0094     u16 A1;
0095     u16 A2;
0096     u16 A3;
0097     u16 A4;
0098     u16 B1;
0099     u16 B2;
0100     u16 B3;
0101     u16 B4;
0102     u16 C1;
0103     u16 C2;
0104     u16 C3;
0105     u16 C4;
0106 };
0107
0108 struct adv7842_sdp_io_sync_adjustment {
0109     bool adjust;
0110     u16 hs_beg;
0111     u16 hs_width;
0112     u16 de_beg;
0113     u16 de_end;
0114     u8 vs_beg_o;
0115     u8 vs_beg_e;
0116     u8 vs_end_o;
0117     u8 vs_end_e;
0118     u8 de_v_beg_o;
0119     u8 de_v_beg_e;
0120     u8 de_v_end_o;
0121     u8 de_v_end_e;
0122 };
0123
0124 /* Platform dependent definition */
0125 struct adv7842_platform_data {
0126     /* chip reset during probe */
0127     unsigned chip_reset:1;
0128
0129     /* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */
0130     unsigned disable_pwrdnb:1;
0131
0132     /* DIS_CABLE_DET_RST: 1 if the 5V pins are unused and unconnected */
0133     unsigned disable_cable_det_rst:1;
0134
0135     /* Analog input muxing mode */
0136     enum adv7842_ain_sel ain_sel;
0137
0138     /* Bus rotation and reordering */
0139     enum adv7842_bus_order bus_order;
0140
0141     /* Select output format mode */
0142     enum adv7842_op_format_mode_sel op_format_mode_sel;
0143
0144     /* Default mode */
0145     enum adv7842_mode mode;
0146
0147     /* Default input */
0148     unsigned input;
0149
0150     /* Video standard */
0151     enum adv7842_vid_std_select vid_std_select;
0152
0153     /* IO register 0x02 */
0154     unsigned alt_gamma:1;
0155
0156     /* IO register 0x05 */
0157     unsigned blank_data:1;
0158     unsigned insert_av_codes:1;
0159     unsigned replicate_av_codes:1;
0160
0161     /* IO register 0x30 */
0162     unsigned output_bus_lsb_to_msb:1;
0163
0164     /* IO register 0x14 */
0165     enum adv7842_drive_strength dr_str_data;
0166     enum adv7842_drive_strength dr_str_clk;
0167     enum adv7842_drive_strength dr_str_sync;
0168
0169     /*
0170      * IO register 0x19: Adjustment to the LLC DLL phase in
0171      * increments of 1/32 of a clock period.
0172      */
0173     unsigned llc_dll_phase:5;
0174
0175     /* External RAM for 3-D comb or frame synchronizer */
0176     unsigned sd_ram_size; /* ram size in MB */
0177     unsigned sd_ram_ddr:1; /* ddr or sdr sdram */
0178
0179     /* HDMI free run, CP-reg 0xBA */
0180     unsigned hdmi_free_run_enable:1;
0181     /* 0 = Mode 0: run when there is no TMDS clock
0182        1 = Mode 1: run when there is no TMDS clock or the
0183            video resolution does not match programmed one. */
0184     unsigned hdmi_free_run_mode:1;
0185
0186     /* SDP free run, CP-reg 0xDD */
0187     unsigned sdp_free_run_auto:1;
0188     unsigned sdp_free_run_man_col_en:1;
0189     unsigned sdp_free_run_cbar_en:1;
0190     unsigned sdp_free_run_force:1;
0191
0192     /* HPA manual (0) or auto (1), affects HDMI register 0x69 */
0193     unsigned hpa_auto:1;
0194
0195     struct adv7842_sdp_csc_coeff sdp_csc_coeff;
0196
0197     struct adv7842_sdp_io_sync_adjustment sdp_io_sync_625;
0198     struct adv7842_sdp_io_sync_adjustment sdp_io_sync_525;
0199
0200     /* i2c addresses */
0201     u8 i2c_sdp_io;
0202     u8 i2c_sdp;
0203     u8 i2c_cp;
0204     u8 i2c_vdp;
0205     u8 i2c_afe;
0206     u8 i2c_hdmi;
0207     u8 i2c_repeater;
0208     u8 i2c_edid;
0209     u8 i2c_infoframe;
0210     u8 i2c_cec;
0211     u8 i2c_avlink;
0212 };
0213
0214 #define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE   (V4L2_CID_DV_CLASS_BASE + 0x1000)
0215 #define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL   (V4L2_CID_DV_CLASS_BASE + 0x1001)
0216 #define V4L2_CID_ADV_RX_FREE_RUN_COLOR      (V4L2_CID_DV_CLASS_BASE + 0x1002)
0217
0218 /* custom ioctl, used to test the external RAM that's used by the
0219  * deinterlacer. */
0220 #define ADV7842_CMD_RAM_TEST _IO('V', BASE_VIDIOC_PRIVATE)
0221
0222 #define ADV7842_EDID_PORT_A   0
0223 #define ADV7842_EDID_PORT_B   1
0224 #define ADV7842_EDID_PORT_VGA 2
0225 #define ADV7842_PAD_SOURCE    3
0226
0227 #endif