media/i2c/adv7604.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * adv7604 - Analog Devices ADV7604 video decoder driver
0004  *
0005  * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
0006  */
0007
0008 #ifndef _ADV7604_
0009 #define _ADV7604_
0010
0011 #include <linux/types.h>
0012
0013 /* Analog input muxing modes (AFE register 0x02, [2:0]) */
0014 enum adv7604_ain_sel {
0015     ADV7604_AIN1_2_3_NC_SYNC_1_2 = 0,
0016     ADV7604_AIN4_5_6_NC_SYNC_2_1 = 1,
0017     ADV7604_AIN7_8_9_NC_SYNC_3_1 = 2,
0018     ADV7604_AIN10_11_12_NC_SYNC_4_1 = 3,
0019     ADV7604_AIN9_4_5_6_SYNC_2_1 = 4,
0020 };
0021
0022 /*
0023  * Bus rotation and reordering. This is used to specify component reordering on
0024  * the board and describes the components order on the bus when the ADV7604
0025  * outputs RGB.
0026  */
0027 enum adv7604_bus_order {
0028     ADV7604_BUS_ORDER_RGB,      /* No operation */
0029     ADV7604_BUS_ORDER_GRB,      /* Swap 1-2 */
0030     ADV7604_BUS_ORDER_RBG,      /* Swap 2-3 */
0031     ADV7604_BUS_ORDER_BGR,      /* Swap 1-3 */
0032     ADV7604_BUS_ORDER_BRG,      /* Rotate right */
0033     ADV7604_BUS_ORDER_GBR,      /* Rotate left  */
0034 };
0035
0036 /* Input Color Space (IO register 0x02, [7:4]) */
0037 enum adv76xx_inp_color_space {
0038     ADV76XX_INP_COLOR_SPACE_LIM_RGB = 0,
0039     ADV76XX_INP_COLOR_SPACE_FULL_RGB = 1,
0040     ADV76XX_INP_COLOR_SPACE_LIM_YCbCr_601 = 2,
0041     ADV76XX_INP_COLOR_SPACE_LIM_YCbCr_709 = 3,
0042     ADV76XX_INP_COLOR_SPACE_XVYCC_601 = 4,
0043     ADV76XX_INP_COLOR_SPACE_XVYCC_709 = 5,
0044     ADV76XX_INP_COLOR_SPACE_FULL_YCbCr_601 = 6,
0045     ADV76XX_INP_COLOR_SPACE_FULL_YCbCr_709 = 7,
0046     ADV76XX_INP_COLOR_SPACE_AUTO = 0xf,
0047 };
0048
0049 /* Select output format (IO register 0x03, [4:2]) */
0050 enum adv7604_op_format_mode_sel {
0051     ADV7604_OP_FORMAT_MODE0 = 0x00,
0052     ADV7604_OP_FORMAT_MODE1 = 0x04,
0053     ADV7604_OP_FORMAT_MODE2 = 0x08,
0054 };
0055
0056 enum adv76xx_drive_strength {
0057     ADV76XX_DR_STR_MEDIUM_LOW = 1,
0058     ADV76XX_DR_STR_MEDIUM_HIGH = 2,
0059     ADV76XX_DR_STR_HIGH = 3,
0060 };
0061
0062 /* INT1 Configuration (IO register 0x40, [1:0]) */
0063 enum adv76xx_int1_config {
0064     ADV76XX_INT1_CONFIG_OPEN_DRAIN,
0065     ADV76XX_INT1_CONFIG_ACTIVE_LOW,
0066     ADV76XX_INT1_CONFIG_ACTIVE_HIGH,
0067     ADV76XX_INT1_CONFIG_DISABLED,
0068 };
0069
0070 enum adv76xx_page {
0071     ADV76XX_PAGE_IO,
0072     ADV7604_PAGE_AVLINK,
0073     ADV76XX_PAGE_CEC,
0074     ADV76XX_PAGE_INFOFRAME,
0075     ADV7604_PAGE_ESDP,
0076     ADV7604_PAGE_DPP,
0077     ADV76XX_PAGE_AFE,
0078     ADV76XX_PAGE_REP,
0079     ADV76XX_PAGE_EDID,
0080     ADV76XX_PAGE_HDMI,
0081     ADV76XX_PAGE_TEST,
0082     ADV76XX_PAGE_CP,
0083     ADV7604_PAGE_VDP,
0084     ADV76XX_PAGE_MAX,
0085 };
0086
0087 /* Platform dependent definition */
0088 struct adv76xx_platform_data {
0089     /* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */
0090     unsigned disable_pwrdnb:1;
0091
0092     /* DIS_CABLE_DET_RST: 1 if the 5V pins are unused and unconnected */
0093     unsigned disable_cable_det_rst:1;
0094
0095     int default_input;
0096
0097     /* Analog input muxing mode */
0098     enum adv7604_ain_sel ain_sel;
0099
0100     /* Bus rotation and reordering */
0101     enum adv7604_bus_order bus_order;
0102
0103     /* Select output format mode */
0104     enum adv7604_op_format_mode_sel op_format_mode_sel;
0105
0106     /* Configuration of the INT1 pin */
0107     enum adv76xx_int1_config int1_config;
0108
0109     /* IO register 0x02 */
0110     unsigned alt_gamma:1;
0111
0112     /* IO register 0x05 */
0113     unsigned blank_data:1;
0114     unsigned insert_av_codes:1;
0115     unsigned replicate_av_codes:1;
0116
0117     /* IO register 0x06 */
0118     unsigned inv_vs_pol:1;
0119     unsigned inv_hs_pol:1;
0120     unsigned inv_llc_pol:1;
0121
0122     /* IO register 0x14 */
0123     enum adv76xx_drive_strength dr_str_data;
0124     enum adv76xx_drive_strength dr_str_clk;
0125     enum adv76xx_drive_strength dr_str_sync;
0126
0127     /* IO register 0x30 */
0128     unsigned output_bus_lsb_to_msb:1;
0129
0130     /* Free run */
0131     unsigned hdmi_free_run_mode;
0132
0133     /* i2c addresses: 0 == use default */
0134     u8 i2c_addresses[ADV76XX_PAGE_MAX];
0135 };
0136
0137 enum adv76xx_pad {
0138     ADV76XX_PAD_HDMI_PORT_A = 0,
0139     ADV7604_PAD_HDMI_PORT_B = 1,
0140     ADV7604_PAD_HDMI_PORT_C = 2,
0141     ADV7604_PAD_HDMI_PORT_D = 3,
0142     ADV7604_PAD_VGA_RGB = 4,
0143     ADV7604_PAD_VGA_COMP = 5,
0144     /* The source pad is either 1 (ADV7611) or 6 (ADV7604) */
0145     ADV7604_PAD_SOURCE = 6,
0146     ADV7611_PAD_SOURCE = 1,
0147     ADV76XX_PAD_MAX = 7,
0148 };
0149
0150 #define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE   (V4L2_CID_DV_CLASS_BASE + 0x1000)
0151 #define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL   (V4L2_CID_DV_CLASS_BASE + 0x1001)
0152 #define V4L2_CID_ADV_RX_FREE_RUN_COLOR      (V4L2_CID_DV_CLASS_BASE + 0x1002)
0153
0154 /* notify events */
0155 #define ADV76XX_HOTPLUG     1
0156
0157 #endif