media/drv-intf/cx25840.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002
0003 /*
0004  *   cx25840.h - definition for cx25840/1/2/3 inputs
0005  *
0006  *   Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)
0007  */
0008
0009 #ifndef _CX25840_H_
0010 #define _CX25840_H_
0011
0012 /*
0013  * Note that the cx25840 driver requires that the bridge driver calls the
0014  * v4l2_subdev's load_fw operation in order to load the driver's firmware.
0015  * This will load the firmware on the first invocation (further ones are NOP).
0016  * Without this the audio standard detection will fail and you will
0017  * only get mono.
0018  * Alternatively, you can call the reset operation (this can be done
0019  * multiple times if needed, each invocation will fully reinitialize
0020  * the device).
0021  *
0022  * Since loading the firmware is often problematic when the driver is
0023  * compiled into the kernel I recommend postponing calling this function
0024  * until the first open of the video device. Another reason for
0025  * postponing it is that loading this firmware takes a long time (seconds)
0026  * due to the slow i2c bus speed. So it will speed up the boot process if
0027  * you can avoid loading the fw as long as the video device isn't used.
0028  */
0029
0030 enum cx25840_video_input {
0031     /* Composite video inputs In1-In8 */
0032     CX25840_COMPOSITE1 = 1,
0033     CX25840_COMPOSITE2,
0034     CX25840_COMPOSITE3,
0035     CX25840_COMPOSITE4,
0036     CX25840_COMPOSITE5,
0037     CX25840_COMPOSITE6,
0038     CX25840_COMPOSITE7,
0039     CX25840_COMPOSITE8,
0040
0041     /*
0042      * S-Video inputs consist of one luma input (In1-In8) ORed with one
0043      * chroma input (In5-In8)
0044      */
0045     CX25840_SVIDEO_LUMA1 = 0x10,
0046     CX25840_SVIDEO_LUMA2 = 0x20,
0047     CX25840_SVIDEO_LUMA3 = 0x30,
0048     CX25840_SVIDEO_LUMA4 = 0x40,
0049     CX25840_SVIDEO_LUMA5 = 0x50,
0050     CX25840_SVIDEO_LUMA6 = 0x60,
0051     CX25840_SVIDEO_LUMA7 = 0x70,
0052     CX25840_SVIDEO_LUMA8 = 0x80,
0053     CX25840_SVIDEO_CHROMA4 = 0x400,
0054     CX25840_SVIDEO_CHROMA5 = 0x500,
0055     CX25840_SVIDEO_CHROMA6 = 0x600,
0056     CX25840_SVIDEO_CHROMA7 = 0x700,
0057     CX25840_SVIDEO_CHROMA8 = 0x800,
0058
0059     /* S-Video aliases for common luma/chroma combinations */
0060     CX25840_SVIDEO1 = 0x510,
0061     CX25840_SVIDEO2 = 0x620,
0062     CX25840_SVIDEO3 = 0x730,
0063     CX25840_SVIDEO4 = 0x840,
0064
0065     /* Allow frames to specify specific input configurations */
0066     CX25840_VIN1_CH1  = 0x80000000,
0067     CX25840_VIN2_CH1  = 0x80000001,
0068     CX25840_VIN3_CH1  = 0x80000002,
0069     CX25840_VIN4_CH1  = 0x80000003,
0070     CX25840_VIN5_CH1  = 0x80000004,
0071     CX25840_VIN6_CH1  = 0x80000005,
0072     CX25840_VIN7_CH1  = 0x80000006,
0073     CX25840_VIN8_CH1  = 0x80000007,
0074     CX25840_VIN4_CH2  = 0x80000000,
0075     CX25840_VIN5_CH2  = 0x80000010,
0076     CX25840_VIN6_CH2  = 0x80000020,
0077     CX25840_NONE_CH2  = 0x80000030,
0078     CX25840_VIN7_CH3  = 0x80000000,
0079     CX25840_VIN8_CH3  = 0x80000040,
0080     CX25840_NONE0_CH3 = 0x80000080,
0081     CX25840_NONE1_CH3 = 0x800000c0,
0082     CX25840_SVIDEO_ON = 0x80000100,
0083     CX25840_COMPONENT_ON = 0x80000200,
0084     CX25840_DIF_ON = 0x80000400,
0085 };
0086
0087 /*
0088  * The defines below are used to set the chip video output settings
0089  * in the generic mode that can be enabled by calling the subdevice
0090  * init core op.
0091  *
0092  * The requested settings can be passed to the init core op as
0093  * @val parameter and to the s_routing video op as @config parameter.
0094  *
0095  * For details please refer to the section 3.7 Video Output Formatting and
0096  * to Video Out Control 1 to 4 registers in the section 5.6 Video Decoder Core
0097  * of the chip datasheet.
0098  */
0099 #define CX25840_VCONFIG_FMT_SHIFT 0
0100 #define CX25840_VCONFIG_FMT_MASK GENMASK(2, 0)
0101 #define CX25840_VCONFIG_FMT_BT601 BIT(0)
0102 #define CX25840_VCONFIG_FMT_BT656 BIT(1)
0103 #define CX25840_VCONFIG_FMT_VIP11 GENMASK(1, 0)
0104 #define CX25840_VCONFIG_FMT_VIP2 BIT(2)
0105
0106 #define CX25840_VCONFIG_RES_SHIFT 3
0107 #define CX25840_VCONFIG_RES_MASK GENMASK(4, 3)
0108 #define CX25840_VCONFIG_RES_8BIT BIT(3)
0109 #define CX25840_VCONFIG_RES_10BIT BIT(4)
0110
0111 #define CX25840_VCONFIG_VBIRAW_SHIFT 5
0112 #define CX25840_VCONFIG_VBIRAW_MASK GENMASK(6, 5)
0113 #define CX25840_VCONFIG_VBIRAW_DISABLED BIT(5)
0114 #define CX25840_VCONFIG_VBIRAW_ENABLED BIT(6)
0115
0116 #define CX25840_VCONFIG_ANCDATA_SHIFT 7
0117 #define CX25840_VCONFIG_ANCDATA_MASK GENMASK(8, 7)
0118 #define CX25840_VCONFIG_ANCDATA_DISABLED BIT(7)
0119 #define CX25840_VCONFIG_ANCDATA_ENABLED BIT(8)
0120
0121 #define CX25840_VCONFIG_TASKBIT_SHIFT 9
0122 #define CX25840_VCONFIG_TASKBIT_MASK GENMASK(10, 9)
0123 #define CX25840_VCONFIG_TASKBIT_ZERO BIT(9)
0124 #define CX25840_VCONFIG_TASKBIT_ONE BIT(10)
0125
0126 #define CX25840_VCONFIG_ACTIVE_SHIFT 11
0127 #define CX25840_VCONFIG_ACTIVE_MASK GENMASK(12, 11)
0128 #define CX25840_VCONFIG_ACTIVE_COMPOSITE BIT(11)
0129 #define CX25840_VCONFIG_ACTIVE_HORIZONTAL BIT(12)
0130
0131 #define CX25840_VCONFIG_VALID_SHIFT 13
0132 #define CX25840_VCONFIG_VALID_MASK GENMASK(14, 13)
0133 #define CX25840_VCONFIG_VALID_NORMAL BIT(13)
0134 #define CX25840_VCONFIG_VALID_ANDACTIVE BIT(14)
0135
0136 #define CX25840_VCONFIG_HRESETW_SHIFT 15
0137 #define CX25840_VCONFIG_HRESETW_MASK GENMASK(16, 15)
0138 #define CX25840_VCONFIG_HRESETW_NORMAL BIT(15)
0139 #define CX25840_VCONFIG_HRESETW_PIXCLK BIT(16)
0140
0141 #define CX25840_VCONFIG_CLKGATE_SHIFT 17
0142 #define CX25840_VCONFIG_CLKGATE_MASK GENMASK(18, 17)
0143 #define CX25840_VCONFIG_CLKGATE_NONE BIT(17)
0144 #define CX25840_VCONFIG_CLKGATE_VALID BIT(18)
0145 #define CX25840_VCONFIG_CLKGATE_VALIDACTIVE GENMASK(18, 17)
0146
0147 #define CX25840_VCONFIG_DCMODE_SHIFT 19
0148 #define CX25840_VCONFIG_DCMODE_MASK GENMASK(20, 19)
0149 #define CX25840_VCONFIG_DCMODE_DWORDS BIT(19)
0150 #define CX25840_VCONFIG_DCMODE_BYTES BIT(20)
0151
0152 #define CX25840_VCONFIG_IDID0S_SHIFT 21
0153 #define CX25840_VCONFIG_IDID0S_MASK GENMASK(22, 21)
0154 #define CX25840_VCONFIG_IDID0S_NORMAL BIT(21)
0155 #define CX25840_VCONFIG_IDID0S_LINECNT BIT(22)
0156
0157 #define CX25840_VCONFIG_VIPCLAMP_SHIFT 23
0158 #define CX25840_VCONFIG_VIPCLAMP_MASK GENMASK(24, 23)
0159 #define CX25840_VCONFIG_VIPCLAMP_ENABLED BIT(23)
0160 #define CX25840_VCONFIG_VIPCLAMP_DISABLED BIT(24)
0161
0162 enum cx25840_audio_input {
0163     /* Audio inputs: serial or In4-In8 */
0164     CX25840_AUDIO_SERIAL,
0165     CX25840_AUDIO4 = 4,
0166     CX25840_AUDIO5,
0167     CX25840_AUDIO6,
0168     CX25840_AUDIO7,
0169     CX25840_AUDIO8,
0170 };
0171
0172 enum cx25840_io_pin {
0173     CX25840_PIN_DVALID_PRGM0 = 0,
0174     CX25840_PIN_FIELD_PRGM1,
0175     CX25840_PIN_HRESET_PRGM2,
0176     CX25840_PIN_VRESET_HCTL_PRGM3,
0177     CX25840_PIN_IRQ_N_PRGM4,
0178     CX25840_PIN_IR_TX_PRGM6,
0179     CX25840_PIN_IR_RX_PRGM5,
0180     CX25840_PIN_GPIO0_PRGM8,
0181     CX25840_PIN_GPIO1_PRGM9,
0182     CX25840_PIN_SA_SDIN,        /* Alternate GP Input only */
0183     CX25840_PIN_SA_SDOUT,       /* Alternate GP Input only */
0184     CX25840_PIN_PLL_CLK_PRGM7,
0185     CX25840_PIN_CHIP_SEL_VIPCLK,    /* Output only */
0186 };
0187
0188 enum cx25840_io_pad {
0189     /* Output pads, these must match the actual chip register values */
0190     CX25840_PAD_DEFAULT = 0,
0191     CX25840_PAD_ACTIVE,
0192     CX25840_PAD_VACTIVE,
0193     CX25840_PAD_CBFLAG,
0194     CX25840_PAD_VID_DATA_EXT0,
0195     CX25840_PAD_VID_DATA_EXT1,
0196     CX25840_PAD_GPO0,
0197     CX25840_PAD_GPO1,
0198     CX25840_PAD_GPO2,
0199     CX25840_PAD_GPO3,
0200     CX25840_PAD_IRQ_N,
0201     CX25840_PAD_AC_SYNC,
0202     CX25840_PAD_AC_SDOUT,
0203     CX25840_PAD_PLL_CLK,
0204     CX25840_PAD_VRESET,
0205     CX25840_PAD_RESERVED,
0206     /* Pads for PLL_CLK output only */
0207     CX25840_PAD_XTI_X5_DLL,
0208     CX25840_PAD_AUX_PLL,
0209     CX25840_PAD_VID_PLL,
0210     CX25840_PAD_XTI,
0211     /* Input Pads */
0212     CX25840_PAD_GPI0,
0213     CX25840_PAD_GPI1,
0214     CX25840_PAD_GPI2,
0215     CX25840_PAD_GPI3,
0216 };
0217
0218 enum cx25840_io_pin_strength {
0219     CX25840_PIN_DRIVE_MEDIUM = 0,
0220     CX25840_PIN_DRIVE_SLOW,
0221     CX25840_PIN_DRIVE_FAST,
0222 };
0223
0224 enum cx23885_io_pin {
0225     CX23885_PIN_IR_RX_GPIO19,
0226     CX23885_PIN_IR_TX_GPIO20,
0227     CX23885_PIN_I2S_SDAT_GPIO21,
0228     CX23885_PIN_I2S_WCLK_GPIO22,
0229     CX23885_PIN_I2S_BCLK_GPIO23,
0230     CX23885_PIN_IRQ_N_GPIO16,
0231 };
0232
0233 enum cx23885_io_pad {
0234     CX23885_PAD_IR_RX,
0235     CX23885_PAD_GPIO19,
0236     CX23885_PAD_IR_TX,
0237     CX23885_PAD_GPIO20,
0238     CX23885_PAD_I2S_SDAT,
0239     CX23885_PAD_GPIO21,
0240     CX23885_PAD_I2S_WCLK,
0241     CX23885_PAD_GPIO22,
0242     CX23885_PAD_I2S_BCLK,
0243     CX23885_PAD_GPIO23,
0244     CX23885_PAD_IRQ_N,
0245     CX23885_PAD_GPIO16,
0246 };
0247
0248 /*
0249  * pvr150_workaround activates a workaround for a hardware bug that is
0250  * present in Hauppauge PVR-150 (and possibly PVR-500) cards that have
0251  * certain NTSC tuners (tveeprom tuner model numbers 85, 99 and 112). The
0252  * audio autodetect fails on some channels for these models and the workaround
0253  * is to select the audio standard explicitly. Many thanks to Hauppauge for
0254  * providing this information.
0255  *
0256  * This platform data only needs to be supplied by the ivtv driver.
0257  */
0258 struct cx25840_platform_data {
0259     int pvr150_workaround;
0260 };
0261
0262 #endif