media/davinci/vpss.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (C) 2009 Texas Instruments Inc
0004  *
0005  * vpss - video processing subsystem module header file.
0006  *
0007  * Include this header file if a driver needs to configure vpss system
0008  * module. It exports a set of library functions  for video drivers to
0009  * configure vpss system module functions such as clock enable/disable,
0010  * vpss interrupt mux to arm, and other common vpss system module
0011  * functions.
0012  */
0013 #ifndef _VPSS_H
0014 #define _VPSS_H
0015
0016 /* selector for ccdc input selection on DM355 */
0017 enum vpss_ccdc_source_sel {
0018     VPSS_CCDCIN,
0019     VPSS_HSSIIN,
0020     VPSS_PGLPBK,    /* for DM365 only */
0021     VPSS_CCDCPG /* for DM365 only */
0022 };
0023
0024 struct vpss_sync_pol {
0025     unsigned int ccdpg_hdpol:1;
0026     unsigned int ccdpg_vdpol:1;
0027 };
0028
0029 struct vpss_pg_frame_size {
0030     short hlpfr;
0031     short pplen;
0032 };
0033
0034 /* Used for enable/disable VPSS Clock */
0035 enum vpss_clock_sel {
0036     /* DM355/DM365 */
0037     VPSS_CCDC_CLOCK,
0038     VPSS_IPIPE_CLOCK,
0039     VPSS_H3A_CLOCK,
0040     VPSS_CFALD_CLOCK,
0041     /*
0042      * When using VPSS_VENC_CLOCK_SEL in vpss_enable_clock() api
0043      * following applies:-
0044      * en = 0 selects ENC_CLK
0045      * en = 1 selects ENC_CLK/2
0046      */
0047     VPSS_VENC_CLOCK_SEL,
0048     VPSS_VPBE_CLOCK,
0049     /* DM365 only clocks */
0050     VPSS_IPIPEIF_CLOCK,
0051     VPSS_RSZ_CLOCK,
0052     VPSS_BL_CLOCK,
0053     /*
0054      * When using VPSS_PCLK_INTERNAL in vpss_enable_clock() api
0055      * following applies:-
0056      * en = 0 disable internal PCLK
0057      * en = 1 enables internal PCLK
0058      */
0059     VPSS_PCLK_INTERNAL,
0060     /*
0061      * When using VPSS_PSYNC_CLOCK_SEL in vpss_enable_clock() api
0062      * following applies:-
0063      * en = 0 enables MMR clock
0064      * en = 1 enables VPSS clock
0065      */
0066     VPSS_PSYNC_CLOCK_SEL,
0067     VPSS_LDC_CLOCK_SEL,
0068     VPSS_OSD_CLOCK_SEL,
0069     VPSS_FDIF_CLOCK,
0070     VPSS_LDC_CLOCK
0071 };
0072
0073 /* select input to ccdc on dm355 */
0074 int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel);
0075 /* enable/disable a vpss clock, 0 - success, -1 - failure */
0076 int vpss_enable_clock(enum vpss_clock_sel clock_sel, int en);
0077 /* set sync polarity, only for DM365*/
0078 void dm365_vpss_set_sync_pol(struct vpss_sync_pol);
0079 /* set the PG_FRAME_SIZE register, only for DM365 */
0080 void dm365_vpss_set_pg_frame_size(struct vpss_pg_frame_size);
0081
0082 /* wbl reset for dm644x */
0083 enum vpss_wbl_sel {
0084     VPSS_PCR_AEW_WBL_0 = 16,
0085     VPSS_PCR_AF_WBL_0,
0086     VPSS_PCR_RSZ4_WBL_0,
0087     VPSS_PCR_RSZ3_WBL_0,
0088     VPSS_PCR_RSZ2_WBL_0,
0089     VPSS_PCR_RSZ1_WBL_0,
0090     VPSS_PCR_PREV_WBL_0,
0091     VPSS_PCR_CCDC_WBL_O,
0092 };
0093 /* clear wbl overflow flag for DM6446 */
0094 int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel);
0095
0096 /* set sync polarity*/
0097 void vpss_set_sync_pol(struct vpss_sync_pol sync);
0098 /* set the PG_FRAME_SIZE register */
0099 void vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size);
0100 /*
0101  * vpss_check_and_clear_interrupt - check and clear interrupt
0102  * @irq - common enumerator for IRQ
0103  *
0104  * Following return values used:-
0105  * 0 - interrupt occurred and cleared
0106  * 1 - interrupt not occurred
0107  * 2 - interrupt status not available
0108  */
0109 int vpss_dma_complete_interrupt(void);
0110
0111 #endif