media/davinci/vpbe_osd.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2007-2009 Texas Instruments Inc
0004  * Copyright (C) 2007 MontaVista Software, Inc.
0005  *
0006  * Andy Lowe (alowe@mvista.com), MontaVista Software
0007  * - Initial version
0008  * Murali Karicheri (mkaricheri@gmail.com), Texas Instruments Ltd.
0009  * - ported to sub device interface
0010  */
0011 #ifndef _OSD_H
0012 #define _OSD_H
0013
0014 #include <media/davinci/vpbe_types.h>
0015
0016 #define DM644X_VPBE_OSD_SUBDEV_NAME "dm644x,vpbe-osd"
0017 #define DM365_VPBE_OSD_SUBDEV_NAME  "dm365,vpbe-osd"
0018 #define DM355_VPBE_OSD_SUBDEV_NAME  "dm355,vpbe-osd"
0019
0020 /**
0021  * enum osd_layer
0022  * @WIN_OSD0: On-Screen Display Window 0
0023  * @WIN_VID0: Video Window 0
0024  * @WIN_OSD1: On-Screen Display Window 1
0025  * @WIN_VID1: Video Window 1
0026  *
0027  * Description:
0028  * An enumeration of the osd display layers.
0029  */
0030 enum osd_layer {
0031     WIN_OSD0,
0032     WIN_VID0,
0033     WIN_OSD1,
0034     WIN_VID1,
0035 };
0036
0037 /**
0038  * enum osd_win_layer
0039  * @OSDWIN_OSD0: On-Screen Display Window 0
0040  * @OSDWIN_OSD1: On-Screen Display Window 1
0041  *
0042  * Description:
0043  * An enumeration of the OSD Window layers.
0044  */
0045 enum osd_win_layer {
0046     OSDWIN_OSD0,
0047     OSDWIN_OSD1,
0048 };
0049
0050 /**
0051  * enum osd_pix_format
0052  * @PIXFMT_1BPP: 1-bit-per-pixel bitmap
0053  * @PIXFMT_2BPP: 2-bits-per-pixel bitmap
0054  * @PIXFMT_4BPP: 4-bits-per-pixel bitmap
0055  * @PIXFMT_8BPP: 8-bits-per-pixel bitmap
0056  * @PIXFMT_RGB565: 16-bits-per-pixel RGB565
0057  * @PIXFMT_YCBCRI: YUV 4:2:2
0058  * @PIXFMT_RGB888: 24-bits-per-pixel RGB888
0059  * @PIXFMT_YCRCBI: YUV 4:2:2 with chroma swap
0060  * @PIXFMT_NV12: YUV 4:2:0 planar
0061  * @PIXFMT_OSD_ATTR: OSD Attribute Window pixel format (4bpp)
0062  *
0063  * Description:
0064  * An enumeration of the DaVinci pixel formats.
0065  */
0066 enum osd_pix_format {
0067     PIXFMT_1BPP = 0,
0068     PIXFMT_2BPP,
0069     PIXFMT_4BPP,
0070     PIXFMT_8BPP,
0071     PIXFMT_RGB565,
0072     PIXFMT_YCBCRI,
0073     PIXFMT_RGB888,
0074     PIXFMT_YCRCBI,
0075     PIXFMT_NV12,
0076     PIXFMT_OSD_ATTR,
0077 };
0078
0079 /**
0080  * enum osd_h_exp_ratio
0081  * @H_EXP_OFF: no expansion (1/1)
0082  * @H_EXP_9_OVER_8: 9/8 expansion ratio
0083  * @H_EXP_3_OVER_2: 3/2 expansion ratio
0084  *
0085  * Description:
0086  * An enumeration of the available horizontal expansion ratios.
0087  */
0088 enum osd_h_exp_ratio {
0089     H_EXP_OFF,
0090     H_EXP_9_OVER_8,
0091     H_EXP_3_OVER_2,
0092 };
0093
0094 /**
0095  * enum osd_v_exp_ratio
0096  * @V_EXP_OFF: no expansion (1/1)
0097  * @V_EXP_6_OVER_5: 6/5 expansion ratio
0098  *
0099  * Description:
0100  * An enumeration of the available vertical expansion ratios.
0101  */
0102 enum osd_v_exp_ratio {
0103     V_EXP_OFF,
0104     V_EXP_6_OVER_5,
0105 };
0106
0107 /**
0108  * enum osd_zoom_factor
0109  * @ZOOM_X1: no zoom (x1)
0110  * @ZOOM_X2: x2 zoom
0111  * @ZOOM_X4: x4 zoom
0112  *
0113  * Description:
0114  * An enumeration of the available zoom factors.
0115  */
0116 enum osd_zoom_factor {
0117     ZOOM_X1,
0118     ZOOM_X2,
0119     ZOOM_X4,
0120 };
0121
0122 /**
0123  * enum osd_clut
0124  * @ROM_CLUT: ROM CLUT
0125  * @RAM_CLUT: RAM CLUT
0126  *
0127  * Description:
0128  * An enumeration of the available Color Lookup Tables (CLUTs).
0129  */
0130 enum osd_clut {
0131     ROM_CLUT,
0132     RAM_CLUT,
0133 };
0134
0135 /**
0136  * enum osd_rom_clut
0137  * @ROM_CLUT0: Macintosh CLUT
0138  * @ROM_CLUT1: CLUT from DM270 and prior devices
0139  *
0140  * Description:
0141  * An enumeration of the ROM Color Lookup Table (CLUT) options.
0142  */
0143 enum osd_rom_clut {
0144     ROM_CLUT0,
0145     ROM_CLUT1,
0146 };
0147
0148 /**
0149  * enum osd_blending_factor
0150  * @OSD_0_VID_8: OSD pixels are fully transparent
0151  * @OSD_1_VID_7: OSD pixels contribute 1/8, video pixels contribute 7/8
0152  * @OSD_2_VID_6: OSD pixels contribute 2/8, video pixels contribute 6/8
0153  * @OSD_3_VID_5: OSD pixels contribute 3/8, video pixels contribute 5/8
0154  * @OSD_4_VID_4: OSD pixels contribute 4/8, video pixels contribute 4/8
0155  * @OSD_5_VID_3: OSD pixels contribute 5/8, video pixels contribute 3/8
0156  * @OSD_6_VID_2: OSD pixels contribute 6/8, video pixels contribute 2/8
0157  * @OSD_8_VID_0: OSD pixels are fully opaque
0158  *
0159  * Description:
0160  * An enumeration of the DaVinci pixel blending factor options.
0161  */
0162 enum osd_blending_factor {
0163     OSD_0_VID_8,
0164     OSD_1_VID_7,
0165     OSD_2_VID_6,
0166     OSD_3_VID_5,
0167     OSD_4_VID_4,
0168     OSD_5_VID_3,
0169     OSD_6_VID_2,
0170     OSD_8_VID_0,
0171 };
0172
0173 /**
0174  * enum osd_blink_interval
0175  * @BLINK_X1: blink interval is 1 vertical refresh cycle
0176  * @BLINK_X2: blink interval is 2 vertical refresh cycles
0177  * @BLINK_X3: blink interval is 3 vertical refresh cycles
0178  * @BLINK_X4: blink interval is 4 vertical refresh cycles
0179  *
0180  * Description:
0181  * An enumeration of the DaVinci pixel blinking interval options.
0182  */
0183 enum osd_blink_interval {
0184     BLINK_X1,
0185     BLINK_X2,
0186     BLINK_X3,
0187     BLINK_X4,
0188 };
0189
0190 /**
0191  * enum osd_cursor_h_width
0192  * @H_WIDTH_1: horizontal line width is 1 pixel
0193  * @H_WIDTH_4: horizontal line width is 4 pixels
0194  * @H_WIDTH_8: horizontal line width is 8 pixels
0195  * @H_WIDTH_12: horizontal line width is 12 pixels
0196  * @H_WIDTH_16: horizontal line width is 16 pixels
0197  * @H_WIDTH_20: horizontal line width is 20 pixels
0198  * @H_WIDTH_24: horizontal line width is 24 pixels
0199  * @H_WIDTH_28: horizontal line width is 28 pixels
0200  */
0201 enum osd_cursor_h_width {
0202     H_WIDTH_1,
0203     H_WIDTH_4,
0204     H_WIDTH_8,
0205     H_WIDTH_12,
0206     H_WIDTH_16,
0207     H_WIDTH_20,
0208     H_WIDTH_24,
0209     H_WIDTH_28,
0210 };
0211
0212 /**
0213  * enum osd_cursor_v_width
0214  * @V_WIDTH_1: vertical line width is 1 line
0215  * @V_WIDTH_2: vertical line width is 2 lines
0216  * @V_WIDTH_4: vertical line width is 4 lines
0217  * @V_WIDTH_6: vertical line width is 6 lines
0218  * @V_WIDTH_8: vertical line width is 8 lines
0219  * @V_WIDTH_10: vertical line width is 10 lines
0220  * @V_WIDTH_12: vertical line width is 12 lines
0221  * @V_WIDTH_14: vertical line width is 14 lines
0222  */
0223 enum osd_cursor_v_width {
0224     V_WIDTH_1,
0225     V_WIDTH_2,
0226     V_WIDTH_4,
0227     V_WIDTH_6,
0228     V_WIDTH_8,
0229     V_WIDTH_10,
0230     V_WIDTH_12,
0231     V_WIDTH_14,
0232 };
0233
0234 /**
0235  * struct osd_cursor_config
0236  * @xsize: horizontal size in pixels
0237  * @ysize: vertical size in lines
0238  * @xpos: horizontal offset in pixels from the left edge of the display
0239  * @ypos: vertical offset in lines from the top of the display
0240  * @interlaced: Non-zero if the display is interlaced, or zero otherwise
0241  * @h_width: horizontal line width
0242  * @v_width: vertical line width
0243  * @clut: the CLUT selector (ROM or RAM) for the cursor color
0244  * @clut_index: an index into the CLUT for the cursor color
0245  *
0246  * Description:
0247  * A structure describing the configuration parameters of the hardware
0248  * rectangular cursor.
0249  */
0250 struct osd_cursor_config {
0251     unsigned xsize;
0252     unsigned ysize;
0253     unsigned xpos;
0254     unsigned ypos;
0255     int interlaced;
0256     enum osd_cursor_h_width h_width;
0257     enum osd_cursor_v_width v_width;
0258     enum osd_clut clut;
0259     unsigned char clut_index;
0260 };
0261
0262 /**
0263  * struct osd_layer_config
0264  * @pixfmt: pixel format
0265  * @line_length: offset in bytes between start of each line in memory
0266  * @xsize: number of horizontal pixels displayed per line
0267  * @ysize: number of lines displayed
0268  * @xpos: horizontal offset in pixels from the left edge of the display
0269  * @ypos: vertical offset in lines from the top of the display
0270  * @interlaced: Non-zero if the display is interlaced, or zero otherwise
0271  *
0272  * Description:
0273  * A structure describing the configuration parameters of an On-Screen Display
0274  * (OSD) or video layer related to how the image is stored in memory.
0275  * @line_length must be a multiple of the cache line size (32 bytes).
0276  */
0277 struct osd_layer_config {
0278     enum osd_pix_format pixfmt;
0279     unsigned line_length;
0280     unsigned xsize;
0281     unsigned ysize;
0282     unsigned xpos;
0283     unsigned ypos;
0284     int interlaced;
0285 };
0286
0287 /* parameters that apply on a per-window (OSD or video) basis */
0288 struct osd_window_state {
0289     int is_allocated;
0290     int is_enabled;
0291     unsigned long fb_base_phys;
0292     enum osd_zoom_factor h_zoom;
0293     enum osd_zoom_factor v_zoom;
0294     struct osd_layer_config lconfig;
0295 };
0296
0297 /* parameters that apply on a per-OSD-window basis */
0298 struct osd_osdwin_state {
0299     enum osd_clut clut;
0300     enum osd_blending_factor blend;
0301     int colorkey_blending;
0302     unsigned colorkey;
0303     int rec601_attenuation;
0304     /* index is pixel value */
0305     unsigned char palette_map[16];
0306 };
0307
0308 /* hardware rectangular cursor parameters */
0309 struct osd_cursor_state {
0310     int is_enabled;
0311     struct osd_cursor_config config;
0312 };
0313
0314 struct osd_state;
0315
0316 struct vpbe_osd_ops {
0317     int (*initialize)(struct osd_state *sd);
0318     int (*request_layer)(struct osd_state *sd, enum osd_layer layer);
0319     void (*release_layer)(struct osd_state *sd, enum osd_layer layer);
0320     int (*enable_layer)(struct osd_state *sd, enum osd_layer layer,
0321                 int otherwin);
0322     void (*disable_layer)(struct osd_state *sd, enum osd_layer layer);
0323     int (*set_layer_config)(struct osd_state *sd, enum osd_layer layer,
0324                 struct osd_layer_config *lconfig);
0325     void (*get_layer_config)(struct osd_state *sd, enum osd_layer layer,
0326                  struct osd_layer_config *lconfig);
0327     void (*start_layer)(struct osd_state *sd, enum osd_layer layer,
0328                 unsigned long fb_base_phys,
0329                 unsigned long cbcr_ofst);
0330     void (*set_left_margin)(struct osd_state *sd, u32 val);
0331     void (*set_top_margin)(struct osd_state *sd, u32 val);
0332     void (*set_interpolation_filter)(struct osd_state *sd, int filter);
0333     int (*set_vid_expansion)(struct osd_state *sd,
0334                     enum osd_h_exp_ratio h_exp,
0335                     enum osd_v_exp_ratio v_exp);
0336     void (*get_vid_expansion)(struct osd_state *sd,
0337                     enum osd_h_exp_ratio *h_exp,
0338                     enum osd_v_exp_ratio *v_exp);
0339     void (*set_zoom)(struct osd_state *sd, enum osd_layer layer,
0340                 enum osd_zoom_factor h_zoom,
0341                 enum osd_zoom_factor v_zoom);
0342 };
0343
0344 struct osd_state {
0345     enum vpbe_version vpbe_type;
0346     spinlock_t lock;
0347     struct device *dev;
0348     dma_addr_t osd_base_phys;
0349     void __iomem *osd_base;
0350     unsigned long osd_size;
0351     /* 1-->the isr will toggle the VID0 ping-pong buffer */
0352     int pingpong;
0353     int interpolation_filter;
0354     int field_inversion;
0355     enum osd_h_exp_ratio osd_h_exp;
0356     enum osd_v_exp_ratio osd_v_exp;
0357     enum osd_h_exp_ratio vid_h_exp;
0358     enum osd_v_exp_ratio vid_v_exp;
0359     enum osd_clut backg_clut;
0360     unsigned backg_clut_index;
0361     enum osd_rom_clut rom_clut;
0362     int is_blinking;
0363     /* attribute window blinking enabled */
0364     enum osd_blink_interval blink;
0365     /* YCbCrI or YCrCbI */
0366     enum osd_pix_format yc_pixfmt;
0367     /* columns are Y, Cb, Cr */
0368     unsigned char clut_ram[256][3];
0369     struct osd_cursor_state cursor;
0370     /* OSD0, VID0, OSD1, VID1 */
0371     struct osd_window_state win[4];
0372     /* OSD0, OSD1 */
0373     struct osd_osdwin_state osdwin[2];
0374     /* OSD device Operations */
0375     struct vpbe_osd_ops ops;
0376 };
0377
0378 struct osd_platform_data {
0379     int  field_inv_wa_enable;
0380 };
0381
0382 #endif