include/linux/via-core.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved.
0004  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
0005  * Copyright 2009-2010 Jonathan Corbet <corbet@lwn.net>
0006  * Copyright 2010 Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
0007  */
0008
0009 #ifndef __VIA_CORE_H__
0010 #define __VIA_CORE_H__
0011 #include <linux/types.h>
0012 #include <linux/io.h>
0013 #include <linux/spinlock.h>
0014 #include <linux/pci.h>
0015
0016 /*
0017  * A description of each known serial I2C/GPIO port.
0018  */
0019 enum via_port_type {
0020     VIA_PORT_NONE = 0,
0021     VIA_PORT_I2C,
0022     VIA_PORT_GPIO,
0023 };
0024
0025 enum via_port_mode {
0026     VIA_MODE_OFF = 0,
0027     VIA_MODE_I2C,       /* Used as I2C port */
0028     VIA_MODE_GPIO,  /* Two GPIO ports */
0029 };
0030
0031 enum viafb_i2c_adap {
0032     VIA_PORT_26 = 0,
0033     VIA_PORT_31,
0034     VIA_PORT_25,
0035     VIA_PORT_2C,
0036     VIA_PORT_3D,
0037 };
0038 #define VIAFB_NUM_PORTS 5
0039
0040 struct via_port_cfg {
0041     enum via_port_type  type;
0042     enum via_port_mode  mode;
0043     u16         io_port;
0044     u8          ioport_index;
0045 };
0046
0047 /*
0048  * Allow subdevs to register suspend/resume hooks.
0049  */
0050 struct viafb_pm_hooks {
0051     struct list_head list;
0052     int (*suspend)(void *private);
0053     int (*resume)(void *private);
0054     void *private;
0055 };
0056
0057 void viafb_pm_register(struct viafb_pm_hooks *hooks);
0058 void viafb_pm_unregister(struct viafb_pm_hooks *hooks);
0059
0060 /*
0061  * This is the global viafb "device" containing stuff needed by
0062  * all subdevs.
0063  */
0064 struct viafb_dev {
0065     struct pci_dev *pdev;
0066     int chip_type;
0067     struct via_port_cfg *port_cfg;
0068     /*
0069      * Spinlock for access to device registers.  Not yet
0070      * globally used.
0071      */
0072     spinlock_t reg_lock;
0073     /*
0074      * The framebuffer MMIO region.  Little, if anything, touches
0075      * this memory directly, and certainly nothing outside of the
0076      * framebuffer device itself.  We *do* have to be able to allocate
0077      * chunks of this memory for other devices, though.
0078      */
0079     unsigned long fbmem_start;
0080     long fbmem_len;
0081     void __iomem *fbmem;
0082 #if defined(CONFIG_VIDEO_VIA_CAMERA) || defined(CONFIG_VIDEO_VIA_CAMERA_MODULE)
0083     long camera_fbmem_offset;
0084     long camera_fbmem_size;
0085 #endif
0086     /*
0087      * The MMIO region for device registers.
0088      */
0089     unsigned long engine_start;
0090     unsigned long engine_len;
0091     void __iomem *engine_mmio;
0092
0093 };
0094
0095 /*
0096  * Interrupt management.
0097  */
0098
0099 void viafb_irq_enable(u32 mask);
0100 void viafb_irq_disable(u32 mask);
0101
0102 /*
0103  * The global interrupt control register and its bits.
0104  */
0105 #define VDE_INTERRUPT   0x200   /* Video interrupt flags/masks */
0106 #define   VDE_I_DVISENSE  0x00000001  /* DVI sense int status */
0107 #define   VDE_I_VBLANK    0x00000002  /* Vertical blank status */
0108 #define   VDE_I_MCCFI     0x00000004  /* MCE compl. frame int status */
0109 #define   VDE_I_VSYNC     0x00000008  /* VGA VSYNC int status */
0110 #define   VDE_I_DMA0DDONE 0x00000010  /* DMA 0 descr done */
0111 #define   VDE_I_DMA0TDONE 0x00000020  /* DMA 0 transfer done */
0112 #define   VDE_I_DMA1DDONE 0x00000040  /* DMA 1 descr done */
0113 #define   VDE_I_DMA1TDONE 0x00000080  /* DMA 1 transfer done */
0114 #define   VDE_I_C1AV      0x00000100  /* Cap Eng 1 act vid end */
0115 #define   VDE_I_HQV0      0x00000200  /* First HQV engine */
0116 #define   VDE_I_HQV1      0x00000400  /* Second HQV engine */
0117 #define   VDE_I_HQV1EN    0x00000800  /* Second HQV engine enable */
0118 #define   VDE_I_C0AV      0x00001000  /* Cap Eng 0 act vid end */
0119 #define   VDE_I_C0VBI     0x00002000  /* Cap Eng 0 VBI end */
0120 #define   VDE_I_C1VBI     0x00004000  /* Cap Eng 1 VBI end */
0121 #define   VDE_I_VSYNC2    0x00008000  /* Sec. Disp. VSYNC */
0122 #define   VDE_I_DVISNSEN  0x00010000  /* DVI sense enable */
0123 #define   VDE_I_VSYNC2EN  0x00020000  /* Sec Disp VSYNC enable */
0124 #define   VDE_I_MCCFIEN   0x00040000  /* MC comp frame int mask enable */
0125 #define   VDE_I_VSYNCEN   0x00080000  /* VSYNC enable */
0126 #define   VDE_I_DMA0DDEN  0x00100000  /* DMA 0 descr done enable */
0127 #define   VDE_I_DMA0TDEN  0x00200000  /* DMA 0 trans done enable */
0128 #define   VDE_I_DMA1DDEN  0x00400000  /* DMA 1 descr done enable */
0129 #define   VDE_I_DMA1TDEN  0x00800000  /* DMA 1 trans done enable */
0130 #define   VDE_I_C1AVEN    0x01000000  /* cap 1 act vid end enable */
0131 #define   VDE_I_HQV0EN    0x02000000  /* First hqv engine enable */
0132 #define   VDE_I_C1VBIEN   0x04000000  /* Cap 1 VBI end enable */
0133 #define   VDE_I_LVDSSI    0x08000000  /* LVDS sense interrupt */
0134 #define   VDE_I_C0AVEN    0x10000000  /* Cap 0 act vid end enable */
0135 #define   VDE_I_C0VBIEN   0x20000000  /* Cap 0 VBI end enable */
0136 #define   VDE_I_LVDSSIEN  0x40000000  /* LVDS Sense enable */
0137 #define   VDE_I_ENABLE    0x80000000  /* Global interrupt enable */
0138
0139 #if defined(CONFIG_VIDEO_VIA_CAMERA) || defined(CONFIG_VIDEO_VIA_CAMERA_MODULE)
0140 /*
0141  * DMA management.
0142  */
0143 int viafb_request_dma(void);
0144 void viafb_release_dma(void);
0145 /* void viafb_dma_copy_out(unsigned int offset, dma_addr_t paddr, int len); */
0146 int viafb_dma_copy_out_sg(unsigned int offset, struct scatterlist *sg, int nsg);
0147
0148 /*
0149  * DMA Controller registers.
0150  */
0151 #define VDMA_MR0    0xe00       /* Mod reg 0 */
0152 #define   VDMA_MR_CHAIN   0x01      /* Chaining mode */
0153 #define   VDMA_MR_TDIE    0x02      /* Transfer done int enable */
0154 #define VDMA_CSR0   0xe04       /* Control/status */
0155 #define   VDMA_C_ENABLE   0x01        /* DMA Enable */
0156 #define   VDMA_C_START    0x02        /* Start a transfer */
0157 #define   VDMA_C_ABORT    0x04        /* Abort a transfer */
0158 #define   VDMA_C_DONE     0x08        /* Transfer is done */
0159 #define VDMA_MARL0  0xe20       /* Mem addr low */
0160 #define VDMA_MARH0  0xe24       /* Mem addr high */
0161 #define VDMA_DAR0   0xe28       /* Device address */
0162 #define VDMA_DQWCR0 0xe2c       /* Count (16-byte) */
0163 #define VDMA_TMR0   0xe30       /* Tile mode reg */
0164 #define VDMA_DPRL0  0xe34       /* Not sure */
0165 #define   VDMA_DPR_IN     0x08      /* Inbound transfer to FB */
0166 #define VDMA_DPRH0  0xe38
0167 #define VDMA_PMR0   (0xe00 + 0x134) /* Pitch mode */
0168
0169 /*
0170  * Useful stuff that probably belongs somewhere global.
0171  */
0172 #define VGA_WIDTH   640
0173 #define VGA_HEIGHT  480
0174 #endif /* CONFIG_VIDEO_VIA_CAMERA */
0175
0176 /*
0177  * Indexed port operations.  Note that these are all multi-op
0178  * functions; every invocation will be racy if you're not holding
0179  * reg_lock.
0180  */
0181
0182 #define VIAStatus   0x3DA  /* Non-indexed port */
0183 #define VIACR       0x3D4
0184 #define VIASR       0x3C4
0185 #define VIAGR       0x3CE
0186 #define VIAAR       0x3C0
0187
0188 static inline u8 via_read_reg(u16 port, u8 index)
0189 {
0190     outb(index, port);
0191     return inb(port + 1);
0192 }
0193
0194 static inline void via_write_reg(u16 port, u8 index, u8 data)
0195 {
0196     outb(index, port);
0197     outb(data, port + 1);
0198 }
0199
0200 static inline void via_write_reg_mask(u16 port, u8 index, u8 data, u8 mask)
0201 {
0202     u8 old;
0203
0204     outb(index, port);
0205     old = inb(port + 1);
0206     outb((data & mask) | (old & ~mask), port + 1);
0207 }
0208
0209 #define VIA_MISC_REG_READ   0x03CC
0210 #define VIA_MISC_REG_WRITE  0x03C2
0211
0212 static inline void via_write_misc_reg_mask(u8 data, u8 mask)
0213 {
0214     u8 old = inb(VIA_MISC_REG_READ);
0215     outb((data & mask) | (old & ~mask), VIA_MISC_REG_WRITE);
0216 }
0217
0218
0219 #endif /* __VIA_CORE_H__ */