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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * R8A66597 driver platform data
0004  *
0005  * Copyright (C) 2009  Renesas Solutions Corp.
0006  *
0007  * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
0008  */
0009 
0010 #ifndef __LINUX_USB_R8A66597_H
0011 #define __LINUX_USB_R8A66597_H
0012 
0013 #define R8A66597_PLATDATA_XTAL_12MHZ    0x01
0014 #define R8A66597_PLATDATA_XTAL_24MHZ    0x02
0015 #define R8A66597_PLATDATA_XTAL_48MHZ    0x03
0016 
0017 struct r8a66597_platdata {
0018     /* This callback can control port power instead of DVSTCTR register. */
0019     void (*port_power)(int port, int power);
0020 
0021     /* This parameter is for BUSWAIT */
0022     u16     buswait;
0023 
0024     /* set one = on chip controller, set zero = external controller */
0025     unsigned    on_chip:1;
0026 
0027     /* (external controller only) set R8A66597_PLATDATA_XTAL_nnMHZ */
0028     unsigned    xtal:2;
0029 
0030     /* set one = 3.3V, set zero = 1.5V */
0031     unsigned    vif:1;
0032 
0033     /* set one = big endian, set zero = little endian */
0034     unsigned    endian:1;
0035 
0036     /* (external controller only) set one = WR0_N shorted to WR1_N */
0037     unsigned    wr0_shorted_to_wr1:1;
0038 
0039     /* set one = using SUDMAC */
0040     unsigned    sudmac:1;
0041 };
0042 
0043 /* Register definitions */
0044 #define SYSCFG0     0x00
0045 #define SYSCFG1     0x02
0046 #define SYSSTS0     0x04
0047 #define SYSSTS1     0x06
0048 #define DVSTCTR0    0x08
0049 #define DVSTCTR1    0x0A
0050 #define TESTMODE    0x0C
0051 #define PINCFG      0x0E
0052 #define DMA0CFG     0x10
0053 #define DMA1CFG     0x12
0054 #define CFIFO       0x14
0055 #define D0FIFO      0x18
0056 #define D1FIFO      0x1C
0057 #define CFIFOSEL    0x20
0058 #define CFIFOCTR    0x22
0059 #define CFIFOSIE    0x24
0060 #define D0FIFOSEL   0x28
0061 #define D0FIFOCTR   0x2A
0062 #define D1FIFOSEL   0x2C
0063 #define D1FIFOCTR   0x2E
0064 #define INTENB0     0x30
0065 #define INTENB1     0x32
0066 #define INTENB2     0x34
0067 #define BRDYENB     0x36
0068 #define NRDYENB     0x38
0069 #define BEMPENB     0x3A
0070 #define SOFCFG      0x3C
0071 #define INTSTS0     0x40
0072 #define INTSTS1     0x42
0073 #define INTSTS2     0x44
0074 #define BRDYSTS     0x46
0075 #define NRDYSTS     0x48
0076 #define BEMPSTS     0x4A
0077 #define FRMNUM      0x4C
0078 #define UFRMNUM     0x4E
0079 #define USBADDR     0x50
0080 #define USBREQ      0x54
0081 #define USBVAL      0x56
0082 #define USBINDX     0x58
0083 #define USBLENG     0x5A
0084 #define DCPCFG      0x5C
0085 #define DCPMAXP     0x5E
0086 #define DCPCTR      0x60
0087 #define PIPESEL     0x64
0088 #define PIPECFG     0x68
0089 #define PIPEBUF     0x6A
0090 #define PIPEMAXP    0x6C
0091 #define PIPEPERI    0x6E
0092 #define PIPE1CTR    0x70
0093 #define PIPE2CTR    0x72
0094 #define PIPE3CTR    0x74
0095 #define PIPE4CTR    0x76
0096 #define PIPE5CTR    0x78
0097 #define PIPE6CTR    0x7A
0098 #define PIPE7CTR    0x7C
0099 #define PIPE8CTR    0x7E
0100 #define PIPE9CTR    0x80
0101 #define PIPE1TRE    0x90
0102 #define PIPE1TRN    0x92
0103 #define PIPE2TRE    0x94
0104 #define PIPE2TRN    0x96
0105 #define PIPE3TRE    0x98
0106 #define PIPE3TRN    0x9A
0107 #define PIPE4TRE    0x9C
0108 #define PIPE4TRN    0x9E
0109 #define PIPE5TRE    0xA0
0110 #define PIPE5TRN    0xA2
0111 #define DEVADD0     0xD0
0112 #define DEVADD1     0xD2
0113 #define DEVADD2     0xD4
0114 #define DEVADD3     0xD6
0115 #define DEVADD4     0xD8
0116 #define DEVADD5     0xDA
0117 #define DEVADD6     0xDC
0118 #define DEVADD7     0xDE
0119 #define DEVADD8     0xE0
0120 #define DEVADD9     0xE2
0121 #define DEVADDA     0xE4
0122 
0123 /* System Configuration Control Register */
0124 #define XTAL        0xC000  /* b15-14: Crystal selection */
0125 #define   XTAL48     0x8000   /* 48MHz */
0126 #define   XTAL24     0x4000   /* 24MHz */
0127 #define   XTAL12     0x0000   /* 12MHz */
0128 #define XCKE        0x2000  /* b13: External clock enable */
0129 #define PLLC        0x0800  /* b11: PLL control */
0130 #define SCKE        0x0400  /* b10: USB clock enable */
0131 #define PCSDIS      0x0200  /* b9: not CS wakeup */
0132 #define LPSME       0x0100  /* b8: Low power sleep mode */
0133 #define HSE     0x0080  /* b7: Hi-speed enable */
0134 #define DCFM        0x0040  /* b6: Controller function select  */
0135 #define DRPD        0x0020  /* b5: D+/- pull down control */
0136 #define DPRPU       0x0010  /* b4: D+ pull up control */
0137 #define USBE        0x0001  /* b0: USB module operation enable */
0138 
0139 /* System Configuration Status Register */
0140 #define OVCBIT      0x8000  /* b15-14: Over-current bit */
0141 #define OVCMON      0xC000  /* b15-14: Over-current monitor */
0142 #define SOFEA       0x0020  /* b5: SOF monitor */
0143 #define IDMON       0x0004  /* b3: ID-pin monitor */
0144 #define LNST        0x0003  /* b1-0: D+, D- line status */
0145 #define   SE1        0x0003   /* SE1 */
0146 #define   FS_KSTS    0x0002   /* Full-Speed K State */
0147 #define   FS_JSTS    0x0001   /* Full-Speed J State */
0148 #define   LS_JSTS    0x0002   /* Low-Speed J State */
0149 #define   LS_KSTS    0x0001   /* Low-Speed K State */
0150 #define   SE0        0x0000   /* SE0 */
0151 
0152 /* Device State Control Register */
0153 #define EXTLP0      0x0400  /* b10: External port */
0154 #define VBOUT       0x0200  /* b9: VBUS output */
0155 #define WKUP        0x0100  /* b8: Remote wakeup */
0156 #define RWUPE       0x0080  /* b7: Remote wakeup sense */
0157 #define USBRST      0x0040  /* b6: USB reset enable */
0158 #define RESUME      0x0020  /* b5: Resume enable */
0159 #define UACT        0x0010  /* b4: USB bus enable */
0160 #define RHST        0x0007  /* b1-0: Reset handshake status */
0161 #define   HSPROC     0x0004   /* HS handshake is processing */
0162 #define   HSMODE     0x0003   /* Hi-Speed mode */
0163 #define   FSMODE     0x0002   /* Full-Speed mode */
0164 #define   LSMODE     0x0001   /* Low-Speed mode */
0165 #define   UNDECID    0x0000   /* Undecided */
0166 
0167 /* Test Mode Register */
0168 #define UTST            0x000F  /* b3-0: Test select */
0169 #define   H_TST_PACKET       0x000C   /* HOST TEST Packet */
0170 #define   H_TST_SE0_NAK      0x000B   /* HOST TEST SE0 NAK */
0171 #define   H_TST_K        0x000A   /* HOST TEST K */
0172 #define   H_TST_J        0x0009   /* HOST TEST J */
0173 #define   H_TST_NORMAL       0x0000   /* HOST Normal Mode */
0174 #define   P_TST_PACKET       0x0004   /* PERI TEST Packet */
0175 #define   P_TST_SE0_NAK      0x0003   /* PERI TEST SE0 NAK */
0176 #define   P_TST_K        0x0002   /* PERI TEST K */
0177 #define   P_TST_J        0x0001   /* PERI TEST J */
0178 #define   P_TST_NORMAL       0x0000   /* PERI Normal Mode */
0179 
0180 /* Data Pin Configuration Register */
0181 #define LDRV            0x8000  /* b15: Drive Current Adjust */
0182 #define   VIF1            0x0000        /* VIF = 1.8V */
0183 #define   VIF3            0x8000        /* VIF = 3.3V */
0184 #define INTA            0x0001  /* b1: USB INT-pin active */
0185 
0186 /* DMAx Pin Configuration Register */
0187 #define DREQA           0x4000  /* b14: Dreq active select */
0188 #define BURST           0x2000  /* b13: Burst mode */
0189 #define DACKA           0x0400  /* b10: Dack active select */
0190 #define DFORM           0x0380  /* b9-7: DMA mode select */
0191 #define   CPU_ADR_RD_WR      0x0000   /* Address + RD/WR mode (CPU bus) */
0192 #define   CPU_DACK_RD_WR     0x0100   /* DACK + RD/WR mode (CPU bus) */
0193 #define   CPU_DACK_ONLY      0x0180   /* DACK only mode (CPU bus) */
0194 #define   SPLIT_DACK_ONLY    0x0200   /* DACK only mode (SPLIT bus) */
0195 #define DENDA           0x0040  /* b6: Dend active select */
0196 #define PKTM            0x0020  /* b5: Packet mode */
0197 #define DENDE           0x0010  /* b4: Dend enable */
0198 #define OBUS            0x0004  /* b2: OUTbus mode */
0199 
0200 /* CFIFO/DxFIFO Port Select Register */
0201 #define RCNT        0x8000  /* b15: Read count mode */
0202 #define REW     0x4000  /* b14: Buffer rewind */
0203 #define DCLRM       0x2000  /* b13: DMA buffer clear mode */
0204 #define DREQE       0x1000  /* b12: DREQ output enable */
0205 #define   MBW_8      0x0000   /*  8bit */
0206 #define   MBW_16     0x0400   /* 16bit */
0207 #define   MBW_32     0x0800   /* 32bit */
0208 #define BIGEND      0x0100  /* b8: Big endian mode */
0209 #define   BYTE_LITTLE    0x0000     /* little dendian */
0210 #define   BYTE_BIG   0x0100     /* big endifan */
0211 #define ISEL        0x0020  /* b5: DCP FIFO port direction select */
0212 #define CURPIPE     0x000F  /* b2-0: PIPE select */
0213 
0214 /* CFIFO/DxFIFO Port Control Register */
0215 #define BVAL        0x8000  /* b15: Buffer valid flag */
0216 #define BCLR        0x4000  /* b14: Buffer clear */
0217 #define FRDY        0x2000  /* b13: FIFO ready */
0218 #define DTLN        0x0FFF  /* b11-0: FIFO received data length */
0219 
0220 /* Interrupt Enable Register 0 */
0221 #define VBSE    0x8000  /* b15: VBUS interrupt */
0222 #define RSME    0x4000  /* b14: Resume interrupt */
0223 #define SOFE    0x2000  /* b13: Frame update interrupt */
0224 #define DVSE    0x1000  /* b12: Device state transition interrupt */
0225 #define CTRE    0x0800  /* b11: Control transfer stage transition interrupt */
0226 #define BEMPE   0x0400  /* b10: Buffer empty interrupt */
0227 #define NRDYE   0x0200  /* b9: Buffer not ready interrupt */
0228 #define BRDYE   0x0100  /* b8: Buffer ready interrupt */
0229 
0230 /* Interrupt Enable Register 1 */
0231 #define OVRCRE      0x8000  /* b15: Over-current interrupt */
0232 #define BCHGE       0x4000  /* b14: USB us chenge interrupt */
0233 #define DTCHE       0x1000  /* b12: Detach sense interrupt */
0234 #define ATTCHE      0x0800  /* b11: Attach sense interrupt */
0235 #define EOFERRE     0x0040  /* b6: EOF error interrupt */
0236 #define SIGNE       0x0020  /* b5: SETUP IGNORE interrupt */
0237 #define SACKE       0x0010  /* b4: SETUP ACK interrupt */
0238 
0239 /* BRDY Interrupt Enable/Status Register */
0240 #define BRDY9       0x0200  /* b9: PIPE9 */
0241 #define BRDY8       0x0100  /* b8: PIPE8 */
0242 #define BRDY7       0x0080  /* b7: PIPE7 */
0243 #define BRDY6       0x0040  /* b6: PIPE6 */
0244 #define BRDY5       0x0020  /* b5: PIPE5 */
0245 #define BRDY4       0x0010  /* b4: PIPE4 */
0246 #define BRDY3       0x0008  /* b3: PIPE3 */
0247 #define BRDY2       0x0004  /* b2: PIPE2 */
0248 #define BRDY1       0x0002  /* b1: PIPE1 */
0249 #define BRDY0       0x0001  /* b1: PIPE0 */
0250 
0251 /* NRDY Interrupt Enable/Status Register */
0252 #define NRDY9       0x0200  /* b9: PIPE9 */
0253 #define NRDY8       0x0100  /* b8: PIPE8 */
0254 #define NRDY7       0x0080  /* b7: PIPE7 */
0255 #define NRDY6       0x0040  /* b6: PIPE6 */
0256 #define NRDY5       0x0020  /* b5: PIPE5 */
0257 #define NRDY4       0x0010  /* b4: PIPE4 */
0258 #define NRDY3       0x0008  /* b3: PIPE3 */
0259 #define NRDY2       0x0004  /* b2: PIPE2 */
0260 #define NRDY1       0x0002  /* b1: PIPE1 */
0261 #define NRDY0       0x0001  /* b1: PIPE0 */
0262 
0263 /* BEMP Interrupt Enable/Status Register */
0264 #define BEMP9       0x0200  /* b9: PIPE9 */
0265 #define BEMP8       0x0100  /* b8: PIPE8 */
0266 #define BEMP7       0x0080  /* b7: PIPE7 */
0267 #define BEMP6       0x0040  /* b6: PIPE6 */
0268 #define BEMP5       0x0020  /* b5: PIPE5 */
0269 #define BEMP4       0x0010  /* b4: PIPE4 */
0270 #define BEMP3       0x0008  /* b3: PIPE3 */
0271 #define BEMP2       0x0004  /* b2: PIPE2 */
0272 #define BEMP1       0x0002  /* b1: PIPE1 */
0273 #define BEMP0       0x0001  /* b0: PIPE0 */
0274 
0275 /* SOF Pin Configuration Register */
0276 #define TRNENSEL    0x0100  /* b8: Select transaction enable period */
0277 #define BRDYM       0x0040  /* b6: BRDY clear timing */
0278 #define INTL        0x0020  /* b5: Interrupt sense select */
0279 #define EDGESTS     0x0010  /* b4:  */
0280 #define SOFMODE     0x000C  /* b3-2: SOF pin select */
0281 #define   SOF_125US  0x0008   /* SOF OUT 125us Frame Signal */
0282 #define   SOF_1MS    0x0004   /* SOF OUT 1ms Frame Signal */
0283 #define   SOF_DISABLE    0x0000   /* SOF OUT Disable */
0284 
0285 /* Interrupt Status Register 0 */
0286 #define VBINT   0x8000  /* b15: VBUS interrupt */
0287 #define RESM    0x4000  /* b14: Resume interrupt */
0288 #define SOFR    0x2000  /* b13: SOF frame update interrupt */
0289 #define DVST    0x1000  /* b12: Device state transition interrupt */
0290 #define CTRT    0x0800  /* b11: Control transfer stage transition interrupt */
0291 #define BEMP    0x0400  /* b10: Buffer empty interrupt */
0292 #define NRDY    0x0200  /* b9: Buffer not ready interrupt */
0293 #define BRDY    0x0100  /* b8: Buffer ready interrupt */
0294 #define VBSTS   0x0080  /* b7: VBUS input port */
0295 #define DVSQ    0x0070  /* b6-4: Device state */
0296 #define   DS_SPD_CNFG    0x0070   /* Suspend Configured */
0297 #define   DS_SPD_ADDR    0x0060   /* Suspend Address */
0298 #define   DS_SPD_DFLT    0x0050   /* Suspend Default */
0299 #define   DS_SPD_POWR    0x0040   /* Suspend Powered */
0300 #define   DS_SUSP    0x0040   /* Suspend */
0301 #define   DS_CNFG    0x0030   /* Configured */
0302 #define   DS_ADDS    0x0020   /* Address */
0303 #define   DS_DFLT    0x0010   /* Default */
0304 #define   DS_POWR    0x0000   /* Powered */
0305 #define DVSQS       0x0030  /* b5-4: Device state */
0306 #define VALID       0x0008  /* b3: Setup packet detected flag */
0307 #define CTSQ        0x0007  /* b2-0: Control transfer stage */
0308 #define   CS_SQER    0x0006   /* Sequence error */
0309 #define   CS_WRND    0x0005   /* Control write nodata status stage */
0310 #define   CS_WRSS    0x0004   /* Control write status stage */
0311 #define   CS_WRDS    0x0003   /* Control write data stage */
0312 #define   CS_RDSS    0x0002   /* Control read status stage */
0313 #define   CS_RDDS    0x0001   /* Control read data stage */
0314 #define   CS_IDST    0x0000   /* Idle or setup stage */
0315 
0316 /* Interrupt Status Register 1 */
0317 #define OVRCR       0x8000  /* b15: Over-current interrupt */
0318 #define BCHG        0x4000  /* b14: USB bus chenge interrupt */
0319 #define DTCH        0x1000  /* b12: Detach sense interrupt */
0320 #define ATTCH       0x0800  /* b11: Attach sense interrupt */
0321 #define EOFERR      0x0040  /* b6: EOF-error interrupt */
0322 #define SIGN        0x0020  /* b5: Setup ignore interrupt */
0323 #define SACK        0x0010  /* b4: Setup acknowledge interrupt */
0324 
0325 /* Frame Number Register */
0326 #define OVRN        0x8000  /* b15: Overrun error */
0327 #define CRCE        0x4000  /* b14: Received data error */
0328 #define FRNM        0x07FF  /* b10-0: Frame number */
0329 
0330 /* Micro Frame Number Register */
0331 #define UFRNM       0x0007  /* b2-0: Micro frame number */
0332 
0333 /* Default Control Pipe Maxpacket Size Register */
0334 /* Pipe Maxpacket Size Register */
0335 #define DEVSEL  0xF000  /* b15-14: Device address select */
0336 #define MAXP    0x007F  /* b6-0: Maxpacket size of default control pipe */
0337 
0338 /* Default Control Pipe Control Register */
0339 #define BSTS        0x8000  /* b15: Buffer status */
0340 #define SUREQ       0x4000  /* b14: Send USB request  */
0341 #define CSCLR       0x2000  /* b13: complete-split status clear */
0342 #define CSSTS       0x1000  /* b12: complete-split status */
0343 #define SUREQCLR    0x0800  /* b11: stop setup request */
0344 #define SQCLR       0x0100  /* b8: Sequence toggle bit clear */
0345 #define SQSET       0x0080  /* b7: Sequence toggle bit set */
0346 #define SQMON       0x0040  /* b6: Sequence toggle bit monitor */
0347 #define PBUSY       0x0020  /* b5: pipe busy */
0348 #define PINGE       0x0010  /* b4: ping enable */
0349 #define CCPL        0x0004  /* b2: Enable control transfer complete */
0350 #define PID     0x0003  /* b1-0: Response PID */
0351 #define   PID_STALL11    0x0003   /* STALL */
0352 #define   PID_STALL  0x0002   /* STALL */
0353 #define   PID_BUF    0x0001   /* BUF */
0354 #define   PID_NAK    0x0000   /* NAK */
0355 
0356 /* Pipe Window Select Register */
0357 #define PIPENM      0x0007  /* b2-0: Pipe select */
0358 
0359 /* Pipe Configuration Register */
0360 #define R8A66597_TYP    0xC000  /* b15-14: Transfer type */
0361 #define   R8A66597_ISO   0xC000       /* Isochronous */
0362 #define   R8A66597_INT   0x8000       /* Interrupt */
0363 #define   R8A66597_BULK  0x4000       /* Bulk */
0364 #define R8A66597_BFRE   0x0400  /* b10: Buffer ready interrupt mode select */
0365 #define R8A66597_DBLB   0x0200  /* b9: Double buffer mode select */
0366 #define R8A66597_CNTMD  0x0100  /* b8: Continuous transfer mode select */
0367 #define R8A66597_SHTNAK 0x0080  /* b7: Transfer end NAK */
0368 #define R8A66597_DIR    0x0010  /* b4: Transfer direction select */
0369 #define R8A66597_EPNUM  0x000F  /* b3-0: Eendpoint number select */
0370 
0371 /* Pipe Buffer Configuration Register */
0372 #define BUFSIZE     0x7C00  /* b14-10: Pipe buffer size */
0373 #define BUFNMB      0x007F  /* b6-0: Pipe buffer number */
0374 #define PIPE0BUF    256
0375 #define PIPExBUF    64
0376 
0377 /* Pipe Maxpacket Size Register */
0378 #define MXPS        0x07FF  /* b10-0: Maxpacket size */
0379 
0380 /* Pipe Cycle Configuration Register */
0381 #define IFIS    0x1000  /* b12: Isochronous in-buffer flush mode select */
0382 #define IITV    0x0007  /* b2-0: Isochronous interval */
0383 
0384 /* Pipex Control Register */
0385 #define BSTS    0x8000  /* b15: Buffer status */
0386 #define INBUFM  0x4000  /* b14: IN buffer monitor (Only for PIPE1 to 5) */
0387 #define CSCLR   0x2000  /* b13: complete-split status clear */
0388 #define CSSTS   0x1000  /* b12: complete-split status */
0389 #define ATREPM  0x0400  /* b10: Auto repeat mode */
0390 #define ACLRM   0x0200  /* b9: Out buffer auto clear mode */
0391 #define SQCLR   0x0100  /* b8: Sequence toggle bit clear */
0392 #define SQSET   0x0080  /* b7: Sequence toggle bit set */
0393 #define SQMON   0x0040  /* b6: Sequence toggle bit monitor */
0394 #define PBUSY   0x0020  /* b5: pipe busy */
0395 #define PID 0x0003  /* b1-0: Response PID */
0396 
0397 /* PIPExTRE */
0398 #define TRENB       0x0200  /* b9: Transaction counter enable */
0399 #define TRCLR       0x0100  /* b8: Transaction counter clear */
0400 
0401 /* PIPExTRN */
0402 #define TRNCNT      0xFFFF  /* b15-0: Transaction counter */
0403 
0404 /* DEVADDx */
0405 #define UPPHUB      0x7800
0406 #define HUBPORT     0x0700
0407 #define USBSPD      0x00C0
0408 #define RTPORT      0x0001
0409 
0410 /* SUDMAC registers */
0411 #define CH0CFG      0x00
0412 #define CH1CFG      0x04
0413 #define CH0BA       0x10
0414 #define CH1BA       0x14
0415 #define CH0BBC      0x18
0416 #define CH1BBC      0x1C
0417 #define CH0CA       0x20
0418 #define CH1CA       0x24
0419 #define CH0CBC      0x28
0420 #define CH1CBC      0x2C
0421 #define CH0DEN      0x30
0422 #define CH1DEN      0x34
0423 #define DSTSCLR     0x38
0424 #define DBUFCTRL    0x3C
0425 #define DINTCTRL    0x40
0426 #define DINTSTS     0x44
0427 #define DINTSTSCLR  0x48
0428 #define CH0SHCTRL   0x50
0429 #define CH1SHCTRL   0x54
0430 
0431 /* SUDMAC Configuration Registers */
0432 #define SENDBUFM    0x1000 /* b12: Transmit Buffer Mode */
0433 #define RCVENDM     0x0100 /* b8: Receive Data Transfer End Mode */
0434 #define LBA_WAIT    0x0030 /* b5-4: Local Bus Access Wait */
0435 
0436 /* DMA Enable Registers */
0437 #define DEN     0x0001 /* b1: DMA Transfer Enable */
0438 
0439 /* DMA Status Clear Register */
0440 #define CH1STCLR    0x0002 /* b2: Ch1 DMA Status Clear */
0441 #define CH0STCLR    0x0001 /* b1: Ch0 DMA Status Clear */
0442 
0443 /* DMA Buffer Control Register */
0444 #define CH1BUFW     0x0200 /* b9: Ch1 DMA Buffer Data Transfer Enable */
0445 #define CH0BUFW     0x0100 /* b8: Ch0 DMA Buffer Data Transfer Enable */
0446 #define CH1BUFS     0x0002 /* b2: Ch1 DMA Buffer Data Status */
0447 #define CH0BUFS     0x0001 /* b1: Ch0 DMA Buffer Data Status */
0448 
0449 /* DMA Interrupt Control Register */
0450 #define CH1ERRE     0x0200 /* b9: Ch1 SHwy Res Err Detect Int Enable */
0451 #define CH0ERRE     0x0100 /* b8: Ch0 SHwy Res Err Detect Int Enable */
0452 #define CH1ENDE     0x0002 /* b2: Ch1 DMA Transfer End Int Enable */
0453 #define CH0ENDE     0x0001 /* b1: Ch0 DMA Transfer End Int Enable */
0454 
0455 /* DMA Interrupt Status Register */
0456 #define CH1ERRS     0x0200 /* b9: Ch1 SHwy Res Err Detect Int Status */
0457 #define CH0ERRS     0x0100 /* b8: Ch0 SHwy Res Err Detect Int Status */
0458 #define CH1ENDS     0x0002 /* b2: Ch1 DMA Transfer End Int Status */
0459 #define CH0ENDS     0x0001 /* b1: Ch0 DMA Transfer End Int Status */
0460 
0461 /* DMA Interrupt Status Clear Register */
0462 #define CH1ERRC     0x0200 /* b9: Ch1 SHwy Res Err Detect Int Stat Clear */
0463 #define CH0ERRC     0x0100 /* b8: Ch0 SHwy Res Err Detect Int Stat Clear */
0464 #define CH1ENDC     0x0002 /* b2: Ch1 DMA Transfer End Int Stat Clear */
0465 #define CH0ENDC     0x0001 /* b1: Ch0 DMA Transfer End Int Stat Clear */
0466 
0467 #endif /* __LINUX_USB_R8A66597_H */
0468
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