linux/usb/ehci_def.h

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright (c) 2001-2002 by David Brownell
0004  */
0005
0006 #ifndef __LINUX_USB_EHCI_DEF_H
0007 #define __LINUX_USB_EHCI_DEF_H
0008
0009 #include <linux/usb/ehci-dbgp.h>
0010
0011 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
0012
0013 /* Section 2.2 Host Controller Capability Registers */
0014 struct ehci_caps {
0015     /* these fields are specified as 8 and 16 bit registers,
0016      * but some hosts can't perform 8 or 16 bit PCI accesses.
0017      * some hosts treat caplength and hciversion as parts of a 32-bit
0018      * register, others treat them as two separate registers, this
0019      * affects the memory map for big endian controllers.
0020      */
0021     u32     hc_capbase;
0022 #define HC_LENGTH(ehci, p)  (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \
0023                 (ehci_big_endian_capbase(ehci) ? 24 : 0)))
0024 #define HC_VERSION(ehci, p) (0xffff&((p) >> /* bits 31:16 / offset 02h */ \
0025                 (ehci_big_endian_capbase(ehci) ? 0 : 16)))
0026     u32     hcs_params;     /* HCSPARAMS - offset 0x4 */
0027 #define HCS_DEBUG_PORT(p)   (((p)>>20)&0xf) /* bits 23:20, debug port? */
0028 #define HCS_INDICATOR(p)    ((p)&(1 << 16)) /* true: has port indicators */
0029 #define HCS_N_CC(p)     (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
0030 #define HCS_N_PCC(p)        (((p)>>8)&0xf)  /* bits 11:8, ports per CC */
0031 #define HCS_PORTROUTED(p)   ((p)&(1 << 7))  /* true: port routing */
0032 #define HCS_PPC(p)      ((p)&(1 << 4))  /* true: port power control */
0033 #define HCS_N_PORTS(p)      (((p)>>0)&0xf)  /* bits 3:0, ports on HC */
0034 #define HCS_N_PORTS_MAX     15      /* N_PORTS valid 0x1-0xF */
0035
0036     u32     hcc_params;      /* HCCPARAMS - offset 0x8 */
0037 /* EHCI 1.1 addendum */
0038 #define HCC_32FRAME_PERIODIC_LIST(p)    ((p)&(1 << 19))
0039 #define HCC_PER_PORT_CHANGE_EVENT(p)    ((p)&(1 << 18))
0040 #define HCC_LPM(p)          ((p)&(1 << 17))
0041 #define HCC_HW_PREFETCH(p)      ((p)&(1 << 16))
0042
0043 #define HCC_EXT_CAPS(p)     (((p)>>8)&0xff) /* for pci extended caps */
0044 #define HCC_ISOC_CACHE(p)       ((p)&(1 << 7))  /* true: can cache isoc frame */
0045 #define HCC_ISOC_THRES(p)       (((p)>>4)&0x7)  /* bits 6:4, uframes cached */
0046 #define HCC_CANPARK(p)      ((p)&(1 << 2))  /* true: can park on async qh */
0047 #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
0048 #define HCC_64BIT_ADDR(p)       ((p)&(1))       /* true: can use 64-bit addr */
0049     u8      portroute[8];    /* nibbles for routing - offset 0xC */
0050 };
0051
0052
0053 /* Section 2.3 Host Controller Operational Registers */
0054 struct ehci_regs {
0055
0056     /* USBCMD: offset 0x00 */
0057     u32     command;
0058
0059 /* EHCI 1.1 addendum */
0060 #define CMD_HIRD    (0xf<<24)   /* host initiated resume duration */
0061 #define CMD_PPCEE   (1<<15)     /* per port change event enable */
0062 #define CMD_FSP     (1<<14)     /* fully synchronized prefetch */
0063 #define CMD_ASPE    (1<<13)     /* async schedule prefetch enable */
0064 #define CMD_PSPE    (1<<12)     /* periodic schedule prefetch enable */
0065 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
0066 #define CMD_PARK    (1<<11)     /* enable "park" on async qh */
0067 #define CMD_PARK_CNT(c) (((c)>>8)&3)    /* how many transfers to park for */
0068 #define CMD_LRESET  (1<<7)      /* partial reset (no ports, etc) */
0069 #define CMD_IAAD    (1<<6)      /* "doorbell" interrupt async advance */
0070 #define CMD_ASE     (1<<5)      /* async schedule enable */
0071 #define CMD_PSE     (1<<4)      /* periodic schedule enable */
0072 /* 3:2 is periodic frame list size */
0073 #define CMD_RESET   (1<<1)      /* reset HC not bus */
0074 #define CMD_RUN     (1<<0)      /* start/stop HC */
0075
0076     /* USBSTS: offset 0x04 */
0077     u32     status;
0078 #define STS_PPCE_MASK   (0xff<<16)  /* Per-Port change event 1-16 */
0079 #define STS_ASS     (1<<15)     /* Async Schedule Status */
0080 #define STS_PSS     (1<<14)     /* Periodic Schedule Status */
0081 #define STS_RECL    (1<<13)     /* Reclamation */
0082 #define STS_HALT    (1<<12)     /* Not running (any reason) */
0083 /* some bits reserved */
0084     /* these STS_* flags are also intr_enable bits (USBINTR) */
0085 #define STS_IAA     (1<<5)      /* Interrupted on async advance */
0086 #define STS_FATAL   (1<<4)      /* such as some PCI access errors */
0087 #define STS_FLR     (1<<3)      /* frame list rolled over */
0088 #define STS_PCD     (1<<2)      /* port change detect */
0089 #define STS_ERR     (1<<1)      /* "error" completion (overflow, ...) */
0090 #define STS_INT     (1<<0)      /* "normal" completion (short, ...) */
0091
0092     /* USBINTR: offset 0x08 */
0093     u32     intr_enable;
0094
0095     /* FRINDEX: offset 0x0C */
0096     u32     frame_index;    /* current microframe number */
0097     /* CTRLDSSEGMENT: offset 0x10 */
0098     u32     segment;    /* address bits 63:32 if needed */
0099     /* PERIODICLISTBASE: offset 0x14 */
0100     u32     frame_list; /* points to periodic list */
0101     /* ASYNCLISTADDR: offset 0x18 */
0102     u32     async_next; /* address of next async queue head */
0103
0104     u32     reserved1[2];
0105
0106     /* TXFILLTUNING: offset 0x24 */
0107     u32     txfill_tuning;  /* TX FIFO Tuning register */
0108 #define TXFIFO_DEFAULT  (8<<16)     /* FIFO burst threshold 8 */
0109
0110     u32     reserved2[6];
0111
0112     /* CONFIGFLAG: offset 0x40 */
0113     u32     configured_flag;
0114 #define FLAG_CF     (1<<0)      /* true: we'll support "high speed" */
0115
0116     union {
0117         /* PORTSC: offset 0x44 */
0118         u32 port_status[HCS_N_PORTS_MAX];   /* up to N_PORTS */
0119 /* EHCI 1.1 addendum */
0120 #define PORTSC_SUSPEND_STS_ACK 0
0121 #define PORTSC_SUSPEND_STS_NYET 1
0122 #define PORTSC_SUSPEND_STS_STALL 2
0123 #define PORTSC_SUSPEND_STS_ERR 3
0124
0125 #define PORT_DEV_ADDR   (0x7f<<25)      /* device address */
0126 #define PORT_SSTS   (0x3<<23)       /* suspend status */
0127 /* 31:23 reserved */
0128 #define PORT_WKOC_E (1<<22)     /* wake on overcurrent (enable) */
0129 #define PORT_WKDISC_E   (1<<21)     /* wake on disconnect (enable) */
0130 #define PORT_WKCONN_E   (1<<20)     /* wake on connect (enable) */
0131 /* 19:16 for port testing */
0132 #define PORT_TEST(x)    (((x)&0xf)<<16) /* Port Test Control */
0133 #define PORT_TEST_PKT   PORT_TEST(0x4)  /* Port Test Control - packet test */
0134 #define PORT_TEST_FORCE PORT_TEST(0x5)  /* Port Test Control - force enable */
0135 #define PORT_LED_OFF    (0<<14)
0136 #define PORT_LED_AMBER  (1<<14)
0137 #define PORT_LED_GREEN  (2<<14)
0138 #define PORT_LED_MASK   (3<<14)
0139 #define PORT_OWNER  (1<<13)     /* true: companion hc owns this port */
0140 #define PORT_POWER  (1<<12)     /* true: has power (see PPC) */
0141 #define PORT_USB11(x) (((x)&(3<<10)) == (1<<10))    /* USB 1.1 device */
0142 #define PORT_LS_MASK    (3<<10)     /* Link status (SE0, K or J */
0143 /* 9 reserved */
0144 #define PORT_LPM    (1<<9)      /* LPM transaction */
0145 #define PORT_RESET  (1<<8)      /* reset port */
0146 #define PORT_SUSPEND    (1<<7)      /* suspend port */
0147 #define PORT_RESUME (1<<6)      /* resume it */
0148 #define PORT_OCC    (1<<5)      /* over current change */
0149 #define PORT_OC     (1<<4)      /* over current active */
0150 #define PORT_PEC    (1<<3)      /* port enable change */
0151 #define PORT_PE     (1<<2)      /* port enable */
0152 #define PORT_CSC    (1<<1)      /* connect status change */
0153 #define PORT_CONNECT    (1<<0)      /* device connected */
0154 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_OCC)
0155         struct {
0156             u32 reserved3[9];
0157             /* USBMODE: offset 0x68 */
0158             u32 usbmode;    /* USB Device mode */
0159         };
0160 #define USBMODE_SDIS    (1<<3)      /* Stream disable */
0161 #define USBMODE_BE  (1<<2)      /* BE/LE endianness select */
0162 #define USBMODE_CM_HC   (3<<0)      /* host controller mode */
0163 #define USBMODE_CM_IDLE (0<<0)      /* idle state */
0164     };
0165
0166 /* Moorestown has some non-standard registers, partially due to the fact that
0167  * its EHCI controller has both TT and LPM support. HOSTPCx are extensions to
0168  * PORTSCx
0169  */
0170     union {
0171         struct {
0172             u32 reserved4;
0173             /* HOSTPC: offset 0x84 */
0174             u32 hostpc[HCS_N_PORTS_MAX];
0175 #define HOSTPC_PHCD (1<<22)     /* Phy clock disable */
0176 #define HOSTPC_PSPD (3<<25)     /* Port speed detection */
0177         };
0178
0179         /* Broadcom-proprietary USB_EHCI_INSNREG00 @ 0x80 */
0180         u32 brcm_insnreg[4];
0181     };
0182
0183     u32     reserved5[2];
0184
0185     /* USBMODE_EX: offset 0xc8 */
0186     u32     usbmode_ex; /* USB Device mode extension */
0187 #define USBMODE_EX_VBPS (1<<5)      /* VBus Power Select On */
0188 #define USBMODE_EX_HC   (3<<0)      /* host controller mode */
0189 };
0190
0191 #endif /* __LINUX_USB_EHCI_DEF_H */