include/linux/ti-emif-sram.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * TI AM33XX EMIF Routines
0004  *
0005  * Copyright (C) 2016-2017 Texas Instruments Inc.
0006  *  Dave Gerlach
0007  */
0008 #ifndef __LINUX_TI_EMIF_H
0009 #define __LINUX_TI_EMIF_H
0010
0011 #include <linux/kbuild.h>
0012 #include <linux/types.h>
0013 #ifndef __ASSEMBLY__
0014
0015 struct emif_regs_amx3 {
0016     u32 emif_sdcfg_val;
0017     u32 emif_timing1_val;
0018     u32 emif_timing2_val;
0019     u32 emif_timing3_val;
0020     u32 emif_ref_ctrl_val;
0021     u32 emif_zqcfg_val;
0022     u32 emif_pmcr_val;
0023     u32 emif_pmcr_shdw_val;
0024     u32 emif_rd_wr_level_ramp_ctrl;
0025     u32 emif_rd_wr_exec_thresh;
0026     u32 emif_cos_config;
0027     u32 emif_priority_to_cos_mapping;
0028     u32 emif_connect_id_serv_1_map;
0029     u32 emif_connect_id_serv_2_map;
0030     u32 emif_ocp_config_val;
0031     u32 emif_lpddr2_nvm_tim;
0032     u32 emif_lpddr2_nvm_tim_shdw;
0033     u32 emif_dll_calib_ctrl_val;
0034     u32 emif_dll_calib_ctrl_val_shdw;
0035     u32 emif_ddr_phy_ctlr_1;
0036     u32 emif_ext_phy_ctrl_vals[120];
0037 };
0038
0039 struct ti_emif_pm_data {
0040     void __iomem *ti_emif_base_addr_virt;
0041     phys_addr_t ti_emif_base_addr_phys;
0042     unsigned long ti_emif_sram_config;
0043     struct emif_regs_amx3 *regs_virt;
0044     phys_addr_t regs_phys;
0045 } __packed __aligned(8);
0046
0047 struct ti_emif_pm_functions {
0048     u32 save_context;
0049     u32 restore_context;
0050     u32 run_hw_leveling;
0051     u32 enter_sr;
0052     u32 exit_sr;
0053     u32 abort_sr;
0054 } __packed __aligned(8);
0055
0056 static inline void ti_emif_asm_offsets(void)
0057 {
0058     DEFINE(EMIF_SDCFG_VAL_OFFSET,
0059            offsetof(struct emif_regs_amx3, emif_sdcfg_val));
0060     DEFINE(EMIF_TIMING1_VAL_OFFSET,
0061            offsetof(struct emif_regs_amx3, emif_timing1_val));
0062     DEFINE(EMIF_TIMING2_VAL_OFFSET,
0063            offsetof(struct emif_regs_amx3, emif_timing2_val));
0064     DEFINE(EMIF_TIMING3_VAL_OFFSET,
0065            offsetof(struct emif_regs_amx3, emif_timing3_val));
0066     DEFINE(EMIF_REF_CTRL_VAL_OFFSET,
0067            offsetof(struct emif_regs_amx3, emif_ref_ctrl_val));
0068     DEFINE(EMIF_ZQCFG_VAL_OFFSET,
0069            offsetof(struct emif_regs_amx3, emif_zqcfg_val));
0070     DEFINE(EMIF_PMCR_VAL_OFFSET,
0071            offsetof(struct emif_regs_amx3, emif_pmcr_val));
0072     DEFINE(EMIF_PMCR_SHDW_VAL_OFFSET,
0073            offsetof(struct emif_regs_amx3, emif_pmcr_shdw_val));
0074     DEFINE(EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET,
0075            offsetof(struct emif_regs_amx3, emif_rd_wr_level_ramp_ctrl));
0076     DEFINE(EMIF_RD_WR_EXEC_THRESH_OFFSET,
0077            offsetof(struct emif_regs_amx3, emif_rd_wr_exec_thresh));
0078     DEFINE(EMIF_COS_CONFIG_OFFSET,
0079            offsetof(struct emif_regs_amx3, emif_cos_config));
0080     DEFINE(EMIF_PRIORITY_TO_COS_MAPPING_OFFSET,
0081            offsetof(struct emif_regs_amx3, emif_priority_to_cos_mapping));
0082     DEFINE(EMIF_CONNECT_ID_SERV_1_MAP_OFFSET,
0083            offsetof(struct emif_regs_amx3, emif_connect_id_serv_1_map));
0084     DEFINE(EMIF_CONNECT_ID_SERV_2_MAP_OFFSET,
0085            offsetof(struct emif_regs_amx3, emif_connect_id_serv_2_map));
0086     DEFINE(EMIF_OCP_CONFIG_VAL_OFFSET,
0087            offsetof(struct emif_regs_amx3, emif_ocp_config_val));
0088     DEFINE(EMIF_LPDDR2_NVM_TIM_OFFSET,
0089            offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim));
0090     DEFINE(EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET,
0091            offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim_shdw));
0092     DEFINE(EMIF_DLL_CALIB_CTRL_VAL_OFFSET,
0093            offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val));
0094     DEFINE(EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET,
0095            offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val_shdw));
0096     DEFINE(EMIF_DDR_PHY_CTLR_1_OFFSET,
0097            offsetof(struct emif_regs_amx3, emif_ddr_phy_ctlr_1));
0098     DEFINE(EMIF_EXT_PHY_CTRL_VALS_OFFSET,
0099            offsetof(struct emif_regs_amx3, emif_ext_phy_ctrl_vals));
0100     DEFINE(EMIF_REGS_AMX3_SIZE, sizeof(struct emif_regs_amx3));
0101
0102     BLANK();
0103
0104     DEFINE(EMIF_PM_BASE_ADDR_VIRT_OFFSET,
0105            offsetof(struct ti_emif_pm_data, ti_emif_base_addr_virt));
0106     DEFINE(EMIF_PM_BASE_ADDR_PHYS_OFFSET,
0107            offsetof(struct ti_emif_pm_data, ti_emif_base_addr_phys));
0108     DEFINE(EMIF_PM_CONFIG_OFFSET,
0109            offsetof(struct ti_emif_pm_data, ti_emif_sram_config));
0110     DEFINE(EMIF_PM_REGS_VIRT_OFFSET,
0111            offsetof(struct ti_emif_pm_data, regs_virt));
0112     DEFINE(EMIF_PM_REGS_PHYS_OFFSET,
0113            offsetof(struct ti_emif_pm_data, regs_phys));
0114     DEFINE(EMIF_PM_DATA_SIZE, sizeof(struct ti_emif_pm_data));
0115
0116     BLANK();
0117
0118     DEFINE(EMIF_PM_SAVE_CONTEXT_OFFSET,
0119            offsetof(struct ti_emif_pm_functions, save_context));
0120     DEFINE(EMIF_PM_RESTORE_CONTEXT_OFFSET,
0121            offsetof(struct ti_emif_pm_functions, restore_context));
0122     DEFINE(EMIF_PM_RUN_HW_LEVELING,
0123            offsetof(struct ti_emif_pm_functions, run_hw_leveling));
0124     DEFINE(EMIF_PM_ENTER_SR_OFFSET,
0125            offsetof(struct ti_emif_pm_functions, enter_sr));
0126     DEFINE(EMIF_PM_EXIT_SR_OFFSET,
0127            offsetof(struct ti_emif_pm_functions, exit_sr));
0128     DEFINE(EMIF_PM_ABORT_SR_OFFSET,
0129            offsetof(struct ti_emif_pm_functions, abort_sr));
0130     DEFINE(EMIF_PM_FUNCTIONS_SIZE, sizeof(struct ti_emif_pm_functions));
0131 }
0132
0133 struct gen_pool;
0134
0135 int ti_emif_copy_pm_function_table(struct gen_pool *sram_pool, void *dst);
0136 int ti_emif_get_mem_type(void);
0137
0138 #endif
0139 #endif /* __LINUX_TI_EMIF_H */