include/linux/sxgbe_platform.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * 10G controller driver for Samsung Exynos SoCs
0004  *
0005  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
0006  *      http://www.samsung.com
0007  *
0008  * Author: Siva Reddy Kallam <siva.kallam@samsung.com>
0009  */
0010 #ifndef __SXGBE_PLATFORM_H__
0011 #define __SXGBE_PLATFORM_H__
0012
0013 #include <linux/phy.h>
0014
0015 /* MDC Clock Selection define*/
0016 #define SXGBE_CSR_100_150M  0x0 /* MDC = clk_scr_i/62 */
0017 #define SXGBE_CSR_150_250M  0x1 /* MDC = clk_scr_i/102 */
0018 #define SXGBE_CSR_250_300M  0x2 /* MDC = clk_scr_i/122 */
0019 #define SXGBE_CSR_300_350M  0x3 /* MDC = clk_scr_i/142 */
0020 #define SXGBE_CSR_350_400M  0x4 /* MDC = clk_scr_i/162 */
0021 #define SXGBE_CSR_400_500M  0x5 /* MDC = clk_scr_i/202 */
0022
0023 /* Platfrom data for platform device structure's
0024  * platform_data field
0025  */
0026 struct sxgbe_mdio_bus_data {
0027     unsigned int phy_mask;
0028     int *irqs;
0029     int probed_phy_irq;
0030 };
0031
0032 struct sxgbe_dma_cfg {
0033     int pbl;
0034     int fixed_burst;
0035     int burst_map;
0036     int adv_addr_mode;
0037 };
0038
0039 struct sxgbe_plat_data {
0040     char *phy_bus_name;
0041     int bus_id;
0042     int phy_addr;
0043     phy_interface_t interface;
0044     struct sxgbe_mdio_bus_data *mdio_bus_data;
0045     struct sxgbe_dma_cfg *dma_cfg;
0046     int clk_csr;
0047     int pmt;
0048     int force_sf_dma_mode;
0049     int force_thresh_dma_mode;
0050     int riwt_off;
0051 };
0052
0053 #endif /* __SXGBE_PLATFORM_H__ */