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0007 #ifndef _SWITCHTEC_H
0008 #define _SWITCHTEC_H
0009
0010 #include <linux/pci.h>
0011 #include <linux/cdev.h>
0012
0013 #define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024
0014 #define SWITCHTEC_MAX_PFF_CSR 255
0015
0016 #define SWITCHTEC_EVENT_OCCURRED BIT(0)
0017 #define SWITCHTEC_EVENT_CLEAR BIT(0)
0018 #define SWITCHTEC_EVENT_EN_LOG BIT(1)
0019 #define SWITCHTEC_EVENT_EN_CLI BIT(2)
0020 #define SWITCHTEC_EVENT_EN_IRQ BIT(3)
0021 #define SWITCHTEC_EVENT_FATAL BIT(4)
0022 #define SWITCHTEC_EVENT_NOT_SUPP BIT(31)
0023
0024 #define SWITCHTEC_DMA_MRPC_EN BIT(0)
0025
0026 #define MRPC_GAS_READ 0x29
0027 #define MRPC_GAS_WRITE 0x87
0028 #define MRPC_CMD_ID(x) ((x) & 0xffff)
0029
0030 enum {
0031 SWITCHTEC_GAS_MRPC_OFFSET = 0x0000,
0032 SWITCHTEC_GAS_TOP_CFG_OFFSET = 0x1000,
0033 SWITCHTEC_GAS_SW_EVENT_OFFSET = 0x1800,
0034 SWITCHTEC_GAS_SYS_INFO_OFFSET = 0x2000,
0035 SWITCHTEC_GAS_FLASH_INFO_OFFSET = 0x2200,
0036 SWITCHTEC_GAS_PART_CFG_OFFSET = 0x4000,
0037 SWITCHTEC_GAS_NTB_OFFSET = 0x10000,
0038 SWITCHTEC_GAS_PFF_CSR_OFFSET = 0x134000,
0039 };
0040
0041 enum switchtec_gen {
0042 SWITCHTEC_GEN3,
0043 SWITCHTEC_GEN4,
0044 };
0045
0046 struct mrpc_regs {
0047 u8 input_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
0048 u8 output_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
0049 u32 cmd;
0050 u32 status;
0051 u32 ret_value;
0052 u32 dma_en;
0053 u64 dma_addr;
0054 u32 dma_vector;
0055 u32 dma_ver;
0056 } __packed;
0057
0058 enum mrpc_status {
0059 SWITCHTEC_MRPC_STATUS_INPROGRESS = 1,
0060 SWITCHTEC_MRPC_STATUS_DONE = 2,
0061 SWITCHTEC_MRPC_STATUS_ERROR = 0xFF,
0062 SWITCHTEC_MRPC_STATUS_INTERRUPTED = 0x100,
0063 };
0064
0065 struct sw_event_regs {
0066 u64 event_report_ctrl;
0067 u64 reserved1;
0068 u64 part_event_bitmap;
0069 u64 reserved2;
0070 u32 global_summary;
0071 u32 reserved3[3];
0072 u32 stack_error_event_hdr;
0073 u32 stack_error_event_data;
0074 u32 reserved4[4];
0075 u32 ppu_error_event_hdr;
0076 u32 ppu_error_event_data;
0077 u32 reserved5[4];
0078 u32 isp_error_event_hdr;
0079 u32 isp_error_event_data;
0080 u32 reserved6[4];
0081 u32 sys_reset_event_hdr;
0082 u32 reserved7[5];
0083 u32 fw_exception_hdr;
0084 u32 reserved8[5];
0085 u32 fw_nmi_hdr;
0086 u32 reserved9[5];
0087 u32 fw_non_fatal_hdr;
0088 u32 reserved10[5];
0089 u32 fw_fatal_hdr;
0090 u32 reserved11[5];
0091 u32 twi_mrpc_comp_hdr;
0092 u32 twi_mrpc_comp_data;
0093 u32 reserved12[4];
0094 u32 twi_mrpc_comp_async_hdr;
0095 u32 twi_mrpc_comp_async_data;
0096 u32 reserved13[4];
0097 u32 cli_mrpc_comp_hdr;
0098 u32 cli_mrpc_comp_data;
0099 u32 reserved14[4];
0100 u32 cli_mrpc_comp_async_hdr;
0101 u32 cli_mrpc_comp_async_data;
0102 u32 reserved15[4];
0103 u32 gpio_interrupt_hdr;
0104 u32 gpio_interrupt_data;
0105 u32 reserved16[4];
0106 u32 gfms_event_hdr;
0107 u32 gfms_event_data;
0108 u32 reserved17[4];
0109 } __packed;
0110
0111 enum {
0112 SWITCHTEC_GEN3_CFG0_RUNNING = 0x04,
0113 SWITCHTEC_GEN3_CFG1_RUNNING = 0x05,
0114 SWITCHTEC_GEN3_IMG0_RUNNING = 0x03,
0115 SWITCHTEC_GEN3_IMG1_RUNNING = 0x07,
0116 };
0117
0118 enum {
0119 SWITCHTEC_GEN4_MAP0_RUNNING = 0x00,
0120 SWITCHTEC_GEN4_MAP1_RUNNING = 0x01,
0121 SWITCHTEC_GEN4_KEY0_RUNNING = 0x02,
0122 SWITCHTEC_GEN4_KEY1_RUNNING = 0x03,
0123 SWITCHTEC_GEN4_BL2_0_RUNNING = 0x04,
0124 SWITCHTEC_GEN4_BL2_1_RUNNING = 0x05,
0125 SWITCHTEC_GEN4_CFG0_RUNNING = 0x06,
0126 SWITCHTEC_GEN4_CFG1_RUNNING = 0x07,
0127 SWITCHTEC_GEN4_IMG0_RUNNING = 0x08,
0128 SWITCHTEC_GEN4_IMG1_RUNNING = 0x09,
0129 };
0130
0131 enum {
0132 SWITCHTEC_GEN4_KEY0_ACTIVE = 0,
0133 SWITCHTEC_GEN4_KEY1_ACTIVE = 1,
0134 SWITCHTEC_GEN4_BL2_0_ACTIVE = 0,
0135 SWITCHTEC_GEN4_BL2_1_ACTIVE = 1,
0136 SWITCHTEC_GEN4_CFG0_ACTIVE = 0,
0137 SWITCHTEC_GEN4_CFG1_ACTIVE = 1,
0138 SWITCHTEC_GEN4_IMG0_ACTIVE = 0,
0139 SWITCHTEC_GEN4_IMG1_ACTIVE = 1,
0140 };
0141
0142 struct sys_info_regs_gen3 {
0143 u32 reserved1;
0144 u32 vendor_table_revision;
0145 u32 table_format_version;
0146 u32 partition_id;
0147 u32 cfg_file_fmt_version;
0148 u16 cfg_running;
0149 u16 img_running;
0150 u32 reserved2[57];
0151 char vendor_id[8];
0152 char product_id[16];
0153 char product_revision[4];
0154 char component_vendor[8];
0155 u16 component_id;
0156 u8 component_revision;
0157 } __packed;
0158
0159 struct sys_info_regs_gen4 {
0160 u16 gas_layout_ver;
0161 u8 evlist_ver;
0162 u8 reserved1;
0163 u16 mgmt_cmd_set_ver;
0164 u16 fabric_cmd_set_ver;
0165 u32 reserved2[2];
0166 u8 mrpc_uart_ver;
0167 u8 mrpc_twi_ver;
0168 u8 mrpc_eth_ver;
0169 u8 mrpc_inband_ver;
0170 u32 reserved3[7];
0171 u32 fw_update_tmo;
0172 u32 xml_version_cfg;
0173 u32 xml_version_img;
0174 u32 partition_id;
0175 u16 bl2_running;
0176 u16 cfg_running;
0177 u16 img_running;
0178 u16 key_running;
0179 u32 reserved4[43];
0180 u32 vendor_seeprom_twi;
0181 u32 vendor_table_revision;
0182 u32 vendor_specific_info[2];
0183 u16 p2p_vendor_id;
0184 u16 p2p_device_id;
0185 u8 p2p_revision_id;
0186 u8 reserved5[3];
0187 u32 p2p_class_id;
0188 u16 subsystem_vendor_id;
0189 u16 subsystem_id;
0190 u32 p2p_serial_number[2];
0191 u8 mac_addr[6];
0192 u8 reserved6[2];
0193 u32 reserved7[3];
0194 char vendor_id[8];
0195 char product_id[24];
0196 char product_revision[2];
0197 u16 reserved8;
0198 } __packed;
0199
0200 struct sys_info_regs {
0201 u32 device_id;
0202 u32 device_version;
0203 u32 firmware_version;
0204 union {
0205 struct sys_info_regs_gen3 gen3;
0206 struct sys_info_regs_gen4 gen4;
0207 };
0208 } __packed;
0209
0210 struct partition_info {
0211 u32 address;
0212 u32 length;
0213 };
0214
0215 struct flash_info_regs_gen3 {
0216 u32 flash_part_map_upd_idx;
0217
0218 struct active_partition_info_gen3 {
0219 u32 address;
0220 u32 build_version;
0221 u32 build_string;
0222 } active_img;
0223
0224 struct active_partition_info_gen3 active_cfg;
0225 struct active_partition_info_gen3 inactive_img;
0226 struct active_partition_info_gen3 inactive_cfg;
0227
0228 u32 flash_length;
0229
0230 struct partition_info cfg0;
0231 struct partition_info cfg1;
0232 struct partition_info img0;
0233 struct partition_info img1;
0234 struct partition_info nvlog;
0235 struct partition_info vendor[8];
0236 };
0237
0238 struct flash_info_regs_gen4 {
0239 u32 flash_address;
0240 u32 flash_length;
0241
0242 struct active_partition_info_gen4 {
0243 unsigned char bl2;
0244 unsigned char cfg;
0245 unsigned char img;
0246 unsigned char key;
0247 } active_flag;
0248
0249 u32 reserved[3];
0250
0251 struct partition_info map0;
0252 struct partition_info map1;
0253 struct partition_info key0;
0254 struct partition_info key1;
0255 struct partition_info bl2_0;
0256 struct partition_info bl2_1;
0257 struct partition_info cfg0;
0258 struct partition_info cfg1;
0259 struct partition_info img0;
0260 struct partition_info img1;
0261 struct partition_info nvlog;
0262 struct partition_info vendor[8];
0263 };
0264
0265 struct flash_info_regs {
0266 union {
0267 struct flash_info_regs_gen3 gen3;
0268 struct flash_info_regs_gen4 gen4;
0269 };
0270 };
0271
0272 enum {
0273 SWITCHTEC_NTB_REG_INFO_OFFSET = 0x0000,
0274 SWITCHTEC_NTB_REG_CTRL_OFFSET = 0x4000,
0275 SWITCHTEC_NTB_REG_DBMSG_OFFSET = 0x64000,
0276 };
0277
0278 struct ntb_info_regs {
0279 u8 partition_count;
0280 u8 partition_id;
0281 u16 reserved1;
0282 u64 ep_map;
0283 u16 requester_id;
0284 u16 reserved2;
0285 u32 reserved3[4];
0286 struct nt_partition_info {
0287 u32 xlink_enabled;
0288 u32 target_part_low;
0289 u32 target_part_high;
0290 u32 reserved;
0291 } ntp_info[48];
0292 } __packed;
0293
0294 struct part_cfg_regs {
0295 u32 status;
0296 u32 state;
0297 u32 port_cnt;
0298 u32 usp_port_mode;
0299 u32 usp_pff_inst_id;
0300 u32 vep_pff_inst_id;
0301 u32 dsp_pff_inst_id[47];
0302 u32 reserved1[11];
0303 u16 vep_vector_number;
0304 u16 usp_vector_number;
0305 u32 port_event_bitmap;
0306 u32 reserved2[3];
0307 u32 part_event_summary;
0308 u32 reserved3[3];
0309 u32 part_reset_hdr;
0310 u32 part_reset_data[5];
0311 u32 mrpc_comp_hdr;
0312 u32 mrpc_comp_data[5];
0313 u32 mrpc_comp_async_hdr;
0314 u32 mrpc_comp_async_data[5];
0315 u32 dyn_binding_hdr;
0316 u32 dyn_binding_data[5];
0317 u32 intercomm_notify_hdr;
0318 u32 intercomm_notify_data[5];
0319 u32 reserved4[153];
0320 } __packed;
0321
0322 enum {
0323 NTB_CTRL_PART_OP_LOCK = 0x1,
0324 NTB_CTRL_PART_OP_CFG = 0x2,
0325 NTB_CTRL_PART_OP_RESET = 0x3,
0326
0327 NTB_CTRL_PART_STATUS_NORMAL = 0x1,
0328 NTB_CTRL_PART_STATUS_LOCKED = 0x2,
0329 NTB_CTRL_PART_STATUS_LOCKING = 0x3,
0330 NTB_CTRL_PART_STATUS_CONFIGURING = 0x4,
0331 NTB_CTRL_PART_STATUS_RESETTING = 0x5,
0332
0333 NTB_CTRL_BAR_VALID = 1 << 0,
0334 NTB_CTRL_BAR_DIR_WIN_EN = 1 << 4,
0335 NTB_CTRL_BAR_LUT_WIN_EN = 1 << 5,
0336
0337 NTB_CTRL_REQ_ID_EN = 1 << 0,
0338
0339 NTB_CTRL_LUT_EN = 1 << 0,
0340 };
0341
0342 struct ntb_ctrl_regs {
0343 u32 partition_status;
0344 u32 partition_op;
0345 u32 partition_ctrl;
0346 u32 bar_setup;
0347 u32 bar_error;
0348 u16 lut_table_entries;
0349 u16 lut_table_offset;
0350 u32 lut_error;
0351 u16 req_id_table_size;
0352 u16 req_id_table_offset;
0353 u32 req_id_error;
0354 u32 reserved1[7];
0355 struct {
0356 u32 ctl;
0357 u32 win_size;
0358 u64 xlate_addr;
0359 } bar_entry[6];
0360 struct {
0361 u32 win_size;
0362 u32 reserved[3];
0363 } bar_ext_entry[6];
0364 u32 reserved2[192];
0365 u32 req_id_table[512];
0366 u32 reserved3[256];
0367 u64 lut_entry[512];
0368 } __packed;
0369
0370 #define NTB_DBMSG_IMSG_STATUS BIT_ULL(32)
0371 #define NTB_DBMSG_IMSG_MASK BIT_ULL(40)
0372
0373 struct ntb_dbmsg_regs {
0374 u32 reserved1[1024];
0375 u64 odb;
0376 u64 odb_mask;
0377 u64 idb;
0378 u64 idb_mask;
0379 u8 idb_vec_map[64];
0380 u32 msg_map;
0381 u32 reserved2;
0382 struct {
0383 u32 msg;
0384 u32 status;
0385 } omsg[4];
0386
0387 struct {
0388 u32 msg;
0389 u8 status;
0390 u8 mask;
0391 u8 src;
0392 u8 reserved;
0393 } imsg[4];
0394
0395 u8 reserved3[3928];
0396 u8 msix_table[1024];
0397 u8 reserved4[3072];
0398 u8 pba[24];
0399 u8 reserved5[4072];
0400 } __packed;
0401
0402 enum {
0403 SWITCHTEC_PART_CFG_EVENT_RESET = 1 << 0,
0404 SWITCHTEC_PART_CFG_EVENT_MRPC_CMP = 1 << 1,
0405 SWITCHTEC_PART_CFG_EVENT_MRPC_ASYNC_CMP = 1 << 2,
0406 SWITCHTEC_PART_CFG_EVENT_DYN_PART_CMP = 1 << 3,
0407 };
0408
0409 struct pff_csr_regs {
0410 u16 vendor_id;
0411 u16 device_id;
0412 u16 pcicmd;
0413 u16 pcists;
0414 u32 pci_class;
0415 u32 pci_opts;
0416 union {
0417 u32 pci_bar[6];
0418 u64 pci_bar64[3];
0419 };
0420 u32 pci_cardbus;
0421 u32 pci_subsystem_id;
0422 u32 pci_expansion_rom;
0423 u32 pci_cap_ptr;
0424 u32 reserved1;
0425 u32 pci_irq;
0426 u32 pci_cap_region[48];
0427 u32 pcie_cap_region[448];
0428 u32 indirect_gas_window[128];
0429 u32 indirect_gas_window_off;
0430 u32 reserved[127];
0431 u32 pff_event_summary;
0432 u32 reserved2[3];
0433 u32 aer_in_p2p_hdr;
0434 u32 aer_in_p2p_data[5];
0435 u32 aer_in_vep_hdr;
0436 u32 aer_in_vep_data[5];
0437 u32 dpc_hdr;
0438 u32 dpc_data[5];
0439 u32 cts_hdr;
0440 u32 cts_data[5];
0441 u32 uec_hdr;
0442 u32 uec_data[5];
0443 u32 hotplug_hdr;
0444 u32 hotplug_data[5];
0445 u32 ier_hdr;
0446 u32 ier_data[5];
0447 u32 threshold_hdr;
0448 u32 threshold_data[5];
0449 u32 power_mgmt_hdr;
0450 u32 power_mgmt_data[5];
0451 u32 tlp_throttling_hdr;
0452 u32 tlp_throttling_data[5];
0453 u32 force_speed_hdr;
0454 u32 force_speed_data[5];
0455 u32 credit_timeout_hdr;
0456 u32 credit_timeout_data[5];
0457 u32 link_state_hdr;
0458 u32 link_state_data[5];
0459 u32 reserved4[174];
0460 } __packed;
0461
0462 struct switchtec_ntb;
0463
0464 struct dma_mrpc_output {
0465 u32 status;
0466 u32 cmd_id;
0467 u32 rtn_code;
0468 u32 output_size;
0469 u8 data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
0470 };
0471
0472 struct switchtec_dev {
0473 struct pci_dev *pdev;
0474 struct device dev;
0475 struct cdev cdev;
0476
0477 enum switchtec_gen gen;
0478
0479 int partition;
0480 int partition_count;
0481 int pff_csr_count;
0482 char pff_local[SWITCHTEC_MAX_PFF_CSR];
0483
0484 void __iomem *mmio;
0485 struct mrpc_regs __iomem *mmio_mrpc;
0486 struct sw_event_regs __iomem *mmio_sw_event;
0487 struct sys_info_regs __iomem *mmio_sys_info;
0488 struct flash_info_regs __iomem *mmio_flash_info;
0489 struct ntb_info_regs __iomem *mmio_ntb;
0490 struct part_cfg_regs __iomem *mmio_part_cfg;
0491 struct part_cfg_regs __iomem *mmio_part_cfg_all;
0492 struct pff_csr_regs __iomem *mmio_pff_csr;
0493
0494
0495
0496
0497
0498 struct mutex mrpc_mutex;
0499 struct list_head mrpc_queue;
0500 int mrpc_busy;
0501 struct work_struct mrpc_work;
0502 struct delayed_work mrpc_timeout;
0503 bool alive;
0504
0505 wait_queue_head_t event_wq;
0506 atomic_t event_cnt;
0507
0508 struct work_struct link_event_work;
0509 void (*link_notifier)(struct switchtec_dev *stdev);
0510 u8 link_event_count[SWITCHTEC_MAX_PFF_CSR];
0511
0512 struct switchtec_ntb *sndev;
0513
0514 struct dma_mrpc_output *dma_mrpc;
0515 dma_addr_t dma_mrpc_dma_addr;
0516 };
0517
0518 static inline struct switchtec_dev *to_stdev(struct device *dev)
0519 {
0520 return container_of(dev, struct switchtec_dev, dev);
0521 }
0522
0523 extern struct class *switchtec_class;
0524
0525 #endif
