include/linux/sungem_phy.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __SUNGEM_PHY_H__
0003 #define __SUNGEM_PHY_H__
0004
0005 #include <linux/types.h>
0006
0007 struct mii_phy;
0008
0009 /* Operations supported by any kind of PHY */
0010 struct mii_phy_ops
0011 {
0012     int     (*init)(struct mii_phy *phy);
0013     int     (*suspend)(struct mii_phy *phy);
0014     int     (*setup_aneg)(struct mii_phy *phy, u32 advertise);
0015     int     (*setup_forced)(struct mii_phy *phy, int speed, int fd);
0016     int     (*poll_link)(struct mii_phy *phy);
0017     int     (*read_link)(struct mii_phy *phy);
0018     int     (*enable_fiber)(struct mii_phy *phy, int autoneg);
0019 };
0020
0021 /* Structure used to statically define an mii/gii based PHY */
0022 struct mii_phy_def
0023 {
0024     u32             phy_id;     /* Concatenated ID1 << 16 | ID2 */
0025     u32             phy_id_mask;    /* Significant bits */
0026     u32             features;   /* Ethtool SUPPORTED_* defines */
0027     int             magic_aneg; /* Autoneg does all speed test for us */
0028     const char*         name;
0029     const struct mii_phy_ops*   ops;
0030 };
0031
0032 enum {
0033     BCM54XX_COPPER,
0034     BCM54XX_FIBER,
0035     BCM54XX_GBIC,
0036     BCM54XX_SGMII,
0037     BCM54XX_UNKNOWN,
0038 };
0039
0040 /* An instance of a PHY, partially borrowed from mii_if_info */
0041 struct mii_phy
0042 {
0043     struct mii_phy_def* def;
0044     u32         advertising;
0045     int         mii_id;
0046
0047     /* 1: autoneg enabled, 0: disabled */
0048     int         autoneg;
0049
0050     /* forced speed & duplex (no autoneg)
0051      * partner speed & duplex & pause (autoneg)
0052      */
0053     int         speed;
0054     int         duplex;
0055     int         pause;
0056
0057     /* Provided by host chip */
0058     struct net_device   *dev;
0059     int (*mdio_read) (struct net_device *dev, int mii_id, int reg);
0060     void (*mdio_write) (struct net_device *dev, int mii_id, int reg, int val);
0061     void            *platform_data;
0062 };
0063
0064 /* Pass in a struct mii_phy with dev, mdio_read and mdio_write
0065  * filled, the remaining fields will be filled on return
0066  */
0067 extern int sungem_phy_probe(struct mii_phy *phy, int mii_id);
0068
0069
0070 /* MII definitions missing from mii.h */
0071
0072 #define BMCR_SPD2   0x0040      /* Gigabit enable (bcm54xx) */
0073 #define LPA_PAUSE   0x0400
0074
0075 /* More PHY registers (model specific) */
0076
0077 /* MII BCM5201 MULTIPHY interrupt register */
0078 #define MII_BCM5201_INTERRUPT           0x1A
0079 #define MII_BCM5201_INTERRUPT_INTENABLE     0x4000
0080
0081 #define MII_BCM5201_AUXMODE2            0x1B
0082 #define MII_BCM5201_AUXMODE2_LOWPOWER       0x0008
0083
0084 #define MII_BCM5201_MULTIPHY                    0x1E
0085
0086 /* MII BCM5201 MULTIPHY register bits */
0087 #define MII_BCM5201_MULTIPHY_SERIALMODE         0x0002
0088 #define MII_BCM5201_MULTIPHY_SUPERISOLATE       0x0008
0089
0090 /* MII BCM5221 Additional registers */
0091 #define MII_BCM5221_TEST            0x1f
0092 #define MII_BCM5221_TEST_ENABLE_SHADOWS     0x0080
0093 #define MII_BCM5221_SHDOW_AUX_STAT2     0x1b
0094 #define MII_BCM5221_SHDOW_AUX_STAT2_APD     0x0020
0095 #define MII_BCM5221_SHDOW_AUX_MODE4     0x1a
0096 #define MII_BCM5221_SHDOW_AUX_MODE4_IDDQMODE    0x0001
0097 #define MII_BCM5221_SHDOW_AUX_MODE4_CLKLOPWR    0x0004
0098
0099 /* MII BCM5241 Additional registers */
0100 #define MII_BCM5241_SHDOW_AUX_MODE4_STANDBYPWR  0x0008
0101
0102 /* MII BCM5400 1000-BASET Control register */
0103 #define MII_BCM5400_GB_CONTROL          0x09
0104 #define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP    0x0200
0105
0106 /* MII BCM5400 AUXCONTROL register */
0107 #define MII_BCM5400_AUXCONTROL                  0x18
0108 #define MII_BCM5400_AUXCONTROL_PWR10BASET       0x0004
0109
0110 /* MII BCM5400 AUXSTATUS register */
0111 #define MII_BCM5400_AUXSTATUS                   0x19
0112 #define MII_BCM5400_AUXSTATUS_LINKMODE_MASK     0x0700
0113 #define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT    8
0114
0115 /* 1000BT control (Marvell & BCM54xx at least) */
0116 #define MII_1000BASETCONTROL            0x09
0117 #define MII_1000BASETCONTROL_FULLDUPLEXCAP  0x0200
0118 #define MII_1000BASETCONTROL_HALFDUPLEXCAP  0x0100
0119
0120 /* Marvell 88E1011 PHY control */
0121 #define MII_M1011_PHY_SPEC_CONTROL      0x10
0122 #define MII_M1011_PHY_SPEC_CONTROL_MANUAL_MDIX  0x20
0123 #define MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX    0x40
0124
0125 /* Marvell 88E1011 PHY status */
0126 #define MII_M1011_PHY_SPEC_STATUS       0x11
0127 #define MII_M1011_PHY_SPEC_STATUS_1000      0x8000
0128 #define MII_M1011_PHY_SPEC_STATUS_100       0x4000
0129 #define MII_M1011_PHY_SPEC_STATUS_SPD_MASK  0xc000
0130 #define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX    0x2000
0131 #define MII_M1011_PHY_SPEC_STATUS_RESOLVED  0x0800
0132 #define MII_M1011_PHY_SPEC_STATUS_TX_PAUSE  0x0008
0133 #define MII_M1011_PHY_SPEC_STATUS_RX_PAUSE  0x0004
0134
0135 #endif /* __SUNGEM_PHY_H__ */