include/linux/stmmac.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*******************************************************************************
0003
0004   Header file for stmmac platform data
0005
0006   Copyright (C) 2009  STMicroelectronics Ltd
0007
0008
0009   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
0010 *******************************************************************************/
0011
0012 #ifndef __STMMAC_PLATFORM_DATA
0013 #define __STMMAC_PLATFORM_DATA
0014
0015 #include <linux/platform_device.h>
0016 #include <linux/phy.h>
0017
0018 #define MTL_MAX_RX_QUEUES   8
0019 #define MTL_MAX_TX_QUEUES   8
0020 #define STMMAC_CH_MAX       8
0021
0022 #define STMMAC_RX_COE_NONE  0
0023 #define STMMAC_RX_COE_TYPE1 1
0024 #define STMMAC_RX_COE_TYPE2 2
0025
0026 /* Define the macros for CSR clock range parameters to be passed by
0027  * platform code.
0028  * This could also be configured at run time using CPU freq framework. */
0029
0030 /* MDC Clock Selection define*/
0031 #define STMMAC_CSR_60_100M  0x0 /* MDC = clk_scr_i/42 */
0032 #define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */
0033 #define STMMAC_CSR_20_35M   0x2 /* MDC = clk_scr_i/16 */
0034 #define STMMAC_CSR_35_60M   0x3 /* MDC = clk_scr_i/26 */
0035 #define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */
0036 #define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */
0037
0038 /* MTL algorithms identifiers */
0039 #define MTL_TX_ALGORITHM_WRR    0x0
0040 #define MTL_TX_ALGORITHM_WFQ    0x1
0041 #define MTL_TX_ALGORITHM_DWRR   0x2
0042 #define MTL_TX_ALGORITHM_SP 0x3
0043 #define MTL_RX_ALGORITHM_SP 0x4
0044 #define MTL_RX_ALGORITHM_WSP    0x5
0045
0046 /* RX/TX Queue Mode */
0047 #define MTL_QUEUE_AVB       0x0
0048 #define MTL_QUEUE_DCB       0x1
0049
0050 /* The MDC clock could be set higher than the IEEE 802.3
0051  * specified frequency limit 0f 2.5 MHz, by programming a clock divider
0052  * of value different than the above defined values. The resultant MDIO
0053  * clock frequency of 12.5 MHz is applicable for the interfacing chips
0054  * supporting higher MDC clocks.
0055  * The MDC clock selection macros need to be defined for MDC clock rate
0056  * of 12.5 MHz, corresponding to the following selection.
0057  */
0058 #define STMMAC_CSR_I_4      0x8 /* clk_csr_i/4 */
0059 #define STMMAC_CSR_I_6      0x9 /* clk_csr_i/6 */
0060 #define STMMAC_CSR_I_8      0xA /* clk_csr_i/8 */
0061 #define STMMAC_CSR_I_10     0xB /* clk_csr_i/10 */
0062 #define STMMAC_CSR_I_12     0xC /* clk_csr_i/12 */
0063 #define STMMAC_CSR_I_14     0xD /* clk_csr_i/14 */
0064 #define STMMAC_CSR_I_16     0xE /* clk_csr_i/16 */
0065 #define STMMAC_CSR_I_18     0xF /* clk_csr_i/18 */
0066
0067 /* AXI DMA Burst length supported */
0068 #define DMA_AXI_BLEN_4      (1 << 1)
0069 #define DMA_AXI_BLEN_8      (1 << 2)
0070 #define DMA_AXI_BLEN_16     (1 << 3)
0071 #define DMA_AXI_BLEN_32     (1 << 4)
0072 #define DMA_AXI_BLEN_64     (1 << 5)
0073 #define DMA_AXI_BLEN_128    (1 << 6)
0074 #define DMA_AXI_BLEN_256    (1 << 7)
0075 #define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
0076             | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
0077             | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)
0078
0079 /* Platfrom data for platform device structure's platform_data field */
0080
0081 struct stmmac_mdio_bus_data {
0082     unsigned int phy_mask;
0083     unsigned int has_xpcs;
0084     unsigned int xpcs_an_inband;
0085     int *irqs;
0086     int probed_phy_irq;
0087     bool needs_reset;
0088 };
0089
0090 struct stmmac_dma_cfg {
0091     int pbl;
0092     int txpbl;
0093     int rxpbl;
0094     bool pblx8;
0095     int fixed_burst;
0096     int mixed_burst;
0097     bool aal;
0098     bool eame;
0099     bool multi_msi_en;
0100     bool dche;
0101 };
0102
0103 #define AXI_BLEN    7
0104 struct stmmac_axi {
0105     bool axi_lpi_en;
0106     bool axi_xit_frm;
0107     u32 axi_wr_osr_lmt;
0108     u32 axi_rd_osr_lmt;
0109     bool axi_kbbe;
0110     u32 axi_blen[AXI_BLEN];
0111     bool axi_fb;
0112     bool axi_mb;
0113     bool axi_rb;
0114 };
0115
0116 #define EST_GCL     1024
0117 struct stmmac_est {
0118     struct mutex lock;
0119     int enable;
0120     u32 btr_reserve[2];
0121     u32 btr_offset[2];
0122     u32 btr[2];
0123     u32 ctr[2];
0124     u32 ter;
0125     u32 gcl_unaligned[EST_GCL];
0126     u32 gcl[EST_GCL];
0127     u32 gcl_size;
0128 };
0129
0130 struct stmmac_rxq_cfg {
0131     u8 mode_to_use;
0132     u32 chan;
0133     u8 pkt_route;
0134     bool use_prio;
0135     u32 prio;
0136 };
0137
0138 struct stmmac_txq_cfg {
0139     u32 weight;
0140     u8 mode_to_use;
0141     /* Credit Base Shaper parameters */
0142     u32 send_slope;
0143     u32 idle_slope;
0144     u32 high_credit;
0145     u32 low_credit;
0146     bool use_prio;
0147     u32 prio;
0148     int tbs_en;
0149 };
0150
0151 /* FPE link state */
0152 enum stmmac_fpe_state {
0153     FPE_STATE_OFF = 0,
0154     FPE_STATE_CAPABLE = 1,
0155     FPE_STATE_ENTERING_ON = 2,
0156     FPE_STATE_ON = 3,
0157 };
0158
0159 /* FPE link-partner hand-shaking mPacket type */
0160 enum stmmac_mpacket_type {
0161     MPACKET_VERIFY = 0,
0162     MPACKET_RESPONSE = 1,
0163 };
0164
0165 enum stmmac_fpe_task_state_t {
0166     __FPE_REMOVING,
0167     __FPE_TASK_SCHED,
0168 };
0169
0170 struct stmmac_fpe_cfg {
0171     bool enable;                /* FPE enable */
0172     bool hs_enable;             /* FPE handshake enable */
0173     enum stmmac_fpe_state lp_fpe_state; /* Link Partner FPE state */
0174     enum stmmac_fpe_state lo_fpe_state; /* Local station FPE state */
0175 };
0176
0177 struct stmmac_safety_feature_cfg {
0178     u32 tsoee;
0179     u32 mrxpee;
0180     u32 mestee;
0181     u32 mrxee;
0182     u32 mtxee;
0183     u32 epsi;
0184     u32 edpp;
0185     u32 prtyen;
0186     u32 tmouten;
0187 };
0188
0189 struct plat_stmmacenet_data {
0190     int bus_id;
0191     int phy_addr;
0192     int interface;
0193     phy_interface_t phy_interface;
0194     struct stmmac_mdio_bus_data *mdio_bus_data;
0195     struct device_node *phy_node;
0196     struct device_node *phylink_node;
0197     struct device_node *mdio_node;
0198     struct stmmac_dma_cfg *dma_cfg;
0199     struct stmmac_est *est;
0200     struct stmmac_fpe_cfg *fpe_cfg;
0201     struct stmmac_safety_feature_cfg *safety_feat_cfg;
0202     int clk_csr;
0203     int has_gmac;
0204     int enh_desc;
0205     int tx_coe;
0206     int rx_coe;
0207     int bugged_jumbo;
0208     int pmt;
0209     int force_sf_dma_mode;
0210     int force_thresh_dma_mode;
0211     int riwt_off;
0212     int max_speed;
0213     int maxmtu;
0214     int multicast_filter_bins;
0215     int unicast_filter_entries;
0216     int tx_fifo_size;
0217     int rx_fifo_size;
0218     u32 addr64;
0219     u32 rx_queues_to_use;
0220     u32 tx_queues_to_use;
0221     u8 rx_sched_algorithm;
0222     u8 tx_sched_algorithm;
0223     struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
0224     struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
0225     void (*fix_mac_speed)(void *priv, unsigned int speed);
0226     int (*serdes_powerup)(struct net_device *ndev, void *priv);
0227     void (*serdes_powerdown)(struct net_device *ndev, void *priv);
0228     void (*speed_mode_2500)(struct net_device *ndev, void *priv);
0229     void (*ptp_clk_freq_config)(void *priv);
0230     int (*init)(struct platform_device *pdev, void *priv);
0231     void (*exit)(struct platform_device *pdev, void *priv);
0232     struct mac_device_info *(*setup)(void *priv);
0233     int (*clks_config)(void *priv, bool enabled);
0234     int (*crosststamp)(ktime_t *device, struct system_counterval_t *system,
0235                void *ctx);
0236     void (*dump_debug_regs)(void *priv);
0237     void *bsp_priv;
0238     struct clk *stmmac_clk;
0239     struct clk *pclk;
0240     struct clk *clk_ptp_ref;
0241     unsigned int clk_ptp_rate;
0242     unsigned int clk_ref_rate;
0243     unsigned int mult_fact_100ns;
0244     s32 ptp_max_adj;
0245     u32 cdc_error_adj;
0246     struct reset_control *stmmac_rst;
0247     struct reset_control *stmmac_ahb_rst;
0248     struct stmmac_axi *axi;
0249     int has_gmac4;
0250     bool has_sun8i;
0251     bool tso_en;
0252     int rss_en;
0253     int mac_port_sel_speed;
0254     bool en_tx_lpi_clockgating;
0255     int has_xgmac;
0256     bool vlan_fail_q_en;
0257     u8 vlan_fail_q;
0258     unsigned int eee_usecs_rate;
0259     struct pci_dev *pdev;
0260     bool has_crossts;
0261     int int_snapshot_num;
0262     int ext_snapshot_num;
0263     bool int_snapshot_en;
0264     bool ext_snapshot_en;
0265     bool multi_msi_en;
0266     int msi_mac_vec;
0267     int msi_wol_vec;
0268     int msi_lpi_vec;
0269     int msi_sfty_ce_vec;
0270     int msi_sfty_ue_vec;
0271     int msi_rx_base_vec;
0272     int msi_tx_base_vec;
0273     bool use_phy_wol;
0274     bool sph_disable;
0275 };
0276 #endif