linux/ssb/ssb_driver_pci.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef LINUX_SSB_PCICORE_H_
0003 #define LINUX_SSB_PCICORE_H_
0004
0005 #include <linux/types.h>
0006
0007 struct pci_dev;
0008
0009
0010 #ifdef CONFIG_SSB_DRIVER_PCICORE
0011
0012 /* PCI core registers. */
0013 #define SSB_PCICORE_CTL         0x0000  /* PCI Control */
0014 #define  SSB_PCICORE_CTL_RST_OE     0x00000001 /* PCI_RESET Output Enable */
0015 #define  SSB_PCICORE_CTL_RST        0x00000002 /* PCI_RESET driven out to pin */
0016 #define  SSB_PCICORE_CTL_CLK_OE     0x00000004 /* Clock gate Output Enable */
0017 #define  SSB_PCICORE_CTL_CLK        0x00000008 /* Gate for clock driven out to pin */
0018 #define SSB_PCICORE_ARBCTL      0x0010  /* PCI Arbiter Control */
0019 #define  SSB_PCICORE_ARBCTL_INTERN  0x00000001 /* Use internal arbiter */
0020 #define  SSB_PCICORE_ARBCTL_EXTERN  0x00000002 /* Use external arbiter */
0021 #define  SSB_PCICORE_ARBCTL_PARKID  0x00000006 /* Mask, selects which agent is parked on an idle bus */
0022 #define   SSB_PCICORE_ARBCTL_PARKID_LAST    0x00000000 /* Last requestor */
0023 #define   SSB_PCICORE_ARBCTL_PARKID_4710    0x00000002 /* 4710 */
0024 #define   SSB_PCICORE_ARBCTL_PARKID_EXT0    0x00000004 /* External requestor 0 */
0025 #define   SSB_PCICORE_ARBCTL_PARKID_EXT1    0x00000006 /* External requestor 1 */
0026 #define SSB_PCICORE_ISTAT       0x0020  /* Interrupt status */
0027 #define  SSB_PCICORE_ISTAT_INTA     0x00000001 /* PCI INTA# */
0028 #define  SSB_PCICORE_ISTAT_INTB     0x00000002 /* PCI INTB# */
0029 #define  SSB_PCICORE_ISTAT_SERR     0x00000004 /* PCI SERR# (write to clear) */
0030 #define  SSB_PCICORE_ISTAT_PERR     0x00000008 /* PCI PERR# (write to clear) */
0031 #define  SSB_PCICORE_ISTAT_PME      0x00000010 /* PCI PME# */
0032 #define SSB_PCICORE_IMASK       0x0024  /* Interrupt mask */
0033 #define  SSB_PCICORE_IMASK_INTA     0x00000001 /* PCI INTA# */
0034 #define  SSB_PCICORE_IMASK_INTB     0x00000002 /* PCI INTB# */
0035 #define  SSB_PCICORE_IMASK_SERR     0x00000004 /* PCI SERR# */
0036 #define  SSB_PCICORE_IMASK_PERR     0x00000008 /* PCI PERR# */
0037 #define  SSB_PCICORE_IMASK_PME      0x00000010 /* PCI PME# */
0038 #define SSB_PCICORE_MBOX        0x0028  /* Backplane to PCI Mailbox */
0039 #define  SSB_PCICORE_MBOX_F0_0      0x00000100 /* PCI function 0, INT 0 */
0040 #define  SSB_PCICORE_MBOX_F0_1      0x00000200 /* PCI function 0, INT 1 */
0041 #define  SSB_PCICORE_MBOX_F1_0      0x00000400 /* PCI function 1, INT 0 */
0042 #define  SSB_PCICORE_MBOX_F1_1      0x00000800 /* PCI function 1, INT 1 */
0043 #define  SSB_PCICORE_MBOX_F2_0      0x00001000 /* PCI function 2, INT 0 */
0044 #define  SSB_PCICORE_MBOX_F2_1      0x00002000 /* PCI function 2, INT 1 */
0045 #define  SSB_PCICORE_MBOX_F3_0      0x00004000 /* PCI function 3, INT 0 */
0046 #define  SSB_PCICORE_MBOX_F3_1      0x00008000 /* PCI function 3, INT 1 */
0047 #define SSB_PCICORE_BCAST_ADDR      0x0050  /* Backplane Broadcast Address */
0048 #define  SSB_PCICORE_BCAST_ADDR_MASK    0x000000FF
0049 #define SSB_PCICORE_BCAST_DATA      0x0054  /* Backplane Broadcast Data */
0050 #define SSB_PCICORE_GPIO_IN     0x0060  /* rev >= 2 only */
0051 #define SSB_PCICORE_GPIO_OUT        0x0064  /* rev >= 2 only */
0052 #define SSB_PCICORE_GPIO_ENABLE     0x0068  /* rev >= 2 only */
0053 #define SSB_PCICORE_GPIO_CTL        0x006C  /* rev >= 2 only */
0054 #define SSB_PCICORE_SBTOPCI0        0x0100  /* Backplane to PCI translation 0 (sbtopci0) */
0055 #define  SSB_PCICORE_SBTOPCI0_MASK  0xFC000000
0056 #define SSB_PCICORE_SBTOPCI1        0x0104  /* Backplane to PCI translation 1 (sbtopci1) */
0057 #define  SSB_PCICORE_SBTOPCI1_MASK  0xFC000000
0058 #define SSB_PCICORE_SBTOPCI2        0x0108  /* Backplane to PCI translation 2 (sbtopci2) */
0059 #define  SSB_PCICORE_SBTOPCI2_MASK  0xC0000000
0060 #define SSB_PCICORE_PCICFG0     0x0400  /* PCI config space 0 (rev >= 8) */
0061 #define SSB_PCICORE_PCICFG1     0x0500  /* PCI config space 1 (rev >= 8) */
0062 #define SSB_PCICORE_PCICFG2     0x0600  /* PCI config space 2 (rev >= 8) */
0063 #define SSB_PCICORE_PCICFG3     0x0700  /* PCI config space 3 (rev >= 8) */
0064 #define SSB_PCICORE_SPROM(wordoffset)   (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
0065
0066 /* SBtoPCIx */
0067 #define SSB_PCICORE_SBTOPCI_MEM     0x00000000
0068 #define SSB_PCICORE_SBTOPCI_IO      0x00000001
0069 #define SSB_PCICORE_SBTOPCI_CFG0    0x00000002
0070 #define SSB_PCICORE_SBTOPCI_CFG1    0x00000003
0071 #define SSB_PCICORE_SBTOPCI_PREF    0x00000004 /* Prefetch enable */
0072 #define SSB_PCICORE_SBTOPCI_BURST   0x00000008 /* Burst enable */
0073 #define SSB_PCICORE_SBTOPCI_MRM     0x00000020 /* Memory Read Multiple */
0074 #define SSB_PCICORE_SBTOPCI_RC      0x00000030 /* Read Command mask (rev >= 11) */
0075 #define  SSB_PCICORE_SBTOPCI_RC_READ    0x00000000 /* Memory read */
0076 #define  SSB_PCICORE_SBTOPCI_RC_READL   0x00000010 /* Memory read line */
0077 #define  SSB_PCICORE_SBTOPCI_RC_READM   0x00000020 /* Memory read multiple */
0078
0079
0080 /* PCIcore specific boardflags */
0081 #define SSB_PCICORE_BFL_NOPCI       0x00000400 /* Board leaves PCI floating */
0082
0083
0084 struct ssb_pcicore {
0085     struct ssb_device *dev;
0086     u8 setup_done:1;
0087     u8 hostmode:1;
0088     u8 cardbusmode:1;
0089 };
0090
0091 extern void ssb_pcicore_init(struct ssb_pcicore *pc);
0092
0093 /* Enable IRQ routing for a specific device */
0094 extern int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
0095                       struct ssb_device *dev);
0096
0097 int ssb_pcicore_plat_dev_init(struct pci_dev *d);
0098 int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
0099
0100
0101 #else /* CONFIG_SSB_DRIVER_PCICORE */
0102
0103
0104 struct ssb_pcicore {
0105 };
0106
0107 static inline
0108 void ssb_pcicore_init(struct ssb_pcicore *pc)
0109 {
0110 }
0111
0112 static inline
0113 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
0114                    struct ssb_device *dev)
0115 {
0116     return 0;
0117 }
0118
0119 static inline
0120 int ssb_pcicore_plat_dev_init(struct pci_dev *d)
0121 {
0122     return -ENODEV;
0123 }
0124 static inline
0125 int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
0126 {
0127     return -ENODEV;
0128 }
0129
0130 #endif /* CONFIG_SSB_DRIVER_PCICORE */
0131 #endif /* LINUX_SSB_PCICORE_H_ */