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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef LINUX_SSB_H_
0003 #define LINUX_SSB_H_
0004 
0005 #include <linux/device.h>
0006 #include <linux/list.h>
0007 #include <linux/types.h>
0008 #include <linux/spinlock.h>
0009 #include <linux/pci.h>
0010 #include <linux/gpio/driver.h>
0011 #include <linux/mod_devicetable.h>
0012 #include <linux/dma-mapping.h>
0013 #include <linux/platform_device.h>
0014 
0015 #include <linux/ssb/ssb_regs.h>
0016 
0017 
0018 struct pcmcia_device;
0019 struct ssb_bus;
0020 struct ssb_driver;
0021 
0022 struct ssb_sprom_core_pwr_info {
0023     u8 itssi_2g, itssi_5g;
0024     u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
0025     u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
0026 };
0027 
0028 struct ssb_sprom {
0029     u8 revision;
0030     u8 il0mac[6] __aligned(sizeof(u16));    /* MAC address for 802.11b/g */
0031     u8 et0mac[6] __aligned(sizeof(u16));    /* MAC address for Ethernet */
0032     u8 et1mac[6] __aligned(sizeof(u16));    /* MAC address for 802.11a */
0033     u8 et2mac[6] __aligned(sizeof(u16));    /* MAC address for extra Ethernet */
0034     u8 et0phyaddr;      /* MII address for enet0 */
0035     u8 et1phyaddr;      /* MII address for enet1 */
0036     u8 et2phyaddr;      /* MII address for enet2 */
0037     u8 et0mdcport;      /* MDIO for enet0 */
0038     u8 et1mdcport;      /* MDIO for enet1 */
0039     u8 et2mdcport;      /* MDIO for enet2 */
0040     u16 dev_id;     /* Device ID overriding e.g. PCI ID */
0041     u16 board_rev;      /* Board revision number from SPROM. */
0042     u16 board_num;      /* Board number from SPROM. */
0043     u16 board_type;     /* Board type from SPROM. */
0044     u8 country_code;    /* Country Code */
0045     char alpha2[2];     /* Country Code as two chars like EU or US */
0046     u8 leddc_on_time;   /* LED Powersave Duty Cycle On Count */
0047     u8 leddc_off_time;  /* LED Powersave Duty Cycle Off Count */
0048     u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
0049     u8 ant_available_bg;    /* 5GHz antenna available bits (up to 4) */
0050     u16 pa0b0;
0051     u16 pa0b1;
0052     u16 pa0b2;
0053     u16 pa1b0;
0054     u16 pa1b1;
0055     u16 pa1b2;
0056     u16 pa1lob0;
0057     u16 pa1lob1;
0058     u16 pa1lob2;
0059     u16 pa1hib0;
0060     u16 pa1hib1;
0061     u16 pa1hib2;
0062     u8 gpio0;       /* GPIO pin 0 */
0063     u8 gpio1;       /* GPIO pin 1 */
0064     u8 gpio2;       /* GPIO pin 2 */
0065     u8 gpio3;       /* GPIO pin 3 */
0066     u8 maxpwr_bg;       /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
0067     u8 maxpwr_al;       /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
0068     u8 maxpwr_a;        /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
0069     u8 maxpwr_ah;       /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
0070     u8 itssi_a;     /* Idle TSSI Target for A-PHY */
0071     u8 itssi_bg;        /* Idle TSSI Target for B/G-PHY */
0072     u8 tri2g;       /* 2.4GHz TX isolation */
0073     u8 tri5gl;      /* 5.2GHz TX isolation */
0074     u8 tri5g;       /* 5.3GHz TX isolation */
0075     u8 tri5gh;      /* 5.8GHz TX isolation */
0076     u8 txpid2g[4];      /* 2GHz TX power index */
0077     u8 txpid5gl[4];     /* 4.9 - 5.1GHz TX power index */
0078     u8 txpid5g[4];      /* 5.1 - 5.5GHz TX power index */
0079     u8 txpid5gh[4];     /* 5.5 - ...GHz TX power index */
0080     s8 rxpo2g;      /* 2GHz RX power offset */
0081     s8 rxpo5g;      /* 5GHz RX power offset */
0082     u8 rssisav2g;       /* 2GHz RSSI params */
0083     u8 rssismc2g;
0084     u8 rssismf2g;
0085     u8 bxa2g;       /* 2GHz BX arch */
0086     u8 rssisav5g;       /* 5GHz RSSI params */
0087     u8 rssismc5g;
0088     u8 rssismf5g;
0089     u8 bxa5g;       /* 5GHz BX arch */
0090     u16 cck2gpo;        /* CCK power offset */
0091     u32 ofdm2gpo;       /* 2.4GHz OFDM power offset */
0092     u32 ofdm5glpo;      /* 5.2GHz OFDM power offset */
0093     u32 ofdm5gpo;       /* 5.3GHz OFDM power offset */
0094     u32 ofdm5ghpo;      /* 5.8GHz OFDM power offset */
0095     u32 boardflags;
0096     u32 boardflags2;
0097     u32 boardflags3;
0098     /* TODO: Switch all drivers to new u32 fields and drop below ones */
0099     u16 boardflags_lo;  /* Board flags (bits 0-15) */
0100     u16 boardflags_hi;  /* Board flags (bits 16-31) */
0101     u16 boardflags2_lo; /* Board flags (bits 32-47) */
0102     u16 boardflags2_hi; /* Board flags (bits 48-63) */
0103 
0104     struct ssb_sprom_core_pwr_info core_pwr_info[4];
0105 
0106     /* Antenna gain values for up to 4 antennas
0107      * on each band. Values in dBm/4 (Q5.2). Negative gain means the
0108      * loss in the connectors is bigger than the gain. */
0109     struct {
0110         s8 a0, a1, a2, a3;
0111     } antenna_gain;
0112 
0113     struct {
0114         struct {
0115             u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
0116         } ghz2;
0117         struct {
0118             u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
0119         } ghz5;
0120     } fem;
0121 
0122     u16 mcs2gpo[8];
0123     u16 mcs5gpo[8];
0124     u16 mcs5glpo[8];
0125     u16 mcs5ghpo[8];
0126     u8 opo;
0127 
0128     u8 rxgainerr2ga[3];
0129     u8 rxgainerr5gla[3];
0130     u8 rxgainerr5gma[3];
0131     u8 rxgainerr5gha[3];
0132     u8 rxgainerr5gua[3];
0133 
0134     u8 noiselvl2ga[3];
0135     u8 noiselvl5gla[3];
0136     u8 noiselvl5gma[3];
0137     u8 noiselvl5gha[3];
0138     u8 noiselvl5gua[3];
0139 
0140     u8 regrev;
0141     u8 txchain;
0142     u8 rxchain;
0143     u8 antswitch;
0144     u16 cddpo;
0145     u16 stbcpo;
0146     u16 bw40po;
0147     u16 bwduppo;
0148 
0149     u8 tempthresh;
0150     u8 tempoffset;
0151     u16 rawtempsense;
0152     u8 measpower;
0153     u8 tempsense_slope;
0154     u8 tempcorrx;
0155     u8 tempsense_option;
0156     u8 freqoffset_corr;
0157     u8 iqcal_swp_dis;
0158     u8 hw_iqcal_en;
0159     u8 elna2g;
0160     u8 elna5g;
0161     u8 phycal_tempdelta;
0162     u8 temps_period;
0163     u8 temps_hysteresis;
0164     u8 measpower1;
0165     u8 measpower2;
0166     u8 pcieingress_war;
0167 
0168     /* power per rate from sromrev 9 */
0169     u16 cckbw202gpo;
0170     u16 cckbw20ul2gpo;
0171     u32 legofdmbw202gpo;
0172     u32 legofdmbw20ul2gpo;
0173     u32 legofdmbw205glpo;
0174     u32 legofdmbw20ul5glpo;
0175     u32 legofdmbw205gmpo;
0176     u32 legofdmbw20ul5gmpo;
0177     u32 legofdmbw205ghpo;
0178     u32 legofdmbw20ul5ghpo;
0179     u32 mcsbw202gpo;
0180     u32 mcsbw20ul2gpo;
0181     u32 mcsbw402gpo;
0182     u32 mcsbw205glpo;
0183     u32 mcsbw20ul5glpo;
0184     u32 mcsbw405glpo;
0185     u32 mcsbw205gmpo;
0186     u32 mcsbw20ul5gmpo;
0187     u32 mcsbw405gmpo;
0188     u32 mcsbw205ghpo;
0189     u32 mcsbw20ul5ghpo;
0190     u32 mcsbw405ghpo;
0191     u16 mcs32po;
0192     u16 legofdm40duppo;
0193     u8 sar2g;
0194     u8 sar5g;
0195 };
0196 
0197 /* Information about the PCB the circuitry is soldered on. */
0198 struct ssb_boardinfo {
0199     u16 vendor;
0200     u16 type;
0201 };
0202 
0203 
0204 struct ssb_device;
0205 /* Lowlevel read/write operations on the device MMIO.
0206  * Internal, don't use that outside of ssb. */
0207 struct ssb_bus_ops {
0208     u8 (*read8)(struct ssb_device *dev, u16 offset);
0209     u16 (*read16)(struct ssb_device *dev, u16 offset);
0210     u32 (*read32)(struct ssb_device *dev, u16 offset);
0211     void (*write8)(struct ssb_device *dev, u16 offset, u8 value);
0212     void (*write16)(struct ssb_device *dev, u16 offset, u16 value);
0213     void (*write32)(struct ssb_device *dev, u16 offset, u32 value);
0214 #ifdef CONFIG_SSB_BLOCKIO
0215     void (*block_read)(struct ssb_device *dev, void *buffer,
0216                size_t count, u16 offset, u8 reg_width);
0217     void (*block_write)(struct ssb_device *dev, const void *buffer,
0218                 size_t count, u16 offset, u8 reg_width);
0219 #endif
0220 };
0221 
0222 
0223 /* Core-ID values. */
0224 #define SSB_DEV_CHIPCOMMON  0x800
0225 #define SSB_DEV_ILINE20     0x801
0226 #define SSB_DEV_SDRAM       0x803
0227 #define SSB_DEV_PCI     0x804
0228 #define SSB_DEV_MIPS        0x805
0229 #define SSB_DEV_ETHERNET    0x806
0230 #define SSB_DEV_V90     0x807
0231 #define SSB_DEV_USB11_HOSTDEV   0x808
0232 #define SSB_DEV_ADSL        0x809
0233 #define SSB_DEV_ILINE100    0x80A
0234 #define SSB_DEV_IPSEC       0x80B
0235 #define SSB_DEV_PCMCIA      0x80D
0236 #define SSB_DEV_INTERNAL_MEM    0x80E
0237 #define SSB_DEV_MEMC_SDRAM  0x80F
0238 #define SSB_DEV_EXTIF       0x811
0239 #define SSB_DEV_80211       0x812
0240 #define SSB_DEV_MIPS_3302   0x816
0241 #define SSB_DEV_USB11_HOST  0x817
0242 #define SSB_DEV_USB11_DEV   0x818
0243 #define SSB_DEV_USB20_HOST  0x819
0244 #define SSB_DEV_USB20_DEV   0x81A
0245 #define SSB_DEV_SDIO_HOST   0x81B
0246 #define SSB_DEV_ROBOSWITCH  0x81C
0247 #define SSB_DEV_PARA_ATA    0x81D
0248 #define SSB_DEV_SATA_XORDMA 0x81E
0249 #define SSB_DEV_ETHERNET_GBIT   0x81F
0250 #define SSB_DEV_PCIE        0x820
0251 #define SSB_DEV_MIMO_PHY    0x821
0252 #define SSB_DEV_SRAM_CTRLR  0x822
0253 #define SSB_DEV_MINI_MACPHY 0x823
0254 #define SSB_DEV_ARM_1176    0x824
0255 #define SSB_DEV_ARM_7TDMI   0x825
0256 #define SSB_DEV_ARM_CM3     0x82A
0257 
0258 /* Vendor-ID values */
0259 #define SSB_VENDOR_BROADCOM 0x4243
0260 
0261 /* Some kernel subsystems poke with dev->drvdata, so we must use the
0262  * following ugly workaround to get from struct device to struct ssb_device */
0263 struct __ssb_dev_wrapper {
0264     struct device dev;
0265     struct ssb_device *sdev;
0266 };
0267 
0268 struct ssb_device {
0269     /* Having a copy of the ops pointer in each dev struct
0270      * is an optimization. */
0271     const struct ssb_bus_ops *ops;
0272 
0273     struct device *dev, *dma_dev;
0274 
0275     struct ssb_bus *bus;
0276     struct ssb_device_id id;
0277 
0278     u8 core_index;
0279     unsigned int irq;
0280 
0281     /* Internal-only stuff follows. */
0282     void *drvdata;      /* Per-device data */
0283     void *devtypedata;  /* Per-devicetype (eg 802.11) data */
0284 };
0285 
0286 /* Go from struct device to struct ssb_device. */
0287 static inline
0288 struct ssb_device * dev_to_ssb_dev(struct device *dev)
0289 {
0290     struct __ssb_dev_wrapper *wrap;
0291     wrap = container_of(dev, struct __ssb_dev_wrapper, dev);
0292     return wrap->sdev;
0293 }
0294 
0295 /* Device specific user data */
0296 static inline
0297 void ssb_set_drvdata(struct ssb_device *dev, void *data)
0298 {
0299     dev->drvdata = data;
0300 }
0301 static inline
0302 void * ssb_get_drvdata(struct ssb_device *dev)
0303 {
0304     return dev->drvdata;
0305 }
0306 
0307 /* Devicetype specific user data. This is per device-type (not per device) */
0308 void ssb_set_devtypedata(struct ssb_device *dev, void *data);
0309 static inline
0310 void * ssb_get_devtypedata(struct ssb_device *dev)
0311 {
0312     return dev->devtypedata;
0313 }
0314 
0315 
0316 struct ssb_driver {
0317     const char *name;
0318     const struct ssb_device_id *id_table;
0319 
0320     int (*probe)(struct ssb_device *dev, const struct ssb_device_id *id);
0321     void (*remove)(struct ssb_device *dev);
0322     int (*suspend)(struct ssb_device *dev, pm_message_t state);
0323     int (*resume)(struct ssb_device *dev);
0324     void (*shutdown)(struct ssb_device *dev);
0325 
0326     struct device_driver drv;
0327 };
0328 #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
0329 
0330 extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
0331 #define ssb_driver_register(drv) \
0332     __ssb_driver_register(drv, THIS_MODULE)
0333 
0334 extern void ssb_driver_unregister(struct ssb_driver *drv);
0335 
0336 
0337 
0338 
0339 enum ssb_bustype {
0340     SSB_BUSTYPE_SSB,    /* This SSB bus is the system bus */
0341     SSB_BUSTYPE_PCI,    /* SSB is connected to PCI bus */
0342     SSB_BUSTYPE_PCMCIA, /* SSB is connected to PCMCIA bus */
0343     SSB_BUSTYPE_SDIO,   /* SSB is connected to SDIO bus */
0344 };
0345 
0346 /* board_vendor */
0347 #define SSB_BOARDVENDOR_BCM 0x14E4  /* Broadcom */
0348 #define SSB_BOARDVENDOR_DELL    0x1028  /* Dell */
0349 #define SSB_BOARDVENDOR_HP  0x0E11  /* HP */
0350 /* board_type */
0351 #define SSB_BOARD_BCM94301CB    0x0406
0352 #define SSB_BOARD_BCM94301MP    0x0407
0353 #define SSB_BOARD_BU4309    0x040A
0354 #define SSB_BOARD_BCM94309CB    0x040B
0355 #define SSB_BOARD_BCM4309MP 0x040C
0356 #define SSB_BOARD_BU4306    0x0416
0357 #define SSB_BOARD_BCM94306MP    0x0418
0358 #define SSB_BOARD_BCM4309G  0x0421
0359 #define SSB_BOARD_BCM4306CB 0x0417
0360 #define SSB_BOARD_BCM94306PC    0x0425  /* pcmcia 3.3v 4306 card */
0361 #define SSB_BOARD_BCM94306CBSG  0x042B  /* with SiGe PA */
0362 #define SSB_BOARD_PCSG94306 0x042D  /* with SiGe PA */
0363 #define SSB_BOARD_BU4704SD  0x042E  /* with sdram */
0364 #define SSB_BOARD_BCM94704AGR   0x042F  /* dual 11a/11g Router */
0365 #define SSB_BOARD_BCM94308MP    0x0430  /* 11a-only minipci */
0366 #define SSB_BOARD_BU4318    0x0447
0367 #define SSB_BOARD_CB4318    0x0448
0368 #define SSB_BOARD_MPG4318   0x0449
0369 #define SSB_BOARD_MP4318    0x044A
0370 #define SSB_BOARD_SD4318    0x044B
0371 #define SSB_BOARD_BCM94306P 0x044C  /* with SiGe */
0372 #define SSB_BOARD_BCM94303MP    0x044E
0373 #define SSB_BOARD_BCM94306MPM   0x0450
0374 #define SSB_BOARD_BCM94306MPL   0x0453
0375 #define SSB_BOARD_PC4303    0x0454  /* pcmcia */
0376 #define SSB_BOARD_BCM94306MPLNA 0x0457
0377 #define SSB_BOARD_BCM94306MPH   0x045B
0378 #define SSB_BOARD_BCM94306PCIV  0x045C
0379 #define SSB_BOARD_BCM94318MPGH  0x0463
0380 #define SSB_BOARD_BU4311    0x0464
0381 #define SSB_BOARD_BCM94311MC    0x0465
0382 #define SSB_BOARD_BCM94311MCAG  0x0466
0383 /* 4321 boards */
0384 #define SSB_BOARD_BU4321    0x046B
0385 #define SSB_BOARD_BU4321E   0x047C
0386 #define SSB_BOARD_MP4321    0x046C
0387 #define SSB_BOARD_CB2_4321  0x046D
0388 #define SSB_BOARD_CB2_4321_AG   0x0066
0389 #define SSB_BOARD_MC4321    0x046E
0390 /* 4325 boards */
0391 #define SSB_BOARD_BCM94325DEVBU 0x0490
0392 #define SSB_BOARD_BCM94325BGABU 0x0491
0393 #define SSB_BOARD_BCM94325SDGWB 0x0492
0394 #define SSB_BOARD_BCM94325SDGMDL    0x04AA
0395 #define SSB_BOARD_BCM94325SDGMDL2   0x04C6
0396 #define SSB_BOARD_BCM94325SDGMDL3   0x04C9
0397 #define SSB_BOARD_BCM94325SDABGWBA  0x04E1
0398 /* 4322 boards */
0399 #define SSB_BOARD_BCM94322MC    0x04A4
0400 #define SSB_BOARD_BCM94322USB   0x04A8  /* dualband */
0401 #define SSB_BOARD_BCM94322HM    0x04B0
0402 #define SSB_BOARD_BCM94322USB2D 0x04Bf  /* single band discrete front end */
0403 /* 4312 boards */
0404 #define SSB_BOARD_BU4312    0x048A
0405 #define SSB_BOARD_BCM4312MCGSG  0x04B5
0406 /* chip_package */
0407 #define SSB_CHIPPACK_BCM4712S   1   /* Small 200pin 4712 */
0408 #define SSB_CHIPPACK_BCM4712M   2   /* Medium 225pin 4712 */
0409 #define SSB_CHIPPACK_BCM4712L   0   /* Large 340pin 4712 */
0410 
0411 #include <linux/ssb/ssb_driver_chipcommon.h>
0412 #include <linux/ssb/ssb_driver_mips.h>
0413 #include <linux/ssb/ssb_driver_extif.h>
0414 #include <linux/ssb/ssb_driver_pci.h>
0415 
0416 struct ssb_bus {
0417     /* The MMIO area. */
0418     void __iomem *mmio;
0419 
0420     const struct ssb_bus_ops *ops;
0421 
0422     /* The core currently mapped into the MMIO window.
0423      * Not valid on all host-buses. So don't use outside of SSB. */
0424     struct ssb_device *mapped_device;
0425     union {
0426         /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
0427         u8 mapped_pcmcia_seg;
0428         /* Current SSB base address window for SDIO. */
0429         u32 sdio_sbaddr;
0430     };
0431     /* Lock for core and segment switching.
0432      * On PCMCIA-host busses this is used to protect the whole MMIO access. */
0433     spinlock_t bar_lock;
0434 
0435     /* The host-bus this backplane is running on. */
0436     enum ssb_bustype bustype;
0437     /* Pointers to the host-bus. Check bustype before using any of these pointers. */
0438     union {
0439         /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
0440         struct pci_dev *host_pci;
0441         /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
0442         struct pcmcia_device *host_pcmcia;
0443         /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
0444         struct sdio_func *host_sdio;
0445     };
0446 
0447     /* See enum ssb_quirks */
0448     unsigned int quirks;
0449 
0450 #ifdef CONFIG_SSB_SPROM
0451     /* Mutex to protect the SPROM writing. */
0452     struct mutex sprom_mutex;
0453 #endif
0454 
0455     /* ID information about the Chip. */
0456     u16 chip_id;
0457     u8 chip_rev;
0458     u16 sprom_offset;
0459     u16 sprom_size;     /* number of words in sprom */
0460     u8 chip_package;
0461 
0462     /* List of devices (cores) on the backplane. */
0463     struct ssb_device devices[SSB_MAX_NR_CORES];
0464     u8 nr_devices;
0465 
0466     /* Software ID number for this bus. */
0467     unsigned int busnumber;
0468 
0469     /* The ChipCommon device (if available). */
0470     struct ssb_chipcommon chipco;
0471     /* The PCI-core device (if available). */
0472     struct ssb_pcicore pcicore;
0473     /* The MIPS-core device (if available). */
0474     struct ssb_mipscore mipscore;
0475     /* The EXTif-core device (if available). */
0476     struct ssb_extif extif;
0477 
0478     /* The following structure elements are not available in early
0479      * SSB initialization. Though, they are available for regular
0480      * registered drivers at any stage. So be careful when
0481      * using them in the ssb core code. */
0482 
0483     /* ID information about the PCB. */
0484     struct ssb_boardinfo boardinfo;
0485     /* Contents of the SPROM. */
0486     struct ssb_sprom sprom;
0487     /* If the board has a cardbus slot, this is set to true. */
0488     bool has_cardbus_slot;
0489 
0490 #ifdef CONFIG_SSB_EMBEDDED
0491     /* Lock for GPIO register access. */
0492     spinlock_t gpio_lock;
0493     struct platform_device *watchdog;
0494 #endif /* EMBEDDED */
0495 #ifdef CONFIG_SSB_DRIVER_GPIO
0496     struct gpio_chip gpio;
0497     struct irq_domain *irq_domain;
0498 #endif /* DRIVER_GPIO */
0499 
0500     /* Internal-only stuff follows. Do not touch. */
0501     struct list_head list;
0502     /* Is the bus already powered up? */
0503     bool powered_up;
0504     int power_warn_count;
0505 };
0506 
0507 enum ssb_quirks {
0508     /* SDIO connected card requires performing a read after writing a 32-bit value */
0509     SSB_QUIRK_SDIO_READ_AFTER_WRITE32   = (1 << 0),
0510 };
0511 
0512 /* The initialization-invariants. */
0513 struct ssb_init_invariants {
0514     /* Versioning information about the PCB. */
0515     struct ssb_boardinfo boardinfo;
0516     /* The SPROM information. That's either stored in an
0517      * EEPROM or NVRAM on the board. */
0518     struct ssb_sprom sprom;
0519     /* If the board has a cardbus slot, this is set to true. */
0520     bool has_cardbus_slot;
0521 };
0522 /* Type of function to fetch the invariants. */
0523 typedef int (*ssb_invariants_func_t)(struct ssb_bus *bus,
0524                      struct ssb_init_invariants *iv);
0525 
0526 /* Register SoC bus. */
0527 extern int ssb_bus_host_soc_register(struct ssb_bus *bus,
0528                      unsigned long baseaddr);
0529 #ifdef CONFIG_SSB_PCIHOST
0530 extern int ssb_bus_pcibus_register(struct ssb_bus *bus,
0531                    struct pci_dev *host_pci);
0532 #endif /* CONFIG_SSB_PCIHOST */
0533 #ifdef CONFIG_SSB_PCMCIAHOST
0534 extern int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
0535                       struct pcmcia_device *pcmcia_dev,
0536                       unsigned long baseaddr);
0537 #endif /* CONFIG_SSB_PCMCIAHOST */
0538 #ifdef CONFIG_SSB_SDIOHOST
0539 extern int ssb_bus_sdiobus_register(struct ssb_bus *bus,
0540                     struct sdio_func *sdio_func,
0541                     unsigned int quirks);
0542 #endif /* CONFIG_SSB_SDIOHOST */
0543 
0544 
0545 extern void ssb_bus_unregister(struct ssb_bus *bus);
0546 
0547 /* Does the device have an SPROM? */
0548 extern bool ssb_is_sprom_available(struct ssb_bus *bus);
0549 
0550 /* Set a fallback SPROM.
0551  * See kdoc at the function definition for complete documentation. */
0552 extern int ssb_arch_register_fallback_sprom(
0553         int (*sprom_callback)(struct ssb_bus *bus,
0554         struct ssb_sprom *out));
0555 
0556 /* Suspend a SSB bus.
0557  * Call this from the parent bus suspend routine. */
0558 extern int ssb_bus_suspend(struct ssb_bus *bus);
0559 /* Resume a SSB bus.
0560  * Call this from the parent bus resume routine. */
0561 extern int ssb_bus_resume(struct ssb_bus *bus);
0562 
0563 extern u32 ssb_clockspeed(struct ssb_bus *bus);
0564 
0565 /* Is the device enabled in hardware? */
0566 int ssb_device_is_enabled(struct ssb_device *dev);
0567 /* Enable a device and pass device-specific SSB_TMSLOW flags.
0568  * If no device-specific flags are available, use 0. */
0569 void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags);
0570 /* Disable a device in hardware and pass SSB_TMSLOW flags (if any). */
0571 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags);
0572 
0573 
0574 /* Device MMIO register read/write functions. */
0575 static inline u8 ssb_read8(struct ssb_device *dev, u16 offset)
0576 {
0577     return dev->ops->read8(dev, offset);
0578 }
0579 static inline u16 ssb_read16(struct ssb_device *dev, u16 offset)
0580 {
0581     return dev->ops->read16(dev, offset);
0582 }
0583 static inline u32 ssb_read32(struct ssb_device *dev, u16 offset)
0584 {
0585     return dev->ops->read32(dev, offset);
0586 }
0587 static inline void ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
0588 {
0589     dev->ops->write8(dev, offset, value);
0590 }
0591 static inline void ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
0592 {
0593     dev->ops->write16(dev, offset, value);
0594 }
0595 static inline void ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
0596 {
0597     dev->ops->write32(dev, offset, value);
0598 }
0599 #ifdef CONFIG_SSB_BLOCKIO
0600 static inline void ssb_block_read(struct ssb_device *dev, void *buffer,
0601                   size_t count, u16 offset, u8 reg_width)
0602 {
0603     dev->ops->block_read(dev, buffer, count, offset, reg_width);
0604 }
0605 
0606 static inline void ssb_block_write(struct ssb_device *dev, const void *buffer,
0607                    size_t count, u16 offset, u8 reg_width)
0608 {
0609     dev->ops->block_write(dev, buffer, count, offset, reg_width);
0610 }
0611 #endif /* CONFIG_SSB_BLOCKIO */
0612 
0613 
0614 /* The SSB DMA API. Use this API for any DMA operation on the device.
0615  * This API basically is a wrapper that calls the correct DMA API for
0616  * the host device type the SSB device is attached to. */
0617 
0618 /* Translation (routing) bits that need to be ORed to DMA
0619  * addresses before they are given to a device. */
0620 extern u32 ssb_dma_translation(struct ssb_device *dev);
0621 #define SSB_DMA_TRANSLATION_MASK    0xC0000000
0622 #define SSB_DMA_TRANSLATION_SHIFT   30
0623 
0624 static inline void __cold __ssb_dma_not_implemented(struct ssb_device *dev)
0625 {
0626 #ifdef CONFIG_SSB_DEBUG
0627     printk(KERN_ERR "SSB: BUG! Calling DMA API for "
0628            "unsupported bustype %d\n", dev->bus->bustype);
0629 #endif /* DEBUG */
0630 }
0631 
0632 #ifdef CONFIG_SSB_PCIHOST
0633 /* PCI-host wrapper driver */
0634 extern int ssb_pcihost_register(struct pci_driver *driver);
0635 static inline void ssb_pcihost_unregister(struct pci_driver *driver)
0636 {
0637     pci_unregister_driver(driver);
0638 }
0639 
0640 static inline
0641 void ssb_pcihost_set_power_state(struct ssb_device *sdev, pci_power_t state)
0642 {
0643     if (sdev->bus->bustype == SSB_BUSTYPE_PCI)
0644         pci_set_power_state(sdev->bus->host_pci, state);
0645 }
0646 #else
0647 static inline void ssb_pcihost_unregister(struct pci_driver *driver)
0648 {
0649 }
0650 
0651 static inline
0652 void ssb_pcihost_set_power_state(struct ssb_device *sdev, pci_power_t state)
0653 {
0654 }
0655 #endif /* CONFIG_SSB_PCIHOST */
0656 
0657 
0658 /* If a driver is shutdown or suspended, call this to signal
0659  * that the bus may be completely powered down. SSB will decide,
0660  * if it's really time to power down the bus, based on if there
0661  * are other devices that want to run. */
0662 extern int ssb_bus_may_powerdown(struct ssb_bus *bus);
0663 /* Before initializing and enabling a device, call this to power-up the bus.
0664  * If you want to allow use of dynamic-power-control, pass the flag.
0665  * Otherwise static always-on powercontrol will be used. */
0666 extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
0667 
0668 extern void ssb_commit_settings(struct ssb_bus *bus);
0669 
0670 /* Various helper functions */
0671 extern u32 ssb_admatch_base(u32 adm);
0672 extern u32 ssb_admatch_size(u32 adm);
0673 
0674 /* PCI device mapping and fixup routines.
0675  * Called from the architecture pcibios init code.
0676  * These are only available on SSB_EMBEDDED configurations. */
0677 #ifdef CONFIG_SSB_EMBEDDED
0678 int ssb_pcibios_plat_dev_init(struct pci_dev *dev);
0679 int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
0680 #endif /* CONFIG_SSB_EMBEDDED */
0681 
0682 #endif /* LINUX_SSB_H_ */
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