linux/soundwire/sdw_intel.h

0001 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
0002 /* Copyright(c) 2015-17 Intel Corporation. */
0003
0004 #ifndef __SDW_INTEL_H
0005 #define __SDW_INTEL_H
0006
0007 #include <linux/irqreturn.h>
0008 #include <linux/soundwire/sdw.h>
0009
0010 #define SDW_SHIM_BASE           0x2C000
0011 #define SDW_ALH_BASE            0x2C800
0012 #define SDW_SHIM_BASE_ACE       0x38000
0013 #define SDW_ALH_BASE_ACE        0x24000
0014 #define SDW_LINK_BASE           0x30000
0015 #define SDW_LINK_SIZE           0x10000
0016
0017 /* Intel SHIM Registers Definition */
0018 #define SDW_SHIM_LCAP           0x0
0019 #define SDW_SHIM_LCTL           0x4
0020 #define SDW_SHIM_IPPTR          0x8
0021 #define SDW_SHIM_SYNC           0xC
0022
0023 #define SDW_SHIM_CTLSCAP(x)     (0x010 + 0x60 * (x))
0024 #define SDW_SHIM_CTLS0CM(x)     (0x012 + 0x60 * (x))
0025 #define SDW_SHIM_CTLS1CM(x)     (0x014 + 0x60 * (x))
0026 #define SDW_SHIM_CTLS2CM(x)     (0x016 + 0x60 * (x))
0027 #define SDW_SHIM_CTLS3CM(x)     (0x018 + 0x60 * (x))
0028 #define SDW_SHIM_PCMSCAP(x)     (0x020 + 0x60 * (x))
0029
0030 #define SDW_SHIM_PCMSYCHM(x, y)     (0x022 + (0x60 * (x)) + (0x2 * (y)))
0031 #define SDW_SHIM_PCMSYCHC(x, y)     (0x042 + (0x60 * (x)) + (0x2 * (y)))
0032 #define SDW_SHIM_PDMSCAP(x)     (0x062 + 0x60 * (x))
0033 #define SDW_SHIM_IOCTL(x)       (0x06C + 0x60 * (x))
0034 #define SDW_SHIM_CTMCTL(x)      (0x06E + 0x60 * (x))
0035
0036 #define SDW_SHIM_WAKEEN         0x190
0037 #define SDW_SHIM_WAKESTS        0x192
0038
0039 #define SDW_SHIM_LCTL_SPA       BIT(0)
0040 #define SDW_SHIM_LCTL_SPA_MASK      GENMASK(3, 0)
0041 #define SDW_SHIM_LCTL_CPA       BIT(8)
0042 #define SDW_SHIM_LCTL_CPA_MASK      GENMASK(11, 8)
0043
0044 #define SDW_SHIM_SYNC_SYNCPRD_VAL_24    (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
0045 #define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4  (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
0046 #define SDW_SHIM_SYNC_SYNCPRD       GENMASK(14, 0)
0047 #define SDW_SHIM_SYNC_SYNCCPU       BIT(15)
0048 #define SDW_SHIM_SYNC_CMDSYNC_MASK  GENMASK(19, 16)
0049 #define SDW_SHIM_SYNC_CMDSYNC       BIT(16)
0050 #define SDW_SHIM_SYNC_SYNCGO        BIT(24)
0051
0052 #define SDW_SHIM_PCMSCAP_ISS        GENMASK(3, 0)
0053 #define SDW_SHIM_PCMSCAP_OSS        GENMASK(7, 4)
0054 #define SDW_SHIM_PCMSCAP_BSS        GENMASK(12, 8)
0055
0056 #define SDW_SHIM_PCMSYCM_LCHN       GENMASK(3, 0)
0057 #define SDW_SHIM_PCMSYCM_HCHN       GENMASK(7, 4)
0058 #define SDW_SHIM_PCMSYCM_STREAM     GENMASK(13, 8)
0059 #define SDW_SHIM_PCMSYCM_DIR        BIT(15)
0060
0061 #define SDW_SHIM_PDMSCAP_ISS        GENMASK(3, 0)
0062 #define SDW_SHIM_PDMSCAP_OSS        GENMASK(7, 4)
0063 #define SDW_SHIM_PDMSCAP_BSS        GENMASK(12, 8)
0064 #define SDW_SHIM_PDMSCAP_CPSS       GENMASK(15, 13)
0065
0066 #define SDW_SHIM_IOCTL_MIF      BIT(0)
0067 #define SDW_SHIM_IOCTL_CO       BIT(1)
0068 #define SDW_SHIM_IOCTL_COE      BIT(2)
0069 #define SDW_SHIM_IOCTL_DO       BIT(3)
0070 #define SDW_SHIM_IOCTL_DOE      BIT(4)
0071 #define SDW_SHIM_IOCTL_BKE      BIT(5)
0072 #define SDW_SHIM_IOCTL_WPDD     BIT(6)
0073 #define SDW_SHIM_IOCTL_CIBD     BIT(8)
0074 #define SDW_SHIM_IOCTL_DIBD     BIT(9)
0075
0076 #define SDW_SHIM_CTMCTL_DACTQE      BIT(0)
0077 #define SDW_SHIM_CTMCTL_DODS        BIT(1)
0078 #define SDW_SHIM_CTMCTL_DOAIS       GENMASK(4, 3)
0079
0080 #define SDW_SHIM_WAKEEN_ENABLE      BIT(0)
0081 #define SDW_SHIM_WAKESTS_STATUS     BIT(0)
0082
0083 /* Intel ALH Register definitions */
0084 #define SDW_ALH_STRMZCFG(x)     (0x000 + (0x4 * (x)))
0085 #define SDW_ALH_NUM_STREAMS     64
0086
0087 #define SDW_ALH_STRMZCFG_DMAT_VAL   0x3
0088 #define SDW_ALH_STRMZCFG_DMAT       GENMASK(7, 0)
0089 #define SDW_ALH_STRMZCFG_CHN        GENMASK(19, 16)
0090
0091 /**
0092  * struct sdw_intel_stream_params_data: configuration passed during
0093  * the @params_stream callback, e.g. for interaction with DSP
0094  * firmware.
0095  */
0096 struct sdw_intel_stream_params_data {
0097     int stream;
0098     struct snd_soc_dai *dai;
0099     struct snd_pcm_hw_params *hw_params;
0100     int link_id;
0101     int alh_stream_id;
0102 };
0103
0104 /**
0105  * struct sdw_intel_stream_free_data: configuration passed during
0106  * the @free_stream callback, e.g. for interaction with DSP
0107  * firmware.
0108  */
0109 struct sdw_intel_stream_free_data {
0110     int stream;
0111     struct snd_soc_dai *dai;
0112     int link_id;
0113 };
0114
0115 /**
0116  * struct sdw_intel_ops: Intel audio driver callback ops
0117  *
0118  */
0119 struct sdw_intel_ops {
0120     int (*params_stream)(struct device *dev,
0121                  struct sdw_intel_stream_params_data *params_data);
0122     int (*free_stream)(struct device *dev,
0123                struct sdw_intel_stream_free_data *free_data);
0124     int (*trigger)(struct snd_soc_dai *dai, int cmd, int stream);
0125 };
0126
0127 /**
0128  * struct sdw_intel_acpi_info - Soundwire Intel information found in ACPI tables
0129  * @handle: ACPI controller handle
0130  * @count: link count found with "sdw-master-count" property
0131  * @link_mask: bit-wise mask listing links enabled by BIOS menu
0132  *
0133  * this structure could be expanded to e.g. provide all the _ADR
0134  * information in case the link_mask is not sufficient to identify
0135  * platform capabilities.
0136  */
0137 struct sdw_intel_acpi_info {
0138     acpi_handle handle;
0139     int count;
0140     u32 link_mask;
0141 };
0142
0143 struct sdw_intel_link_dev;
0144
0145 /* Intel clock-stop/pm_runtime quirk definitions */
0146
0147 /*
0148  * Force the clock to remain on during pm_runtime suspend. This might
0149  * be needed if Slave devices do not have an alternate clock source or
0150  * if the latency requirements are very strict.
0151  */
0152 #define SDW_INTEL_CLK_STOP_NOT_ALLOWED      BIT(0)
0153
0154 /*
0155  * Stop the bus during pm_runtime suspend. If set, a complete bus
0156  * reset and re-enumeration will be performed when the bus
0157  * restarts. This mode shall not be used if Slave devices can generate
0158  * in-band wakes.
0159  */
0160 #define SDW_INTEL_CLK_STOP_TEARDOWN     BIT(1)
0161
0162 /*
0163  * Stop the bus during pm_suspend if Slaves are not wake capable
0164  * (e.g. speaker amplifiers). The clock-stop mode is typically
0165  * slightly higher power than when the IP is completely powered-off.
0166  */
0167 #define SDW_INTEL_CLK_STOP_WAKE_CAPABLE_ONLY    BIT(2)
0168
0169 /*
0170  * Require a bus reset (and complete re-enumeration) when exiting
0171  * clock stop modes. This may be needed if the controller power was
0172  * turned off and all context lost. This quirk shall not be used if a
0173  * Slave device needs to remain enumerated and keep its context,
0174  * e.g. to provide the reasons for the wake, report acoustic events or
0175  * pass a history buffer.
0176  */
0177 #define SDW_INTEL_CLK_STOP_BUS_RESET        BIT(3)
0178
0179 struct sdw_intel_slave_id {
0180     int link_id;
0181     struct sdw_slave_id id;
0182 };
0183
0184 /**
0185  * struct sdw_intel_ctx - context allocated by the controller
0186  * driver probe
0187  * @count: link count
0188  * @mmio_base: mmio base of SoundWire registers, only used to check
0189  * hardware capabilities after all power dependencies are settled.
0190  * @link_mask: bit-wise mask listing SoundWire links reported by the
0191  * Controller
0192  * @num_slaves: total number of devices exposed across all enabled links
0193  * @handle: ACPI parent handle
0194  * @ldev: information for each link (controller-specific and kept
0195  * opaque here)
0196  * @ids: array of slave_id, representing Slaves exposed across all enabled
0197  * links
0198  * @link_list: list to handle interrupts across all links
0199  * @shim_lock: mutex to handle concurrent rmw access to shared SHIM registers.
0200  * @shim_mask: flags to track initialization of SHIM shared registers
0201  * @shim_base: sdw shim base.
0202  * @alh_base: sdw alh base.
0203  */
0204 struct sdw_intel_ctx {
0205     int count;
0206     void __iomem *mmio_base;
0207     u32 link_mask;
0208     int num_slaves;
0209     acpi_handle handle;
0210     struct sdw_intel_link_dev **ldev;
0211     struct sdw_intel_slave_id *ids;
0212     struct list_head link_list;
0213     struct mutex shim_lock; /* lock for access to shared SHIM registers */
0214     u32 shim_mask;
0215     u32 shim_base;
0216     u32 alh_base;
0217 };
0218
0219 /**
0220  * struct sdw_intel_res - Soundwire Intel global resource structure,
0221  * typically populated by the DSP driver
0222  *
0223  * @count: link count
0224  * @mmio_base: mmio base of SoundWire registers
0225  * @irq: interrupt number
0226  * @handle: ACPI parent handle
0227  * @parent: parent device
0228  * @ops: callback ops
0229  * @dev: device implementing hwparams and free callbacks
0230  * @link_mask: bit-wise mask listing links selected by the DSP driver
0231  * This mask may be a subset of the one reported by the controller since
0232  * machine-specific quirks are handled in the DSP driver.
0233  * @clock_stop_quirks: mask array of possible behaviors requested by the
0234  * DSP driver. The quirks are common for all links for now.
0235  * @shim_base: sdw shim base.
0236  * @alh_base: sdw alh base.
0237  */
0238 struct sdw_intel_res {
0239     int count;
0240     void __iomem *mmio_base;
0241     int irq;
0242     acpi_handle handle;
0243     struct device *parent;
0244     const struct sdw_intel_ops *ops;
0245     struct device *dev;
0246     u32 link_mask;
0247     u32 clock_stop_quirks;
0248     u32 shim_base;
0249     u32 alh_base;
0250 };
0251
0252 /*
0253  * On Intel platforms, the SoundWire IP has dependencies on power
0254  * rails shared with the DSP, and the initialization steps are split
0255  * in three. First an ACPI scan to check what the firmware describes
0256  * in DSDT tables, then an allocation step (with no hardware
0257  * configuration but with all the relevant devices created) and last
0258  * the actual hardware configuration. The final stage is a global
0259  * interrupt enable which is controlled by the DSP driver. Splitting
0260  * these phases helps simplify the boot flow and make early decisions
0261  * on e.g. which machine driver to select (I2S mode, HDaudio or
0262  * SoundWire).
0263  */
0264 int sdw_intel_acpi_scan(acpi_handle *parent_handle,
0265             struct sdw_intel_acpi_info *info);
0266
0267 void sdw_intel_process_wakeen_event(struct sdw_intel_ctx *ctx);
0268
0269 struct sdw_intel_ctx *
0270 sdw_intel_probe(struct sdw_intel_res *res);
0271
0272 int sdw_intel_startup(struct sdw_intel_ctx *ctx);
0273
0274 void sdw_intel_exit(struct sdw_intel_ctx *ctx);
0275
0276 void sdw_intel_enable_irq(void __iomem *mmio_base, bool enable);
0277
0278 irqreturn_t sdw_intel_thread(int irq, void *dev_id);
0279
0280 #define SDW_INTEL_QUIRK_MASK_BUS_DISABLE      BIT(1)
0281
0282 #endif