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0001 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 0002 /* Copyright(c) 2015-17 Intel Corporation. */ 0003 0004 #ifndef __SOUNDWIRE_H 0005 #define __SOUNDWIRE_H 0006 0007 #include <linux/mod_devicetable.h> 0008 #include <linux/bitfield.h> 0009 0010 struct sdw_bus; 0011 struct sdw_slave; 0012 0013 /* SDW spec defines and enums, as defined by MIPI 1.1. Spec */ 0014 0015 /* SDW Broadcast Device Number */ 0016 #define SDW_BROADCAST_DEV_NUM 15 0017 0018 /* SDW Enumeration Device Number */ 0019 #define SDW_ENUM_DEV_NUM 0 0020 0021 /* SDW Group Device Numbers */ 0022 #define SDW_GROUP12_DEV_NUM 12 0023 #define SDW_GROUP13_DEV_NUM 13 0024 0025 /* SDW Master Device Number, not supported yet */ 0026 #define SDW_MASTER_DEV_NUM 14 0027 0028 #define SDW_NUM_DEV_ID_REGISTERS 6 0029 /* frame shape defines */ 0030 0031 /* 0032 * Note: The maximum row define in SoundWire spec 1.1 is 23. In order to 0033 * fill hole with 0, one more dummy entry is added 0034 */ 0035 #define SDW_FRAME_ROWS 24 0036 #define SDW_FRAME_COLS 8 0037 #define SDW_FRAME_ROW_COLS (SDW_FRAME_ROWS * SDW_FRAME_COLS) 0038 0039 #define SDW_FRAME_CTRL_BITS 48 0040 #define SDW_MAX_DEVICES 11 0041 0042 #define SDW_MAX_PORTS 15 0043 #define SDW_VALID_PORT_RANGE(n) ((n) < SDW_MAX_PORTS && (n) >= 1) 0044 0045 enum { 0046 SDW_PORT_DIRN_SINK = 0, 0047 SDW_PORT_DIRN_SOURCE, 0048 SDW_PORT_DIRN_MAX, 0049 }; 0050 0051 /* 0052 * constants for flow control, ports and transport 0053 * 0054 * these are bit masks as devices can have multiple capabilities 0055 */ 0056 0057 /* 0058 * flow modes for SDW port. These can be isochronous, tx controlled, 0059 * rx controlled or async 0060 */ 0061 #define SDW_PORT_FLOW_MODE_ISOCH 0 0062 #define SDW_PORT_FLOW_MODE_TX_CNTRL BIT(0) 0063 #define SDW_PORT_FLOW_MODE_RX_CNTRL BIT(1) 0064 #define SDW_PORT_FLOW_MODE_ASYNC GENMASK(1, 0) 0065 0066 /* sample packaging for block. It can be per port or per channel */ 0067 #define SDW_BLOCK_PACKG_PER_PORT BIT(0) 0068 #define SDW_BLOCK_PACKG_PER_CH BIT(1) 0069 0070 /** 0071 * enum sdw_slave_status - Slave status 0072 * @SDW_SLAVE_UNATTACHED: Slave is not attached with the bus. 0073 * @SDW_SLAVE_ATTACHED: Slave is attached with bus. 0074 * @SDW_SLAVE_ALERT: Some alert condition on the Slave 0075 * @SDW_SLAVE_RESERVED: Reserved for future use 0076 */ 0077 enum sdw_slave_status { 0078 SDW_SLAVE_UNATTACHED = 0, 0079 SDW_SLAVE_ATTACHED = 1, 0080 SDW_SLAVE_ALERT = 2, 0081 SDW_SLAVE_RESERVED = 3, 0082 }; 0083 0084 /** 0085 * enum sdw_clk_stop_type: clock stop operations 0086 * 0087 * @SDW_CLK_PRE_PREPARE: pre clock stop prepare 0088 * @SDW_CLK_POST_PREPARE: post clock stop prepare 0089 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare 0090 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare 0091 */ 0092 enum sdw_clk_stop_type { 0093 SDW_CLK_PRE_PREPARE = 0, 0094 SDW_CLK_POST_PREPARE, 0095 SDW_CLK_PRE_DEPREPARE, 0096 SDW_CLK_POST_DEPREPARE, 0097 }; 0098 0099 /** 0100 * enum sdw_command_response - Command response as defined by SDW spec 0101 * @SDW_CMD_OK: cmd was successful 0102 * @SDW_CMD_IGNORED: cmd was ignored 0103 * @SDW_CMD_FAIL: cmd was NACKed 0104 * @SDW_CMD_TIMEOUT: cmd timedout 0105 * @SDW_CMD_FAIL_OTHER: cmd failed due to other reason than above 0106 * 0107 * NOTE: The enum is different than actual Spec as response in the Spec is 0108 * combination of ACK/NAK bits 0109 * 0110 * SDW_CMD_TIMEOUT/FAIL_OTHER is defined for SW use, not in spec 0111 */ 0112 enum sdw_command_response { 0113 SDW_CMD_OK = 0, 0114 SDW_CMD_IGNORED = 1, 0115 SDW_CMD_FAIL = 2, 0116 SDW_CMD_TIMEOUT = 3, 0117 SDW_CMD_FAIL_OTHER = 4, 0118 }; 0119 0120 /* block group count enum */ 0121 enum sdw_dpn_grouping { 0122 SDW_BLK_GRP_CNT_1 = 0, 0123 SDW_BLK_GRP_CNT_2 = 1, 0124 SDW_BLK_GRP_CNT_3 = 2, 0125 SDW_BLK_GRP_CNT_4 = 3, 0126 }; 0127 0128 /* block packing mode enum */ 0129 enum sdw_dpn_pkg_mode { 0130 SDW_BLK_PKG_PER_PORT = 0, 0131 SDW_BLK_PKG_PER_CHANNEL = 1 0132 }; 0133 0134 /** 0135 * enum sdw_stream_type: data stream type 0136 * 0137 * @SDW_STREAM_PCM: PCM data stream 0138 * @SDW_STREAM_PDM: PDM data stream 0139 * 0140 * spec doesn't define this, but is used in implementation 0141 */ 0142 enum sdw_stream_type { 0143 SDW_STREAM_PCM = 0, 0144 SDW_STREAM_PDM = 1, 0145 }; 0146 0147 /** 0148 * enum sdw_data_direction: Data direction 0149 * 0150 * @SDW_DATA_DIR_RX: Data into Port 0151 * @SDW_DATA_DIR_TX: Data out of Port 0152 */ 0153 enum sdw_data_direction { 0154 SDW_DATA_DIR_RX = 0, 0155 SDW_DATA_DIR_TX = 1, 0156 }; 0157 0158 /** 0159 * enum sdw_port_data_mode: Data Port mode 0160 * 0161 * @SDW_PORT_DATA_MODE_NORMAL: Normal data mode where audio data is received 0162 * and transmitted. 0163 * @SDW_PORT_DATA_MODE_PRBS: Test mode which uses a PRBS generator to produce 0164 * a pseudo random data pattern that is transferred 0165 * @SDW_PORT_DATA_MODE_STATIC_0: Simple test mode which uses static value of 0166 * logic 0. The encoding will result in no signal transitions 0167 * @SDW_PORT_DATA_MODE_STATIC_1: Simple test mode which uses static value of 0168 * logic 1. The encoding will result in signal transitions at every bitslot 0169 * owned by this Port 0170 */ 0171 enum sdw_port_data_mode { 0172 SDW_PORT_DATA_MODE_NORMAL = 0, 0173 SDW_PORT_DATA_MODE_PRBS = 1, 0174 SDW_PORT_DATA_MODE_STATIC_0 = 2, 0175 SDW_PORT_DATA_MODE_STATIC_1 = 3, 0176 }; 0177 0178 /* 0179 * SDW properties, defined in MIPI DisCo spec v1.0 0180 */ 0181 enum sdw_clk_stop_reset_behave { 0182 SDW_CLK_STOP_KEEP_STATUS = 1, 0183 }; 0184 0185 /** 0186 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a 0187 * read 0188 * @SDW_P15_READ_IGNORED: Read is ignored 0189 * @SDW_P15_CMD_OK: Command is ok 0190 */ 0191 enum sdw_p15_behave { 0192 SDW_P15_READ_IGNORED = 0, 0193 SDW_P15_CMD_OK = 1, 0194 }; 0195 0196 /** 0197 * enum sdw_dpn_type - Data port types 0198 * @SDW_DPN_FULL: Full Data Port is supported 0199 * @SDW_DPN_SIMPLE: Simplified Data Port as defined in spec. 0200 * DPN_SampleCtrl2, DPN_OffsetCtrl2, DPN_HCtrl and DPN_BlockCtrl3 0201 * are not implemented. 0202 * @SDW_DPN_REDUCED: Reduced Data Port as defined in spec. 0203 * DPN_SampleCtrl2, DPN_HCtrl are not implemented. 0204 */ 0205 enum sdw_dpn_type { 0206 SDW_DPN_FULL = 0, 0207 SDW_DPN_SIMPLE = 1, 0208 SDW_DPN_REDUCED = 2, 0209 }; 0210 0211 /** 0212 * enum sdw_clk_stop_mode - Clock Stop modes 0213 * @SDW_CLK_STOP_MODE0: Slave can continue operation seamlessly on clock 0214 * restart 0215 * @SDW_CLK_STOP_MODE1: Slave may have entered a deeper power-saving mode, 0216 * not capable of continuing operation seamlessly when the clock restarts 0217 */ 0218 enum sdw_clk_stop_mode { 0219 SDW_CLK_STOP_MODE0 = 0, 0220 SDW_CLK_STOP_MODE1 = 1, 0221 }; 0222 0223 /** 0224 * struct sdw_dp0_prop - DP0 properties 0225 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64 0226 * (inclusive) 0227 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64 0228 * (inclusive) 0229 * @num_words: number of wordlengths supported 0230 * @words: wordlengths supported 0231 * @BRA_flow_controlled: Slave implementation results in an OK_NotReady 0232 * response 0233 * @simple_ch_prep_sm: If channel prepare sequence is required 0234 * @imp_def_interrupts: If set, each bit corresponds to support for 0235 * implementation-defined interrupts 0236 * 0237 * The wordlengths are specified by Spec as max, min AND number of 0238 * discrete values, implementation can define based on the wordlengths they 0239 * support 0240 */ 0241 struct sdw_dp0_prop { 0242 u32 max_word; 0243 u32 min_word; 0244 u32 num_words; 0245 u32 *words; 0246 bool BRA_flow_controlled; 0247 bool simple_ch_prep_sm; 0248 bool imp_def_interrupts; 0249 }; 0250 0251 /** 0252 * struct sdw_dpn_audio_mode - Audio mode properties for DPn 0253 * @bus_min_freq: Minimum bus frequency, in Hz 0254 * @bus_max_freq: Maximum bus frequency, in Hz 0255 * @bus_num_freq: Number of discrete frequencies supported 0256 * @bus_freq: Discrete bus frequencies, in Hz 0257 * @min_freq: Minimum sampling frequency, in Hz 0258 * @max_freq: Maximum sampling bus frequency, in Hz 0259 * @num_freq: Number of discrete sampling frequency supported 0260 * @freq: Discrete sampling frequencies, in Hz 0261 * @prep_ch_behave: Specifies the dependencies between Channel Prepare 0262 * sequence and bus clock configuration 0263 * If 0, Channel Prepare can happen at any Bus clock rate 0264 * If 1, Channel Prepare sequence shall happen only after Bus clock is 0265 * changed to a frequency supported by this mode or compatible modes 0266 * described by the next field 0267 * @glitchless: Bitmap describing possible glitchless transitions from this 0268 * Audio Mode to other Audio Modes 0269 */ 0270 struct sdw_dpn_audio_mode { 0271 u32 bus_min_freq; 0272 u32 bus_max_freq; 0273 u32 bus_num_freq; 0274 u32 *bus_freq; 0275 u32 max_freq; 0276 u32 min_freq; 0277 u32 num_freq; 0278 u32 *freq; 0279 u32 prep_ch_behave; 0280 u32 glitchless; 0281 }; 0282 0283 /** 0284 * struct sdw_dpn_prop - Data Port DPn properties 0285 * @num: port number 0286 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64 0287 * (inclusive) 0288 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64 0289 * (inclusive) 0290 * @num_words: Number of discrete supported wordlengths 0291 * @words: Discrete supported wordlength 0292 * @type: Data port type. Full, Simplified or Reduced 0293 * @max_grouping: Maximum number of samples that can be grouped together for 0294 * a full data port 0295 * @simple_ch_prep_sm: If the port supports simplified channel prepare state 0296 * machine 0297 * @ch_prep_timeout: Port-specific timeout value, in milliseconds 0298 * @imp_def_interrupts: If set, each bit corresponds to support for 0299 * implementation-defined interrupts 0300 * @max_ch: Maximum channels supported 0301 * @min_ch: Minimum channels supported 0302 * @num_channels: Number of discrete channels supported 0303 * @channels: Discrete channels supported 0304 * @num_ch_combinations: Number of channel combinations supported 0305 * @ch_combinations: Channel combinations supported 0306 * @modes: SDW mode supported 0307 * @max_async_buffer: Number of samples that this port can buffer in 0308 * asynchronous modes 0309 * @block_pack_mode: Type of block port mode supported 0310 * @read_only_wordlength: Read Only wordlength field in DPN_BlockCtrl1 register 0311 * @port_encoding: Payload Channel Sample encoding schemes supported 0312 * @audio_modes: Audio modes supported 0313 */ 0314 struct sdw_dpn_prop { 0315 u32 num; 0316 u32 max_word; 0317 u32 min_word; 0318 u32 num_words; 0319 u32 *words; 0320 enum sdw_dpn_type type; 0321 u32 max_grouping; 0322 bool simple_ch_prep_sm; 0323 u32 ch_prep_timeout; 0324 u32 imp_def_interrupts; 0325 u32 max_ch; 0326 u32 min_ch; 0327 u32 num_channels; 0328 u32 *channels; 0329 u32 num_ch_combinations; 0330 u32 *ch_combinations; 0331 u32 modes; 0332 u32 max_async_buffer; 0333 bool block_pack_mode; 0334 bool read_only_wordlength; 0335 u32 port_encoding; 0336 struct sdw_dpn_audio_mode *audio_modes; 0337 }; 0338 0339 /** 0340 * struct sdw_slave_prop - SoundWire Slave properties 0341 * @mipi_revision: Spec version of the implementation 0342 * @wake_capable: Wake-up events are supported 0343 * @test_mode_capable: If test mode is supported 0344 * @clk_stop_mode1: Clock-Stop Mode 1 is supported 0345 * @simple_clk_stop_capable: Simple clock mode is supported 0346 * @clk_stop_timeout: Worst-case latency of the Clock Stop Prepare State 0347 * Machine transitions, in milliseconds 0348 * @ch_prep_timeout: Worst-case latency of the Channel Prepare State Machine 0349 * transitions, in milliseconds 0350 * @reset_behave: Slave keeps the status of the SlaveStopClockPrepare 0351 * state machine (P=1 SCSP_SM) after exit from clock-stop mode1 0352 * @high_PHY_capable: Slave is HighPHY capable 0353 * @paging_support: Slave implements paging registers SCP_AddrPage1 and 0354 * SCP_AddrPage2 0355 * @bank_delay_support: Slave implements bank delay/bridge support registers 0356 * SCP_BankDelay and SCP_NextFrame 0357 * @p15_behave: Slave behavior when the Master attempts a read to the Port15 0358 * alias 0359 * @lane_control_support: Slave supports lane control 0360 * @master_count: Number of Masters present on this Slave 0361 * @source_ports: Bitmap identifying source ports 0362 * @sink_ports: Bitmap identifying sink ports 0363 * @dp0_prop: Data Port 0 properties 0364 * @src_dpn_prop: Source Data Port N properties 0365 * @sink_dpn_prop: Sink Data Port N properties 0366 * @scp_int1_mask: SCP_INT1_MASK desired settings 0367 * @quirks: bitmask identifying deltas from the MIPI specification 0368 * @is_sdca: the Slave supports the SDCA specification 0369 */ 0370 struct sdw_slave_prop { 0371 u32 mipi_revision; 0372 bool wake_capable; 0373 bool test_mode_capable; 0374 bool clk_stop_mode1; 0375 bool simple_clk_stop_capable; 0376 u32 clk_stop_timeout; 0377 u32 ch_prep_timeout; 0378 enum sdw_clk_stop_reset_behave reset_behave; 0379 bool high_PHY_capable; 0380 bool paging_support; 0381 bool bank_delay_support; 0382 enum sdw_p15_behave p15_behave; 0383 bool lane_control_support; 0384 u32 master_count; 0385 u32 source_ports; 0386 u32 sink_ports; 0387 struct sdw_dp0_prop *dp0_prop; 0388 struct sdw_dpn_prop *src_dpn_prop; 0389 struct sdw_dpn_prop *sink_dpn_prop; 0390 u8 scp_int1_mask; 0391 u32 quirks; 0392 bool is_sdca; 0393 }; 0394 0395 #define SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY BIT(0) 0396 0397 /** 0398 * struct sdw_master_prop - Master properties 0399 * @revision: MIPI spec version of the implementation 0400 * @clk_stop_modes: Bitmap, bit N set when clock-stop-modeN supported 0401 * @max_clk_freq: Maximum Bus clock frequency, in Hz 0402 * @num_clk_gears: Number of clock gears supported 0403 * @clk_gears: Clock gears supported 0404 * @num_clk_freq: Number of clock frequencies supported, in Hz 0405 * @clk_freq: Clock frequencies supported, in Hz 0406 * @default_frame_rate: Controller default Frame rate, in Hz 0407 * @default_row: Number of rows 0408 * @default_col: Number of columns 0409 * @dynamic_frame: Dynamic frame shape supported 0410 * @err_threshold: Number of times that software may retry sending a single 0411 * command 0412 * @mclk_freq: clock reference passed to SoundWire Master, in Hz. 0413 * @hw_disabled: if true, the Master is not functional, typically due to pin-mux 0414 * @quirks: bitmask identifying optional behavior beyond the scope of the MIPI specification 0415 */ 0416 struct sdw_master_prop { 0417 u32 revision; 0418 u32 clk_stop_modes; 0419 u32 max_clk_freq; 0420 u32 num_clk_gears; 0421 u32 *clk_gears; 0422 u32 num_clk_freq; 0423 u32 *clk_freq; 0424 u32 default_frame_rate; 0425 u32 default_row; 0426 u32 default_col; 0427 bool dynamic_frame; 0428 u32 err_threshold; 0429 u32 mclk_freq; 0430 bool hw_disabled; 0431 u64 quirks; 0432 }; 0433 0434 /* Definitions for Master quirks */ 0435 0436 /* 0437 * In a number of platforms bus clashes are reported after a hardware 0438 * reset but without any explanations or evidence of a real problem. 0439 * The following quirk will discard all initial bus clash interrupts 0440 * but will leave the detection on should real bus clashes happen 0441 */ 0442 #define SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASH BIT(0) 0443 0444 /* 0445 * Some Slave devices have known issues with incorrect parity errors 0446 * reported after a hardware reset. However during integration unexplained 0447 * parity errors can be reported by Slave devices, possibly due to electrical 0448 * issues at the Master level. 0449 * The following quirk will discard all initial parity errors but will leave 0450 * the detection on should real parity errors happen. 0451 */ 0452 #define SDW_MASTER_QUIRKS_CLEAR_INITIAL_PARITY BIT(1) 0453 0454 int sdw_master_read_prop(struct sdw_bus *bus); 0455 int sdw_slave_read_prop(struct sdw_slave *slave); 0456 0457 /* 0458 * SDW Slave Structures and APIs 0459 */ 0460 0461 #define SDW_IGNORED_UNIQUE_ID 0xFF 0462 0463 /** 0464 * struct sdw_slave_id - Slave ID 0465 * @mfg_id: MIPI Manufacturer ID 0466 * @part_id: Device Part ID 0467 * @class_id: MIPI Class ID (defined starting with SoundWire 1.2 spec) 0468 * @unique_id: Device unique ID 0469 * @sdw_version: SDW version implemented 0470 * 0471 * The order of the IDs here does not follow the DisCo spec definitions 0472 */ 0473 struct sdw_slave_id { 0474 __u16 mfg_id; 0475 __u16 part_id; 0476 __u8 class_id; 0477 __u8 unique_id; 0478 __u8 sdw_version:4; 0479 }; 0480 0481 /* 0482 * Helper macros to extract the MIPI-defined IDs 0483 * 0484 * Spec definition 0485 * Register Bit Contents 0486 * DevId_0 [7:4] 47:44 sdw_version 0487 * DevId_0 [3:0] 43:40 unique_id 0488 * DevId_1 39:32 mfg_id [15:8] 0489 * DevId_2 31:24 mfg_id [7:0] 0490 * DevId_3 23:16 part_id [15:8] 0491 * DevId_4 15:08 part_id [7:0] 0492 * DevId_5 07:00 class_id 0493 * 0494 * The MIPI DisCo for SoundWire defines in addition the link_id as bits 51:48 0495 */ 0496 #define SDW_DISCO_LINK_ID_MASK GENMASK_ULL(51, 48) 0497 #define SDW_VERSION_MASK GENMASK_ULL(47, 44) 0498 #define SDW_UNIQUE_ID_MASK GENMASK_ULL(43, 40) 0499 #define SDW_MFG_ID_MASK GENMASK_ULL(39, 24) 0500 #define SDW_PART_ID_MASK GENMASK_ULL(23, 8) 0501 #define SDW_CLASS_ID_MASK GENMASK_ULL(7, 0) 0502 0503 #define SDW_DISCO_LINK_ID(addr) FIELD_GET(SDW_DISCO_LINK_ID_MASK, addr) 0504 #define SDW_VERSION(addr) FIELD_GET(SDW_VERSION_MASK, addr) 0505 #define SDW_UNIQUE_ID(addr) FIELD_GET(SDW_UNIQUE_ID_MASK, addr) 0506 #define SDW_MFG_ID(addr) FIELD_GET(SDW_MFG_ID_MASK, addr) 0507 #define SDW_PART_ID(addr) FIELD_GET(SDW_PART_ID_MASK, addr) 0508 #define SDW_CLASS_ID(addr) FIELD_GET(SDW_CLASS_ID_MASK, addr) 0509 0510 /** 0511 * struct sdw_slave_intr_status - Slave interrupt status 0512 * @sdca_cascade: set if the Slave device reports an SDCA interrupt 0513 * @control_port: control port status 0514 * @port: data port status 0515 */ 0516 struct sdw_slave_intr_status { 0517 bool sdca_cascade; 0518 u8 control_port; 0519 u8 port[15]; 0520 }; 0521 0522 /** 0523 * sdw_reg_bank - SoundWire register banks 0524 * @SDW_BANK0: Soundwire register bank 0 0525 * @SDW_BANK1: Soundwire register bank 1 0526 */ 0527 enum sdw_reg_bank { 0528 SDW_BANK0, 0529 SDW_BANK1, 0530 }; 0531 0532 /** 0533 * struct sdw_bus_conf: Bus configuration 0534 * 0535 * @clk_freq: Clock frequency, in Hz 0536 * @num_rows: Number of rows in frame 0537 * @num_cols: Number of columns in frame 0538 * @bank: Next register bank 0539 */ 0540 struct sdw_bus_conf { 0541 unsigned int clk_freq; 0542 unsigned int num_rows; 0543 unsigned int num_cols; 0544 unsigned int bank; 0545 }; 0546 0547 /** 0548 * struct sdw_prepare_ch: Prepare/De-prepare Data Port channel 0549 * 0550 * @num: Port number 0551 * @ch_mask: Active channel mask 0552 * @prepare: Prepare (true) /de-prepare (false) channel 0553 * @bank: Register bank, which bank Slave/Master driver should program for 0554 * implementation defined registers. This is always updated to next_bank 0555 * value read from bus params. 0556 * 0557 */ 0558 struct sdw_prepare_ch { 0559 unsigned int num; 0560 unsigned int ch_mask; 0561 bool prepare; 0562 unsigned int bank; 0563 }; 0564 0565 /** 0566 * enum sdw_port_prep_ops: Prepare operations for Data Port 0567 * 0568 * @SDW_OPS_PORT_PRE_PREP: Pre prepare operation for the Port 0569 * @SDW_OPS_PORT_PREP: Prepare operation for the Port 0570 * @SDW_OPS_PORT_POST_PREP: Post prepare operation for the Port 0571 */ 0572 enum sdw_port_prep_ops { 0573 SDW_OPS_PORT_PRE_PREP = 0, 0574 SDW_OPS_PORT_PREP = 1, 0575 SDW_OPS_PORT_POST_PREP = 2, 0576 }; 0577 0578 /** 0579 * struct sdw_bus_params: Structure holding bus configuration 0580 * 0581 * @curr_bank: Current bank in use (BANK0/BANK1) 0582 * @next_bank: Next bank to use (BANK0/BANK1). next_bank will always be 0583 * set to !curr_bank 0584 * @max_dr_freq: Maximum double rate clock frequency supported, in Hz 0585 * @curr_dr_freq: Current double rate clock frequency, in Hz 0586 * @bandwidth: Current bandwidth 0587 * @col: Active columns 0588 * @row: Active rows 0589 * @s_data_mode: NORMAL, STATIC or PRBS mode for all Slave ports 0590 * @m_data_mode: NORMAL, STATIC or PRBS mode for all Master ports. The value 0591 * should be the same to detect transmission issues, but can be different to 0592 * test the interrupt reports 0593 */ 0594 struct sdw_bus_params { 0595 enum sdw_reg_bank curr_bank; 0596 enum sdw_reg_bank next_bank; 0597 unsigned int max_dr_freq; 0598 unsigned int curr_dr_freq; 0599 unsigned int bandwidth; 0600 unsigned int col; 0601 unsigned int row; 0602 int s_data_mode; 0603 int m_data_mode; 0604 }; 0605 0606 /** 0607 * struct sdw_slave_ops: Slave driver callback ops 0608 * 0609 * @read_prop: Read Slave properties 0610 * @interrupt_callback: Device interrupt notification (invoked in thread 0611 * context) 0612 * @update_status: Update Slave status 0613 * @bus_config: Update the bus config for Slave 0614 * @port_prep: Prepare the port with parameters 0615 * @clk_stop: handle imp-def sequences before and after prepare and de-prepare 0616 */ 0617 struct sdw_slave_ops { 0618 int (*read_prop)(struct sdw_slave *sdw); 0619 int (*interrupt_callback)(struct sdw_slave *slave, 0620 struct sdw_slave_intr_status *status); 0621 int (*update_status)(struct sdw_slave *slave, 0622 enum sdw_slave_status status); 0623 int (*bus_config)(struct sdw_slave *slave, 0624 struct sdw_bus_params *params); 0625 int (*port_prep)(struct sdw_slave *slave, 0626 struct sdw_prepare_ch *prepare_ch, 0627 enum sdw_port_prep_ops pre_ops); 0628 int (*clk_stop)(struct sdw_slave *slave, 0629 enum sdw_clk_stop_mode mode, 0630 enum sdw_clk_stop_type type); 0631 0632 }; 0633 0634 /** 0635 * struct sdw_slave - SoundWire Slave 0636 * @id: MIPI device ID 0637 * @dev: Linux device 0638 * @status: Status reported by the Slave 0639 * @bus: Bus handle 0640 * @prop: Slave properties 0641 * @debugfs: Slave debugfs 0642 * @node: node for bus list 0643 * @port_ready: Port ready completion flag for each Slave port 0644 * @m_port_map: static Master port map for each Slave port 0645 * @dev_num: Current Device Number, values can be 0 or dev_num_sticky 0646 * @dev_num_sticky: one-time static Device Number assigned by Bus 0647 * @probed: boolean tracking driver state 0648 * @enumeration_complete: completion utility to control potential races 0649 * on startup between device enumeration and read/write access to the 0650 * Slave device 0651 * @initialization_complete: completion utility to control potential races 0652 * on startup between device enumeration and settings being restored 0653 * @unattach_request: mask field to keep track why the Slave re-attached and 0654 * was re-initialized. This is useful to deal with potential race conditions 0655 * between the Master suspending and the codec resuming, and make sure that 0656 * when the Master triggered a reset the Slave is properly enumerated and 0657 * initialized 0658 * @first_interrupt_done: status flag tracking if the interrupt handling 0659 * for a Slave happens for the first time after enumeration 0660 * @is_mockup_device: status flag used to squelch errors in the command/control 0661 * protocol for SoundWire mockup devices 0662 * @sdw_dev_lock: mutex used to protect callbacks/remove races 0663 */ 0664 struct sdw_slave { 0665 struct sdw_slave_id id; 0666 struct device dev; 0667 enum sdw_slave_status status; 0668 struct sdw_bus *bus; 0669 struct sdw_slave_prop prop; 0670 #ifdef CONFIG_DEBUG_FS 0671 struct dentry *debugfs; 0672 #endif 0673 struct list_head node; 0674 struct completion port_ready[SDW_MAX_PORTS]; 0675 unsigned int m_port_map[SDW_MAX_PORTS]; 0676 u16 dev_num; 0677 u16 dev_num_sticky; 0678 bool probed; 0679 struct completion enumeration_complete; 0680 struct completion initialization_complete; 0681 u32 unattach_request; 0682 bool first_interrupt_done; 0683 bool is_mockup_device; 0684 struct mutex sdw_dev_lock; /* protect callbacks/remove races */ 0685 }; 0686 0687 #define dev_to_sdw_dev(_dev) container_of(_dev, struct sdw_slave, dev) 0688 0689 /** 0690 * struct sdw_master_device - SoundWire 'Master Device' representation 0691 * @dev: Linux device for this Master 0692 * @bus: Bus handle shortcut 0693 */ 0694 struct sdw_master_device { 0695 struct device dev; 0696 struct sdw_bus *bus; 0697 }; 0698 0699 #define dev_to_sdw_master_device(d) \ 0700 container_of(d, struct sdw_master_device, dev) 0701 0702 struct sdw_driver { 0703 const char *name; 0704 0705 int (*probe)(struct sdw_slave *sdw, 0706 const struct sdw_device_id *id); 0707 int (*remove)(struct sdw_slave *sdw); 0708 void (*shutdown)(struct sdw_slave *sdw); 0709 0710 const struct sdw_device_id *id_table; 0711 const struct sdw_slave_ops *ops; 0712 0713 struct device_driver driver; 0714 }; 0715 0716 #define SDW_SLAVE_ENTRY_EXT(_mfg_id, _part_id, _version, _c_id, _drv_data) \ 0717 { .mfg_id = (_mfg_id), .part_id = (_part_id), \ 0718 .sdw_version = (_version), .class_id = (_c_id), \ 0719 .driver_data = (unsigned long)(_drv_data) } 0720 0721 #define SDW_SLAVE_ENTRY(_mfg_id, _part_id, _drv_data) \ 0722 SDW_SLAVE_ENTRY_EXT((_mfg_id), (_part_id), 0, 0, (_drv_data)) 0723 0724 int sdw_handle_slave_status(struct sdw_bus *bus, 0725 enum sdw_slave_status status[]); 0726 0727 /* 0728 * SDW master structures and APIs 0729 */ 0730 0731 /** 0732 * struct sdw_port_params: Data Port parameters 0733 * 0734 * @num: Port number 0735 * @bps: Word length of the Port 0736 * @flow_mode: Port Data flow mode 0737 * @data_mode: Test modes or normal mode 0738 * 0739 * This is used to program the Data Port based on Data Port stream 0740 * parameters. 0741 */ 0742 struct sdw_port_params { 0743 unsigned int num; 0744 unsigned int bps; 0745 unsigned int flow_mode; 0746 unsigned int data_mode; 0747 }; 0748 0749 /** 0750 * struct sdw_transport_params: Data Port Transport Parameters 0751 * 0752 * @blk_grp_ctrl_valid: Port implements block group control 0753 * @num: Port number 0754 * @blk_grp_ctrl: Block group control value 0755 * @sample_interval: Sample interval 0756 * @offset1: Blockoffset of the payload data 0757 * @offset2: Blockoffset of the payload data 0758 * @hstart: Horizontal start of the payload data 0759 * @hstop: Horizontal stop of the payload data 0760 * @blk_pkg_mode: Block per channel or block per port 0761 * @lane_ctrl: Data lane Port uses for Data transfer. Currently only single 0762 * data lane is supported in bus 0763 * 0764 * This is used to program the Data Port based on Data Port transport 0765 * parameters. All these parameters are banked and can be modified 0766 * during a bank switch without any artifacts in audio stream. 0767 */ 0768 struct sdw_transport_params { 0769 bool blk_grp_ctrl_valid; 0770 unsigned int port_num; 0771 unsigned int blk_grp_ctrl; 0772 unsigned int sample_interval; 0773 unsigned int offset1; 0774 unsigned int offset2; 0775 unsigned int hstart; 0776 unsigned int hstop; 0777 unsigned int blk_pkg_mode; 0778 unsigned int lane_ctrl; 0779 }; 0780 0781 /** 0782 * struct sdw_enable_ch: Enable/disable Data Port channel 0783 * 0784 * @num: Port number 0785 * @ch_mask: Active channel mask 0786 * @enable: Enable (true) /disable (false) channel 0787 */ 0788 struct sdw_enable_ch { 0789 unsigned int port_num; 0790 unsigned int ch_mask; 0791 bool enable; 0792 }; 0793 0794 /** 0795 * struct sdw_master_port_ops: Callback functions from bus to Master 0796 * driver to set Master Data ports. 0797 * 0798 * @dpn_set_port_params: Set the Port parameters for the Master Port. 0799 * Mandatory callback 0800 * @dpn_set_port_transport_params: Set transport parameters for the Master 0801 * Port. Mandatory callback 0802 * @dpn_port_prep: Port prepare operations for the Master Data Port. 0803 * @dpn_port_enable_ch: Enable the channels of Master Port. 0804 */ 0805 struct sdw_master_port_ops { 0806 int (*dpn_set_port_params)(struct sdw_bus *bus, 0807 struct sdw_port_params *port_params, 0808 unsigned int bank); 0809 int (*dpn_set_port_transport_params)(struct sdw_bus *bus, 0810 struct sdw_transport_params *transport_params, 0811 enum sdw_reg_bank bank); 0812 int (*dpn_port_prep)(struct sdw_bus *bus, 0813 struct sdw_prepare_ch *prepare_ch); 0814 int (*dpn_port_enable_ch)(struct sdw_bus *bus, 0815 struct sdw_enable_ch *enable_ch, unsigned int bank); 0816 }; 0817 0818 struct sdw_msg; 0819 0820 /** 0821 * struct sdw_defer - SDW deffered message 0822 * @length: message length 0823 * @complete: message completion 0824 * @msg: SDW message 0825 */ 0826 struct sdw_defer { 0827 int length; 0828 struct completion complete; 0829 struct sdw_msg *msg; 0830 }; 0831 0832 /** 0833 * struct sdw_master_ops - Master driver ops 0834 * @read_prop: Read Master properties 0835 * @override_adr: Override value read from firmware (quirk for buggy firmware) 0836 * @xfer_msg: Transfer message callback 0837 * @xfer_msg_defer: Defer version of transfer message callback 0838 * @reset_page_addr: Reset the SCP page address registers 0839 * @set_bus_conf: Set the bus configuration 0840 * @pre_bank_switch: Callback for pre bank switch 0841 * @post_bank_switch: Callback for post bank switch 0842 */ 0843 struct sdw_master_ops { 0844 int (*read_prop)(struct sdw_bus *bus); 0845 u64 (*override_adr) 0846 (struct sdw_bus *bus, u64 addr); 0847 enum sdw_command_response (*xfer_msg) 0848 (struct sdw_bus *bus, struct sdw_msg *msg); 0849 enum sdw_command_response (*xfer_msg_defer) 0850 (struct sdw_bus *bus, struct sdw_msg *msg, 0851 struct sdw_defer *defer); 0852 enum sdw_command_response (*reset_page_addr) 0853 (struct sdw_bus *bus, unsigned int dev_num); 0854 int (*set_bus_conf)(struct sdw_bus *bus, 0855 struct sdw_bus_params *params); 0856 int (*pre_bank_switch)(struct sdw_bus *bus); 0857 int (*post_bank_switch)(struct sdw_bus *bus); 0858 0859 }; 0860 0861 /** 0862 * struct sdw_bus - SoundWire bus 0863 * @dev: Shortcut to &bus->md->dev to avoid changing the entire code. 0864 * @md: Master device 0865 * @link_id: Link id number, can be 0 to N, unique for each Master 0866 * @id: bus system-wide unique id 0867 * @slaves: list of Slaves on this bus 0868 * @assigned: Bitmap for Slave device numbers. 0869 * Bit set implies used number, bit clear implies unused number. 0870 * @bus_lock: bus lock 0871 * @msg_lock: message lock 0872 * @compute_params: points to Bus resource management implementation 0873 * @ops: Master callback ops 0874 * @port_ops: Master port callback ops 0875 * @params: Current bus parameters 0876 * @prop: Master properties 0877 * @m_rt_list: List of Master instance of all stream(s) running on Bus. This 0878 * is used to compute and program bus bandwidth, clock, frame shape, 0879 * transport and port parameters 0880 * @debugfs: Bus debugfs 0881 * @defer_msg: Defer message 0882 * @clk_stop_timeout: Clock stop timeout computed 0883 * @bank_switch_timeout: Bank switch timeout computed 0884 * @multi_link: Store bus property that indicates if multi links 0885 * are supported. This flag is populated by drivers after reading 0886 * appropriate firmware (ACPI/DT). 0887 * @hw_sync_min_links: Number of links used by a stream above which 0888 * hardware-based synchronization is required. This value is only 0889 * meaningful if multi_link is set. If set to 1, hardware-based 0890 * synchronization will be used even if a stream only uses a single 0891 * SoundWire segment. 0892 */ 0893 struct sdw_bus { 0894 struct device *dev; 0895 struct sdw_master_device *md; 0896 unsigned int link_id; 0897 int id; 0898 struct list_head slaves; 0899 DECLARE_BITMAP(assigned, SDW_MAX_DEVICES); 0900 struct mutex bus_lock; 0901 struct mutex msg_lock; 0902 int (*compute_params)(struct sdw_bus *bus); 0903 const struct sdw_master_ops *ops; 0904 const struct sdw_master_port_ops *port_ops; 0905 struct sdw_bus_params params; 0906 struct sdw_master_prop prop; 0907 struct list_head m_rt_list; 0908 #ifdef CONFIG_DEBUG_FS 0909 struct dentry *debugfs; 0910 #endif 0911 struct sdw_defer defer_msg; 0912 unsigned int clk_stop_timeout; 0913 u32 bank_switch_timeout; 0914 bool multi_link; 0915 int hw_sync_min_links; 0916 }; 0917 0918 int sdw_bus_master_add(struct sdw_bus *bus, struct device *parent, 0919 struct fwnode_handle *fwnode); 0920 void sdw_bus_master_delete(struct sdw_bus *bus); 0921 0922 /** 0923 * sdw_port_config: Master or Slave Port configuration 0924 * 0925 * @num: Port number 0926 * @ch_mask: channels mask for port 0927 */ 0928 struct sdw_port_config { 0929 unsigned int num; 0930 unsigned int ch_mask; 0931 }; 0932 0933 /** 0934 * sdw_stream_config: Master or Slave stream configuration 0935 * 0936 * @frame_rate: Audio frame rate of the stream, in Hz 0937 * @ch_count: Channel count of the stream 0938 * @bps: Number of bits per audio sample 0939 * @direction: Data direction 0940 * @type: Stream type PCM or PDM 0941 */ 0942 struct sdw_stream_config { 0943 unsigned int frame_rate; 0944 unsigned int ch_count; 0945 unsigned int bps; 0946 enum sdw_data_direction direction; 0947 enum sdw_stream_type type; 0948 }; 0949 0950 /** 0951 * sdw_stream_state: Stream states 0952 * 0953 * @SDW_STREAM_ALLOCATED: New stream allocated. 0954 * @SDW_STREAM_CONFIGURED: Stream configured 0955 * @SDW_STREAM_PREPARED: Stream prepared 0956 * @SDW_STREAM_ENABLED: Stream enabled 0957 * @SDW_STREAM_DISABLED: Stream disabled 0958 * @SDW_STREAM_DEPREPARED: Stream de-prepared 0959 * @SDW_STREAM_RELEASED: Stream released 0960 */ 0961 enum sdw_stream_state { 0962 SDW_STREAM_ALLOCATED = 0, 0963 SDW_STREAM_CONFIGURED = 1, 0964 SDW_STREAM_PREPARED = 2, 0965 SDW_STREAM_ENABLED = 3, 0966 SDW_STREAM_DISABLED = 4, 0967 SDW_STREAM_DEPREPARED = 5, 0968 SDW_STREAM_RELEASED = 6, 0969 }; 0970 0971 /** 0972 * sdw_stream_params: Stream parameters 0973 * 0974 * @rate: Sampling frequency, in Hz 0975 * @ch_count: Number of channels 0976 * @bps: bits per channel sample 0977 */ 0978 struct sdw_stream_params { 0979 unsigned int rate; 0980 unsigned int ch_count; 0981 unsigned int bps; 0982 }; 0983 0984 /** 0985 * sdw_stream_runtime: Runtime stream parameters 0986 * 0987 * @name: SoundWire stream name 0988 * @params: Stream parameters 0989 * @state: Current state of the stream 0990 * @type: Stream type PCM or PDM 0991 * @master_list: List of Master runtime(s) in this stream. 0992 * master_list can contain only one m_rt per Master instance 0993 * for a stream 0994 * @m_rt_count: Count of Master runtime(s) in this stream 0995 */ 0996 struct sdw_stream_runtime { 0997 const char *name; 0998 struct sdw_stream_params params; 0999 enum sdw_stream_state state; 1000 enum sdw_stream_type type; 1001 struct list_head master_list; 1002 int m_rt_count; 1003 }; 1004 1005 struct sdw_stream_runtime *sdw_alloc_stream(const char *stream_name); 1006 void sdw_release_stream(struct sdw_stream_runtime *stream); 1007 1008 int sdw_compute_params(struct sdw_bus *bus); 1009 1010 int sdw_stream_add_master(struct sdw_bus *bus, 1011 struct sdw_stream_config *stream_config, 1012 struct sdw_port_config *port_config, 1013 unsigned int num_ports, 1014 struct sdw_stream_runtime *stream); 1015 int sdw_stream_add_slave(struct sdw_slave *slave, 1016 struct sdw_stream_config *stream_config, 1017 struct sdw_port_config *port_config, 1018 unsigned int num_ports, 1019 struct sdw_stream_runtime *stream); 1020 int sdw_stream_remove_master(struct sdw_bus *bus, 1021 struct sdw_stream_runtime *stream); 1022 int sdw_stream_remove_slave(struct sdw_slave *slave, 1023 struct sdw_stream_runtime *stream); 1024 int sdw_startup_stream(void *sdw_substream); 1025 int sdw_prepare_stream(struct sdw_stream_runtime *stream); 1026 int sdw_enable_stream(struct sdw_stream_runtime *stream); 1027 int sdw_disable_stream(struct sdw_stream_runtime *stream); 1028 int sdw_deprepare_stream(struct sdw_stream_runtime *stream); 1029 void sdw_shutdown_stream(void *sdw_substream); 1030 int sdw_bus_prep_clk_stop(struct sdw_bus *bus); 1031 int sdw_bus_clk_stop(struct sdw_bus *bus); 1032 int sdw_bus_exit_clk_stop(struct sdw_bus *bus); 1033 1034 /* messaging and data APIs */ 1035 1036 int sdw_read(struct sdw_slave *slave, u32 addr); 1037 int sdw_write(struct sdw_slave *slave, u32 addr, u8 value); 1038 int sdw_write_no_pm(struct sdw_slave *slave, u32 addr, u8 value); 1039 int sdw_read_no_pm(struct sdw_slave *slave, u32 addr); 1040 int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val); 1041 int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val); 1042 int sdw_update(struct sdw_slave *slave, u32 addr, u8 mask, u8 val); 1043 int sdw_update_no_pm(struct sdw_slave *slave, u32 addr, u8 mask, u8 val); 1044 1045 int sdw_compare_devid(struct sdw_slave *slave, struct sdw_slave_id id); 1046 void sdw_extract_slave_id(struct sdw_bus *bus, u64 addr, struct sdw_slave_id *id); 1047 1048 #endif /* __SOUNDWIRE_H */
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