soc/ti/ti_sci_protocol.h

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Texas Instruments System Control Interface Protocol
0004  *
0005  * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
0006  *  Nishanth Menon
0007  */
0008
0009 #ifndef __TISCI_PROTOCOL_H
0010 #define __TISCI_PROTOCOL_H
0011
0012 /**
0013  * struct ti_sci_version_info - version information structure
0014  * @abi_major:  Major ABI version. Change here implies risk of backward
0015  *      compatibility break.
0016  * @abi_minor:  Minor ABI version. Change here implies new feature addition,
0017  *      or compatible change in ABI.
0018  * @firmware_revision:  Firmware revision (not usually used).
0019  * @firmware_description: Firmware description (not usually used).
0020  */
0021 struct ti_sci_version_info {
0022     u8 abi_major;
0023     u8 abi_minor;
0024     u16 firmware_revision;
0025     char firmware_description[32];
0026 };
0027
0028 struct ti_sci_handle;
0029
0030 /**
0031  * struct ti_sci_core_ops - SoC Core Operations
0032  * @reboot_device: Reboot the SoC
0033  *      Returns 0 for successful request(ideally should never return),
0034  *      else returns corresponding error value.
0035  */
0036 struct ti_sci_core_ops {
0037     int (*reboot_device)(const struct ti_sci_handle *handle);
0038 };
0039
0040 /**
0041  * struct ti_sci_dev_ops - Device control operations
0042  * @get_device: Command to request for device managed by TISCI
0043  *      Returns 0 for successful exclusive request, else returns
0044  *      corresponding error message.
0045  * @idle_device: Command to idle a device managed by TISCI
0046  *      Returns 0 for successful exclusive request, else returns
0047  *      corresponding error message.
0048  * @put_device: Command to release a device managed by TISCI
0049  *      Returns 0 for successful release, else returns corresponding
0050  *      error message.
0051  * @is_valid:   Check if the device ID is a valid ID.
0052  *      Returns 0 if the ID is valid, else returns corresponding error.
0053  * @get_context_loss_count: Command to retrieve context loss counter - this
0054  *      increments every time the device looses context. Overflow
0055  *      is possible.
0056  *      - count: pointer to u32 which will retrieve counter
0057  *      Returns 0 for successful information request and count has
0058  *      proper data, else returns corresponding error message.
0059  * @is_idle:    Reports back about device idle state
0060  *      - req_state: Returns requested idle state
0061  *      Returns 0 for successful information request and req_state and
0062  *      current_state has proper data, else returns corresponding error
0063  *      message.
0064  * @is_stop:    Reports back about device stop state
0065  *      - req_state: Returns requested stop state
0066  *      - current_state: Returns current stop state
0067  *      Returns 0 for successful information request and req_state and
0068  *      current_state has proper data, else returns corresponding error
0069  *      message.
0070  * @is_on:  Reports back about device ON(or active) state
0071  *      - req_state: Returns requested ON state
0072  *      - current_state: Returns current ON state
0073  *      Returns 0 for successful information request and req_state and
0074  *      current_state has proper data, else returns corresponding error
0075  *      message.
0076  * @is_transitioning: Reports back if the device is in the middle of transition
0077  *      of state.
0078  *      -current_state: Returns 'true' if currently transitioning.
0079  * @set_device_resets: Command to configure resets for device managed by TISCI.
0080  *      -reset_state: Device specific reset bit field
0081  *      Returns 0 for successful request, else returns
0082  *      corresponding error message.
0083  * @get_device_resets: Command to read state of resets for device managed
0084  *      by TISCI.
0085  *      -reset_state: pointer to u32 which will retrieve resets
0086  *      Returns 0 for successful request, else returns
0087  *      corresponding error message.
0088  *
0089  * NOTE: for all these functions, the following parameters are generic in
0090  * nature:
0091  * -handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
0092  * -id:     Device Identifier
0093  *
0094  * Request for the device - NOTE: the client MUST maintain integrity of
0095  * usage count by balancing get_device with put_device. No refcounting is
0096  * managed by driver for that purpose.
0097  */
0098 struct ti_sci_dev_ops {
0099     int (*get_device)(const struct ti_sci_handle *handle, u32 id);
0100     int (*get_device_exclusive)(const struct ti_sci_handle *handle, u32 id);
0101     int (*idle_device)(const struct ti_sci_handle *handle, u32 id);
0102     int (*idle_device_exclusive)(const struct ti_sci_handle *handle,
0103                      u32 id);
0104     int (*put_device)(const struct ti_sci_handle *handle, u32 id);
0105     int (*is_valid)(const struct ti_sci_handle *handle, u32 id);
0106     int (*get_context_loss_count)(const struct ti_sci_handle *handle,
0107                       u32 id, u32 *count);
0108     int (*is_idle)(const struct ti_sci_handle *handle, u32 id,
0109                bool *requested_state);
0110     int (*is_stop)(const struct ti_sci_handle *handle, u32 id,
0111                bool *req_state, bool *current_state);
0112     int (*is_on)(const struct ti_sci_handle *handle, u32 id,
0113              bool *req_state, bool *current_state);
0114     int (*is_transitioning)(const struct ti_sci_handle *handle, u32 id,
0115                 bool *current_state);
0116     int (*set_device_resets)(const struct ti_sci_handle *handle, u32 id,
0117                  u32 reset_state);
0118     int (*get_device_resets)(const struct ti_sci_handle *handle, u32 id,
0119                  u32 *reset_state);
0120 };
0121
0122 /**
0123  * struct ti_sci_clk_ops - Clock control operations
0124  * @get_clock:  Request for activation of clock and manage by processor
0125  *      - needs_ssc: 'true' if Spread Spectrum clock is desired.
0126  *      - can_change_freq: 'true' if frequency change is desired.
0127  *      - enable_input_term: 'true' if input termination is desired.
0128  * @idle_clock: Request for Idling a clock managed by processor
0129  * @put_clock:  Release the clock to be auto managed by TISCI
0130  * @is_auto:    Is the clock being auto managed
0131  *      - req_state: state indicating if the clock is auto managed
0132  * @is_on:  Is the clock ON
0133  *      - req_state: if the clock is requested to be forced ON
0134  *      - current_state: if the clock is currently ON
0135  * @is_off: Is the clock OFF
0136  *      - req_state: if the clock is requested to be forced OFF
0137  *      - current_state: if the clock is currently Gated
0138  * @set_parent: Set the clock source of a specific device clock
0139  *      - parent_id: Parent clock identifier to set.
0140  * @get_parent: Get the current clock source of a specific device clock
0141  *      - parent_id: Parent clock identifier which is the parent.
0142  * @get_num_parents: Get the number of parents of the current clock source
0143  *      - num_parents: returns the number of parent clocks.
0144  * @get_best_match_freq: Find a best matching frequency for a frequency
0145  *      range.
0146  *      - match_freq: Best matching frequency in Hz.
0147  * @set_freq:   Set the Clock frequency
0148  * @get_freq:   Get the Clock frequency
0149  *      - current_freq: Frequency in Hz that the clock is at.
0150  *
0151  * NOTE: for all these functions, the following parameters are generic in
0152  * nature:
0153  * -handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
0154  * -did:    Device identifier this request is for
0155  * -cid:    Clock identifier for the device for this request.
0156  *      Each device has it's own set of clock inputs. This indexes
0157  *      which clock input to modify.
0158  * -min_freq:   The minimum allowable frequency in Hz. This is the minimum
0159  *      allowable programmed frequency and does not account for clock
0160  *      tolerances and jitter.
0161  * -target_freq: The target clock frequency in Hz. A frequency will be
0162  *      processed as close to this target frequency as possible.
0163  * -max_freq:   The maximum allowable frequency in Hz. This is the maximum
0164  *      allowable programmed frequency and does not account for clock
0165  *      tolerances and jitter.
0166  *
0167  * Request for the clock - NOTE: the client MUST maintain integrity of
0168  * usage count by balancing get_clock with put_clock. No refcounting is
0169  * managed by driver for that purpose.
0170  */
0171 struct ti_sci_clk_ops {
0172     int (*get_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid,
0173              bool needs_ssc, bool can_change_freq,
0174              bool enable_input_term);
0175     int (*idle_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid);
0176     int (*put_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid);
0177     int (*is_auto)(const struct ti_sci_handle *handle, u32 did, u32 cid,
0178                bool *req_state);
0179     int (*is_on)(const struct ti_sci_handle *handle, u32 did, u32 cid,
0180              bool *req_state, bool *current_state);
0181     int (*is_off)(const struct ti_sci_handle *handle, u32 did, u32 cid,
0182               bool *req_state, bool *current_state);
0183     int (*set_parent)(const struct ti_sci_handle *handle, u32 did, u32 cid,
0184               u32 parent_id);
0185     int (*get_parent)(const struct ti_sci_handle *handle, u32 did, u32 cid,
0186               u32 *parent_id);
0187     int (*get_num_parents)(const struct ti_sci_handle *handle, u32 did,
0188                    u32 cid, u32 *num_parents);
0189     int (*get_best_match_freq)(const struct ti_sci_handle *handle, u32 did,
0190                    u32 cid, u64 min_freq, u64 target_freq,
0191                    u64 max_freq, u64 *match_freq);
0192     int (*set_freq)(const struct ti_sci_handle *handle, u32 did, u32 cid,
0193             u64 min_freq, u64 target_freq, u64 max_freq);
0194     int (*get_freq)(const struct ti_sci_handle *handle, u32 did, u32 cid,
0195             u64 *current_freq);
0196 };
0197
0198 /**
0199  * struct ti_sci_resource_desc - Description of TI SCI resource instance range.
0200  * @start:  Start index of the first resource range.
0201  * @num:    Number of resources in the first range.
0202  * @start_sec:  Start index of the second resource range.
0203  * @num_sec:    Number of resources in the second range.
0204  * @res_map:    Bitmap to manage the allocation of these resources.
0205  */
0206 struct ti_sci_resource_desc {
0207     u16 start;
0208     u16 num;
0209     u16 start_sec;
0210     u16 num_sec;
0211     unsigned long *res_map;
0212 };
0213
0214 /**
0215  * struct ti_sci_rm_core_ops - Resource management core operations
0216  * @get_range:      Get a range of resources belonging to ti sci host.
0217  * @get_rage_from_shost:    Get a range of resources belonging to
0218  *              specified host id.
0219  *          - s_host: Host processing entity to which the
0220  *                resources are allocated
0221  *
0222  * NOTE: for these functions, all the parameters are consolidated and defined
0223  * as below:
0224  * - handle:    Pointer to TISCI handle as retrieved by *ti_sci_get_handle
0225  * - dev_id:    TISCI device ID.
0226  * - subtype:   Resource assignment subtype that is being requested
0227  *      from the given device.
0228  * - desc:  Pointer to ti_sci_resource_desc to be updated with the resource
0229  *      range start index and number of resources
0230  */
0231 struct ti_sci_rm_core_ops {
0232     int (*get_range)(const struct ti_sci_handle *handle, u32 dev_id,
0233              u8 subtype, struct ti_sci_resource_desc *desc);
0234     int (*get_range_from_shost)(const struct ti_sci_handle *handle,
0235                     u32 dev_id, u8 subtype, u8 s_host,
0236                     struct ti_sci_resource_desc *desc);
0237 };
0238
0239 #define TI_SCI_RESASG_SUBTYPE_IR_OUTPUT     0
0240 #define TI_SCI_RESASG_SUBTYPE_IA_VINT       0xa
0241 #define TI_SCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT 0xd
0242 /**
0243  * struct ti_sci_rm_irq_ops: IRQ management operations
0244  * @set_irq:        Set an IRQ route between the requested source
0245  *          and destination
0246  * @set_event_map:  Set an Event based peripheral irq to Interrupt
0247  *          Aggregator.
0248  * @free_irq:       Free an IRQ route between the requested source
0249  *          and destination.
0250  * @free_event_map: Free an event based peripheral irq to Interrupt
0251  *          Aggregator.
0252  */
0253 struct ti_sci_rm_irq_ops {
0254     int (*set_irq)(const struct ti_sci_handle *handle, u16 src_id,
0255                u16 src_index, u16 dst_id, u16 dst_host_irq);
0256     int (*set_event_map)(const struct ti_sci_handle *handle, u16 src_id,
0257                  u16 src_index, u16 ia_id, u16 vint,
0258                  u16 global_event, u8 vint_status_bit);
0259     int (*free_irq)(const struct ti_sci_handle *handle, u16 src_id,
0260             u16 src_index, u16 dst_id, u16 dst_host_irq);
0261     int (*free_event_map)(const struct ti_sci_handle *handle, u16 src_id,
0262                   u16 src_index, u16 ia_id, u16 vint,
0263                   u16 global_event, u8 vint_status_bit);
0264 };
0265
0266 /* RA config.addr_lo parameter is valid for RM ring configure TI_SCI message */
0267 #define TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID  BIT(0)
0268 /* RA config.addr_hi parameter is valid for RM ring configure TI_SCI message */
0269 #define TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID  BIT(1)
0270  /* RA config.count parameter is valid for RM ring configure TI_SCI message */
0271 #define TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID    BIT(2)
0272 /* RA config.mode parameter is valid for RM ring configure TI_SCI message */
0273 #define TI_SCI_MSG_VALUE_RM_RING_MODE_VALID BIT(3)
0274 /* RA config.size parameter is valid for RM ring configure TI_SCI message */
0275 #define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID BIT(4)
0276 /* RA config.order_id parameter is valid for RM ring configure TISCI message */
0277 #define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID BIT(5)
0278 /* RA config.virtid parameter is valid for RM ring configure TISCI message */
0279 #define TI_SCI_MSG_VALUE_RM_RING_VIRTID_VALID   BIT(6)
0280 /* RA config.asel parameter is valid for RM ring configure TISCI message */
0281 #define TI_SCI_MSG_VALUE_RM_RING_ASEL_VALID BIT(7)
0282
0283 #define TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER \
0284     (TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID | \
0285     TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID | \
0286     TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID | \
0287     TI_SCI_MSG_VALUE_RM_RING_MODE_VALID | \
0288     TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID | \
0289     TI_SCI_MSG_VALUE_RM_RING_ASEL_VALID)
0290
0291 /**
0292  * struct ti_sci_msg_rm_ring_cfg - Ring configuration
0293  *
0294  * Parameters for Navigator Subsystem ring configuration
0295  * See @ti_sci_msg_rm_ring_cfg_req
0296  */
0297 struct ti_sci_msg_rm_ring_cfg {
0298     u32 valid_params;
0299     u16 nav_id;
0300     u16 index;
0301     u32 addr_lo;
0302     u32 addr_hi;
0303     u32 count;
0304     u8 mode;
0305     u8 size;
0306     u8 order_id;
0307     u16 virtid;
0308     u8 asel;
0309 };
0310
0311 /**
0312  * struct ti_sci_rm_ringacc_ops - Ring Accelerator Management operations
0313  * @set_cfg: configure the SoC Navigator Subsystem Ring Accelerator ring
0314  */
0315 struct ti_sci_rm_ringacc_ops {
0316     int (*set_cfg)(const struct ti_sci_handle *handle,
0317                const struct ti_sci_msg_rm_ring_cfg *params);
0318 };
0319
0320 /**
0321  * struct ti_sci_rm_psil_ops - PSI-L thread operations
0322  * @pair: pair PSI-L source thread to a destination thread.
0323  *  If the src_thread is mapped to UDMA tchan, the corresponding channel's
0324  *  TCHAN_THRD_ID register is updated.
0325  *  If the dst_thread is mapped to UDMA rchan, the corresponding channel's
0326  *  RCHAN_THRD_ID register is updated.
0327  * @unpair: unpair PSI-L source thread from a destination thread.
0328  *  If the src_thread is mapped to UDMA tchan, the corresponding channel's
0329  *  TCHAN_THRD_ID register is cleared.
0330  *  If the dst_thread is mapped to UDMA rchan, the corresponding channel's
0331  *  RCHAN_THRD_ID register is cleared.
0332  */
0333 struct ti_sci_rm_psil_ops {
0334     int (*pair)(const struct ti_sci_handle *handle, u32 nav_id,
0335             u32 src_thread, u32 dst_thread);
0336     int (*unpair)(const struct ti_sci_handle *handle, u32 nav_id,
0337               u32 src_thread, u32 dst_thread);
0338 };
0339
0340 /* UDMAP channel types */
0341 #define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR      2
0342 #define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR_SB       3   /* RX only */
0343 #define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBRR     10
0344 #define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBVR     11
0345 #define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR   12
0346 #define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBVR   13
0347
0348 #define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST       0
0349 #define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO       2
0350
0351 #define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES    1
0352 #define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES   2
0353 #define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES   3
0354
0355 #define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_TCHAN      0
0356 #define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_BCHAN      1
0357
0358 /* UDMAP TX/RX channel valid_params common declarations */
0359 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID     BIT(0)
0360 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID                BIT(1)
0361 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID            BIT(2)
0362 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID           BIT(3)
0363 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID              BIT(4)
0364 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID             BIT(5)
0365 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID                  BIT(6)
0366 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID             BIT(7)
0367 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID       BIT(8)
0368 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID       BIT(14)
0369
0370 /**
0371  * Configures a Navigator Subsystem UDMAP transmit channel
0372  *
0373  * Configures a Navigator Subsystem UDMAP transmit channel registers.
0374  * See @ti_sci_msg_rm_udmap_tx_ch_cfg_req
0375  */
0376 struct ti_sci_msg_rm_udmap_tx_ch_cfg {
0377     u32 valid_params;
0378 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID        BIT(9)
0379 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID      BIT(10)
0380 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID        BIT(11)
0381 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID      BIT(12)
0382 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID            BIT(13)
0383 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID            BIT(15)
0384 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID BIT(16)
0385     u16 nav_id;
0386     u16 index;
0387     u8 tx_pause_on_err;
0388     u8 tx_filt_einfo;
0389     u8 tx_filt_pswords;
0390     u8 tx_atype;
0391     u8 tx_chan_type;
0392     u8 tx_supr_tdpkt;
0393     u16 tx_fetch_size;
0394     u8 tx_credit_count;
0395     u16 txcq_qnum;
0396     u8 tx_priority;
0397     u8 tx_qos;
0398     u8 tx_orderid;
0399     u16 fdepth;
0400     u8 tx_sched_priority;
0401     u8 tx_burst_size;
0402     u8 tx_tdtype;
0403     u8 extended_ch_type;
0404 };
0405
0406 /**
0407  * Configures a Navigator Subsystem UDMAP receive channel
0408  *
0409  * Configures a Navigator Subsystem UDMAP receive channel registers.
0410  * See @ti_sci_msg_rm_udmap_rx_ch_cfg_req
0411  */
0412 struct ti_sci_msg_rm_udmap_rx_ch_cfg {
0413     u32 valid_params;
0414 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID      BIT(9)
0415 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID        BIT(10)
0416 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID      BIT(11)
0417 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID       BIT(12)
0418     u16 nav_id;
0419     u16 index;
0420     u16 rx_fetch_size;
0421     u16 rxcq_qnum;
0422     u8 rx_priority;
0423     u8 rx_qos;
0424     u8 rx_orderid;
0425     u8 rx_sched_priority;
0426     u16 flowid_start;
0427     u16 flowid_cnt;
0428     u8 rx_pause_on_err;
0429     u8 rx_atype;
0430     u8 rx_chan_type;
0431     u8 rx_ignore_short;
0432     u8 rx_ignore_long;
0433     u8 rx_burst_size;
0434 };
0435
0436 /**
0437  * Configures a Navigator Subsystem UDMAP receive flow
0438  *
0439  * Configures a Navigator Subsystem UDMAP receive flow's registers.
0440  * See @tis_ci_msg_rm_udmap_flow_cfg_req
0441  */
0442 struct ti_sci_msg_rm_udmap_flow_cfg {
0443     u32 valid_params;
0444 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID  BIT(0)
0445 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID     BIT(1)
0446 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID     BIT(2)
0447 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID          BIT(3)
0448 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID         BIT(4)
0449 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID          BIT(5)
0450 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID         BIT(6)
0451 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID         BIT(7)
0452 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID        BIT(8)
0453 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID        BIT(9)
0454 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID     BIT(10)
0455 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID     BIT(11)
0456 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID    BIT(12)
0457 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID    BIT(13)
0458 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID      BIT(14)
0459 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID          BIT(15)
0460 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID          BIT(16)
0461 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID          BIT(17)
0462 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID        BIT(18)
0463     u16 nav_id;
0464     u16 flow_index;
0465     u8 rx_einfo_present;
0466     u8 rx_psinfo_present;
0467     u8 rx_error_handling;
0468     u8 rx_desc_type;
0469     u16 rx_sop_offset;
0470     u16 rx_dest_qnum;
0471     u8 rx_src_tag_hi;
0472     u8 rx_src_tag_lo;
0473     u8 rx_dest_tag_hi;
0474     u8 rx_dest_tag_lo;
0475     u8 rx_src_tag_hi_sel;
0476     u8 rx_src_tag_lo_sel;
0477     u8 rx_dest_tag_hi_sel;
0478     u8 rx_dest_tag_lo_sel;
0479     u16 rx_fdq0_sz0_qnum;
0480     u16 rx_fdq1_qnum;
0481     u16 rx_fdq2_qnum;
0482     u16 rx_fdq3_qnum;
0483     u8 rx_ps_location;
0484 };
0485
0486 /**
0487  * struct ti_sci_rm_udmap_ops - UDMA Management operations
0488  * @tx_ch_cfg: configure SoC Navigator Subsystem UDMA transmit channel.
0489  * @rx_ch_cfg: configure SoC Navigator Subsystem UDMA receive channel.
0490  * @rx_flow_cfg1: configure SoC Navigator Subsystem UDMA receive flow.
0491  */
0492 struct ti_sci_rm_udmap_ops {
0493     int (*tx_ch_cfg)(const struct ti_sci_handle *handle,
0494              const struct ti_sci_msg_rm_udmap_tx_ch_cfg *params);
0495     int (*rx_ch_cfg)(const struct ti_sci_handle *handle,
0496              const struct ti_sci_msg_rm_udmap_rx_ch_cfg *params);
0497     int (*rx_flow_cfg)(const struct ti_sci_handle *handle,
0498                const struct ti_sci_msg_rm_udmap_flow_cfg *params);
0499 };
0500
0501 /**
0502  * struct ti_sci_proc_ops - Processor Control operations
0503  * @request:    Request to control a physical processor. The requesting host
0504  *      should be in the processor access list
0505  * @release:    Relinquish a physical processor control
0506  * @handover:   Handover a physical processor control to another host
0507  *      in the permitted list
0508  * @set_config: Set base configuration of a processor
0509  * @set_control: Setup limited control flags in specific cases
0510  * @get_status: Get the state of physical processor
0511  *
0512  * NOTE: The following paramteres are generic in nature for all these ops,
0513  * -handle: Pointer to TI SCI handle as retrieved by *ti_sci_get_handle
0514  * -pid:    Processor ID
0515  * -hid:    Host ID
0516  */
0517 struct ti_sci_proc_ops {
0518     int (*request)(const struct ti_sci_handle *handle, u8 pid);
0519     int (*release)(const struct ti_sci_handle *handle, u8 pid);
0520     int (*handover)(const struct ti_sci_handle *handle, u8 pid, u8 hid);
0521     int (*set_config)(const struct ti_sci_handle *handle, u8 pid,
0522               u64 boot_vector, u32 cfg_set, u32 cfg_clr);
0523     int (*set_control)(const struct ti_sci_handle *handle, u8 pid,
0524                u32 ctrl_set, u32 ctrl_clr);
0525     int (*get_status)(const struct ti_sci_handle *handle, u8 pid,
0526               u64 *boot_vector, u32 *cfg_flags, u32 *ctrl_flags,
0527               u32 *status_flags);
0528 };
0529
0530 /**
0531  * struct ti_sci_ops - Function support for TI SCI
0532  * @dev_ops:    Device specific operations
0533  * @clk_ops:    Clock specific operations
0534  * @rm_core_ops:    Resource management core operations.
0535  * @rm_irq_ops:     IRQ management specific operations
0536  * @proc_ops:   Processor Control specific operations
0537  */
0538 struct ti_sci_ops {
0539     struct ti_sci_core_ops core_ops;
0540     struct ti_sci_dev_ops dev_ops;
0541     struct ti_sci_clk_ops clk_ops;
0542     struct ti_sci_rm_core_ops rm_core_ops;
0543     struct ti_sci_rm_irq_ops rm_irq_ops;
0544     struct ti_sci_rm_ringacc_ops rm_ring_ops;
0545     struct ti_sci_rm_psil_ops rm_psil_ops;
0546     struct ti_sci_rm_udmap_ops rm_udmap_ops;
0547     struct ti_sci_proc_ops proc_ops;
0548 };
0549
0550 /**
0551  * struct ti_sci_handle - Handle returned to TI SCI clients for usage.
0552  * @version:    structure containing version information
0553  * @ops:    operations that are made available to TI SCI clients
0554  */
0555 struct ti_sci_handle {
0556     struct ti_sci_version_info version;
0557     struct ti_sci_ops ops;
0558 };
0559
0560 #define TI_SCI_RESOURCE_NULL    0xffff
0561
0562 /**
0563  * struct ti_sci_resource - Structure representing a resource assigned
0564  *              to a device.
0565  * @sets:   Number of sets available from this resource type
0566  * @lock:   Lock to guard the res map in each set.
0567  * @desc:   Array of resource descriptors.
0568  */
0569 struct ti_sci_resource {
0570     u16 sets;
0571     raw_spinlock_t lock;
0572     struct ti_sci_resource_desc *desc;
0573 };
0574
0575 #if IS_ENABLED(CONFIG_TI_SCI_PROTOCOL)
0576 const struct ti_sci_handle *ti_sci_get_handle(struct device *dev);
0577 int ti_sci_put_handle(const struct ti_sci_handle *handle);
0578 const struct ti_sci_handle *devm_ti_sci_get_handle(struct device *dev);
0579 const struct ti_sci_handle *ti_sci_get_by_phandle(struct device_node *np,
0580                           const char *property);
0581 const struct ti_sci_handle *devm_ti_sci_get_by_phandle(struct device *dev,
0582                                const char *property);
0583 u16 ti_sci_get_free_resource(struct ti_sci_resource *res);
0584 void ti_sci_release_resource(struct ti_sci_resource *res, u16 id);
0585 u32 ti_sci_get_num_resources(struct ti_sci_resource *res);
0586 struct ti_sci_resource *
0587 devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
0588                 struct device *dev, u32 dev_id, char *of_prop);
0589 struct ti_sci_resource *
0590 devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
0591              u32 dev_id, u32 sub_type);
0592
0593 #else   /* CONFIG_TI_SCI_PROTOCOL */
0594
0595 static inline const struct ti_sci_handle *ti_sci_get_handle(struct device *dev)
0596 {
0597     return ERR_PTR(-EINVAL);
0598 }
0599
0600 static inline int ti_sci_put_handle(const struct ti_sci_handle *handle)
0601 {
0602     return -EINVAL;
0603 }
0604
0605 static inline
0606 const struct ti_sci_handle *devm_ti_sci_get_handle(struct device *dev)
0607 {
0608     return ERR_PTR(-EINVAL);
0609 }
0610
0611 static inline
0612 const struct ti_sci_handle *ti_sci_get_by_phandle(struct device_node *np,
0613                           const char *property)
0614 {
0615     return ERR_PTR(-EINVAL);
0616 }
0617
0618 static inline
0619 const struct ti_sci_handle *devm_ti_sci_get_by_phandle(struct device *dev,
0620                                const char *property)
0621 {
0622     return ERR_PTR(-EINVAL);
0623 }
0624
0625 static inline u16 ti_sci_get_free_resource(struct ti_sci_resource *res)
0626 {
0627     return TI_SCI_RESOURCE_NULL;
0628 }
0629
0630 static inline void ti_sci_release_resource(struct ti_sci_resource *res, u16 id)
0631 {
0632 }
0633
0634 static inline u32 ti_sci_get_num_resources(struct ti_sci_resource *res)
0635 {
0636     return 0;
0637 }
0638
0639 static inline struct ti_sci_resource *
0640 devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
0641                 struct device *dev, u32 dev_id, char *of_prop)
0642 {
0643     return ERR_PTR(-EINVAL);
0644 }
0645
0646 static inline struct ti_sci_resource *
0647 devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
0648              u32 dev_id, u32 sub_type)
0649 {
0650     return ERR_PTR(-EINVAL);
0651 }
0652 #endif  /* CONFIG_TI_SCI_PROTOCOL */
0653
0654 #endif  /* __TISCI_PROTOCOL_H */