soc/ti/omap1-io.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 #ifndef __ASM_ARCH_OMAP_IO_H
0003 #define __ASM_ARCH_OMAP_IO_H
0004
0005 #ifndef __ASSEMBLER__
0006 #include <linux/types.h>
0007
0008 #ifdef CONFIG_ARCH_OMAP1_ANY
0009 /*
0010  * NOTE: Please use ioremap + __raw_read/write where possible instead of these
0011  */
0012 extern u8 omap_readb(u32 pa);
0013 extern u16 omap_readw(u32 pa);
0014 extern u32 omap_readl(u32 pa);
0015 extern void omap_writeb(u8 v, u32 pa);
0016 extern void omap_writew(u16 v, u32 pa);
0017 extern void omap_writel(u32 v, u32 pa);
0018 #else
0019 static inline u8 omap_readb(u32 pa)  { return 0; }
0020 static inline u16 omap_readw(u32 pa) { return 0; }
0021 static inline u32 omap_readl(u32 pa) { return 0; }
0022 static inline void omap_writeb(u8 v, u32 pa)   { }
0023 static inline void omap_writew(u16 v, u32 pa)  { }
0024 static inline void omap_writel(u32 v, u32 pa)  { }
0025 #endif
0026 #endif
0027
0028 /*
0029  * ----------------------------------------------------------------------------
0030  * System control registers
0031  * ----------------------------------------------------------------------------
0032  */
0033 #define MOD_CONF_CTRL_0     0xfffe1080
0034 #define MOD_CONF_CTRL_1     0xfffe1110
0035
0036 /*
0037  * ---------------------------------------------------------------------------
0038  * UPLD
0039  * ---------------------------------------------------------------------------
0040  */
0041 #define ULPD_REG_BASE       (0xfffe0800)
0042 #define ULPD_IT_STATUS      (ULPD_REG_BASE + 0x14)
0043 #define ULPD_SETUP_ANALOG_CELL_3    (ULPD_REG_BASE + 0x24)
0044 #define ULPD_CLOCK_CTRL     (ULPD_REG_BASE + 0x30)
0045 #   define DIS_USB_PVCI_CLK     (1 << 5)    /* no USB/FAC synch */
0046 #   define USB_MCLK_EN      (1 << 4)    /* enable W4_USB_CLKO */
0047 #define ULPD_SOFT_REQ       (ULPD_REG_BASE + 0x34)
0048 #   define SOFT_UDC_REQ     (1 << 4)
0049 #   define SOFT_USB_CLK_REQ     (1 << 3)
0050 #   define SOFT_DPLL_REQ        (1 << 0)
0051 #define ULPD_DPLL_CTRL      (ULPD_REG_BASE + 0x3c)
0052 #define ULPD_STATUS_REQ     (ULPD_REG_BASE + 0x40)
0053 #define ULPD_APLL_CTRL      (ULPD_REG_BASE + 0x4c)
0054 #define ULPD_POWER_CTRL     (ULPD_REG_BASE + 0x50)
0055 #define ULPD_SOFT_DISABLE_REQ_REG   (ULPD_REG_BASE + 0x68)
0056 #   define DIS_MMC2_DPLL_REQ    (1 << 11)
0057 #   define DIS_MMC1_DPLL_REQ    (1 << 10)
0058 #   define DIS_UART3_DPLL_REQ   (1 << 9)
0059 #   define DIS_UART2_DPLL_REQ   (1 << 8)
0060 #   define DIS_UART1_DPLL_REQ   (1 << 7)
0061 #   define DIS_USB_HOST_DPLL_REQ    (1 << 6)
0062 #define ULPD_SDW_CLK_DIV_CTRL_SEL   (ULPD_REG_BASE + 0x74)
0063 #define ULPD_CAM_CLK_CTRL   (ULPD_REG_BASE + 0x7c)
0064
0065 /*
0066  * ----------------------------------------------------------------------------
0067  * Clocks
0068  * ----------------------------------------------------------------------------
0069  */
0070 #define CLKGEN_REG_BASE     (0xfffece00)
0071 #define ARM_CKCTL       (CLKGEN_REG_BASE + 0x0)
0072 #define ARM_IDLECT1     (CLKGEN_REG_BASE + 0x4)
0073 #define ARM_IDLECT2     (CLKGEN_REG_BASE + 0x8)
0074 #define ARM_EWUPCT      (CLKGEN_REG_BASE + 0xC)
0075 #define ARM_RSTCT1      (CLKGEN_REG_BASE + 0x10)
0076 #define ARM_RSTCT2      (CLKGEN_REG_BASE + 0x14)
0077 #define ARM_SYSST       (CLKGEN_REG_BASE + 0x18)
0078 #define ARM_IDLECT3     (CLKGEN_REG_BASE + 0x24)
0079
0080 #define CK_RATEF        1
0081 #define CK_IDLEF        2
0082 #define CK_ENABLEF      4
0083 #define CK_SELECTF      8
0084 #define SETARM_IDLE_SHIFT
0085
0086 /* DPLL control registers */
0087 #define DPLL_CTL        (0xfffecf00)
0088
0089 /* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
0090 #define DSP_CONFIG_REG_BASE     IOMEM(0xe1008000)
0091 #define DSP_CKCTL       (DSP_CONFIG_REG_BASE + 0x0)
0092 #define DSP_IDLECT1     (DSP_CONFIG_REG_BASE + 0x4)
0093 #define DSP_IDLECT2     (DSP_CONFIG_REG_BASE + 0x8)
0094 #define DSP_RSTCT2      (DSP_CONFIG_REG_BASE + 0x14)
0095
0096 /*
0097  * ----------------------------------------------------------------------------
0098  * Pulse-Width Light
0099  * ----------------------------------------------------------------------------
0100  */
0101 #define OMAP_PWL_BASE           0xfffb5800
0102 #define OMAP_PWL_ENABLE         (OMAP_PWL_BASE + 0x00)
0103 #define OMAP_PWL_CLK_ENABLE     (OMAP_PWL_BASE + 0x04)
0104
0105 /*
0106  * ----------------------------------------------------------------------------
0107  * Pin multiplexing registers
0108  * ----------------------------------------------------------------------------
0109  */
0110 #define FUNC_MUX_CTRL_0     0xfffe1000
0111 #define FUNC_MUX_CTRL_1     0xfffe1004
0112 #define FUNC_MUX_CTRL_2     0xfffe1008
0113 #define COMP_MODE_CTRL_0    0xfffe100c
0114 #define FUNC_MUX_CTRL_3     0xfffe1010
0115 #define FUNC_MUX_CTRL_4     0xfffe1014
0116 #define FUNC_MUX_CTRL_5     0xfffe1018
0117 #define FUNC_MUX_CTRL_6     0xfffe101C
0118 #define FUNC_MUX_CTRL_7     0xfffe1020
0119 #define FUNC_MUX_CTRL_8     0xfffe1024
0120 #define FUNC_MUX_CTRL_9     0xfffe1028
0121 #define FUNC_MUX_CTRL_A     0xfffe102C
0122 #define FUNC_MUX_CTRL_B     0xfffe1030
0123 #define FUNC_MUX_CTRL_C     0xfffe1034
0124 #define FUNC_MUX_CTRL_D     0xfffe1038
0125 #define PULL_DWN_CTRL_0     0xfffe1040
0126 #define PULL_DWN_CTRL_1     0xfffe1044
0127 #define PULL_DWN_CTRL_2     0xfffe1048
0128 #define PULL_DWN_CTRL_3     0xfffe104c
0129 #define PULL_DWN_CTRL_4     0xfffe10ac
0130
0131 /* OMAP-1610 specific multiplexing registers */
0132 #define FUNC_MUX_CTRL_E     0xfffe1090
0133 #define FUNC_MUX_CTRL_F     0xfffe1094
0134 #define FUNC_MUX_CTRL_10    0xfffe1098
0135 #define FUNC_MUX_CTRL_11    0xfffe109c
0136 #define FUNC_MUX_CTRL_12    0xfffe10a0
0137 #define PU_PD_SEL_0     0xfffe10b4
0138 #define PU_PD_SEL_1     0xfffe10b8
0139 #define PU_PD_SEL_2     0xfffe10bc
0140 #define PU_PD_SEL_3     0xfffe10c0
0141 #define PU_PD_SEL_4     0xfffe10c4
0142
0143 #endif