soc/samsung/s3c-cpu-freq.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2006-2007 Simtec Electronics
0004  *  http://armlinux.simtec.co.uk/
0005  *  Ben Dooks <ben@simtec.co.uk>
0006  *
0007  * S3C CPU frequency scaling support - driver and board
0008  */
0009 #ifndef __LINUX_SOC_SAMSUNG_S3C_CPU_FREQ_H
0010 #define __LINUX_SOC_SAMSUNG_S3C_CPU_FREQ_H
0011
0012 #include <linux/cpufreq.h>
0013
0014 struct s3c_cpufreq_info;
0015 struct s3c_cpufreq_board;
0016 struct s3c_iotimings;
0017
0018 /**
0019  * struct s3c_freq - frequency information (mainly for core drivers)
0020  * @fclk: The FCLK frequency in Hz.
0021  * @armclk: The ARMCLK frequency in Hz.
0022  * @hclk_tns: HCLK cycle time in 10ths of nano-seconds.
0023  * @hclk: The HCLK frequency in Hz.
0024  * @pclk: The PCLK frequency in Hz.
0025  *
0026  * This contains the frequency information about the current configuration
0027  * mainly for the core drivers to ensure we do not end up passing about
0028  * a large number of parameters.
0029  *
0030  * The @hclk_tns field is a useful cache for the parts of the drivers that
0031  * need to calculate IO timings and suchlike.
0032  */
0033 struct s3c_freq {
0034     unsigned long   fclk;
0035     unsigned long   armclk;
0036     unsigned long   hclk_tns;   /* in 10ths of ns */
0037     unsigned long   hclk;
0038     unsigned long   pclk;
0039 };
0040
0041 /**
0042  * struct s3c_cpufreq_freqs - s3c cpufreq notification information.
0043  * @freqs: The cpufreq setting information.
0044  * @old: The old clock settings.
0045  * @new: The new clock settings.
0046  * @pll_changing: Set if the PLL is changing.
0047  *
0048  * Wrapper 'struct cpufreq_freqs' so that any drivers receiving the
0049  * notification can use this information that is not provided by just
0050  * having the core frequency alone.
0051  *
0052  * The pll_changing flag is used to indicate if the PLL itself is
0053  * being set during this change. This is important as the clocks
0054  * will temporarily be set to the XTAL clock during this time, so
0055  * drivers may want to close down their output during this time.
0056  *
0057  * Note, this is not being used by any current drivers and therefore
0058  * may be removed in the future.
0059  */
0060 struct s3c_cpufreq_freqs {
0061     struct cpufreq_freqs    freqs;
0062     struct s3c_freq     old;
0063     struct s3c_freq     new;
0064
0065     unsigned int        pll_changing:1;
0066 };
0067
0068 #define to_s3c_cpufreq(_cf) container_of(_cf, struct s3c_cpufreq_freqs, freqs)
0069
0070 /**
0071  * struct s3c_clkdivs - clock divisor information
0072  * @p_divisor: Divisor from FCLK to PCLK.
0073  * @h_divisor: Divisor from FCLK to HCLK.
0074  * @arm_divisor: Divisor from FCLK to ARMCLK (not all CPUs).
0075  * @dvs: Non-zero if using DVS mode for ARMCLK.
0076  *
0077  * Divisor settings for the core clocks.
0078  */
0079 struct s3c_clkdivs {
0080     int     p_divisor;
0081     int     h_divisor;
0082     int     arm_divisor;
0083     unsigned char   dvs;
0084 };
0085
0086 #define PLLVAL(_m, _p, _s) (((_m) << 12) | ((_p) << 4) | (_s))
0087
0088 /**
0089  * struct s3c_pllval - PLL value entry.
0090  * @freq: The frequency for this entry in Hz.
0091  * @pll_reg: The PLL register setting for this PLL value.
0092  */
0093 struct s3c_pllval {
0094     unsigned long       freq;
0095     unsigned long       pll_reg;
0096 };
0097
0098 /**
0099  * struct s3c_cpufreq_board - per-board cpu frequency informatin
0100  * @refresh: The SDRAM refresh period in nanoseconds.
0101  * @auto_io: Set if the IO timing settings should be generated from the
0102  *  initialisation time hardware registers.
0103  * @need_io: Set if the board has external IO on any of the chipselect
0104  *  lines that will require the hardware timing registers to be
0105  *  updated on a clock change.
0106  * @max: The maxium frequency limits for the system. Any field that
0107  *  is left at zero will use the CPU's settings.
0108  *
0109  * This contains the board specific settings that affect how the CPU
0110  * drivers chose settings. These include the memory refresh and IO
0111  * timing information.
0112  *
0113  * Registration depends on the driver being used, the ARMCLK only
0114  * implementation does not currently need this but the older style
0115  * driver requires this to be available.
0116  */
0117 struct s3c_cpufreq_board {
0118     unsigned int    refresh;
0119     unsigned int    auto_io:1;  /* automatically init io timings. */
0120     unsigned int    need_io:1;  /* set if needs io timing support. */
0121
0122     /* any non-zero field in here is taken as an upper limit. */
0123     struct s3c_freq max;    /* frequency limits */
0124 };
0125
0126 /* Things depending on frequency scaling. */
0127 #ifdef CONFIG_ARM_S3C_CPUFREQ
0128 #define __init_or_cpufreq
0129 #else
0130 #define __init_or_cpufreq __init
0131 #endif
0132
0133 /* Board functions */
0134
0135 #ifdef CONFIG_ARM_S3C_CPUFREQ
0136 extern int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board);
0137 #else
0138
0139 static inline int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
0140 {
0141     return 0;
0142 }
0143 #endif  /* CONFIG_ARM_S3C_CPUFREQ */
0144
0145 #endif