0001
0002 #ifndef __QCOM_SMD_RPM_H__
0003 #define __QCOM_SMD_RPM_H__
0004
0005 struct qcom_smd_rpm;
0006
0007 #define QCOM_SMD_RPM_ACTIVE_STATE 0
0008 #define QCOM_SMD_RPM_SLEEP_STATE 1
0009
0010
0011
0012
0013 #define QCOM_SMD_RPM_BBYB 0x62796262
0014 #define QCOM_SMD_RPM_BOBB 0x62626f62
0015 #define QCOM_SMD_RPM_BOOST 0x61747362
0016 #define QCOM_SMD_RPM_BUS_CLK 0x316b6c63
0017 #define QCOM_SMD_RPM_BUS_MASTER 0x73616d62
0018 #define QCOM_SMD_RPM_BUS_SLAVE 0x766c7362
0019 #define QCOM_SMD_RPM_CLK_BUF_A 0x616B6C63
0020 #define QCOM_SMD_RPM_LDOA 0x616f646c
0021 #define QCOM_SMD_RPM_LDOB 0x626F646C
0022 #define QCOM_SMD_RPM_RWCX 0x78637772
0023 #define QCOM_SMD_RPM_RWMX 0x786d7772
0024 #define QCOM_SMD_RPM_RWLC 0x636c7772
0025 #define QCOM_SMD_RPM_RWLM 0x6d6c7772
0026 #define QCOM_SMD_RPM_MEM_CLK 0x326b6c63
0027 #define QCOM_SMD_RPM_MISC_CLK 0x306b6c63
0028 #define QCOM_SMD_RPM_NCPA 0x6170636E
0029 #define QCOM_SMD_RPM_NCPB 0x6270636E
0030 #define QCOM_SMD_RPM_OCMEM_PWR 0x706d636f
0031 #define QCOM_SMD_RPM_QPIC_CLK 0x63697071
0032 #define QCOM_SMD_RPM_QUP_CLK 0x707571
0033 #define QCOM_SMD_RPM_SMPA 0x61706d73
0034 #define QCOM_SMD_RPM_SMPB 0x62706d73
0035 #define QCOM_SMD_RPM_SPDM 0x63707362
0036 #define QCOM_SMD_RPM_VSA 0x00617376
0037 #define QCOM_SMD_RPM_MMAXI_CLK 0x69786d6d
0038 #define QCOM_SMD_RPM_IPA_CLK 0x617069
0039 #define QCOM_SMD_RPM_CE_CLK 0x6563
0040 #define QCOM_SMD_RPM_AGGR_CLK 0x72676761
0041 #define QCOM_SMD_RPM_HWKM_CLK 0x6d6b7768
0042 #define QCOM_SMD_RPM_PKA_CLK 0x616b70
0043 #define QCOM_SMD_RPM_MCFG_CLK 0x6766636d
0044
0045 int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,
0046 int state,
0047 u32 resource_type, u32 resource_id,
0048 void *buf, size_t count);
0049
0050 #endif