soc/mediatek/mtk-mmsys.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2015 MediaTek Inc.
0004  */
0005
0006 #ifndef __MTK_MMSYS_H
0007 #define __MTK_MMSYS_H
0008
0009 enum mtk_ddp_comp_id;
0010 struct device;
0011
0012 enum mtk_ddp_comp_id {
0013     DDP_COMPONENT_AAL0,
0014     DDP_COMPONENT_AAL1,
0015     DDP_COMPONENT_BLS,
0016     DDP_COMPONENT_CCORR,
0017     DDP_COMPONENT_COLOR0,
0018     DDP_COMPONENT_COLOR1,
0019     DDP_COMPONENT_DITHER,
0020     DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
0021     DDP_COMPONENT_DITHER1,
0022     DDP_COMPONENT_DP_INTF0,
0023     DDP_COMPONENT_DP_INTF1,
0024     DDP_COMPONENT_DPI0,
0025     DDP_COMPONENT_DPI1,
0026     DDP_COMPONENT_DSC0,
0027     DDP_COMPONENT_DSC1,
0028     DDP_COMPONENT_DSI0,
0029     DDP_COMPONENT_DSI1,
0030     DDP_COMPONENT_DSI2,
0031     DDP_COMPONENT_DSI3,
0032     DDP_COMPONENT_GAMMA,
0033     DDP_COMPONENT_MERGE0,
0034     DDP_COMPONENT_MERGE1,
0035     DDP_COMPONENT_MERGE2,
0036     DDP_COMPONENT_MERGE3,
0037     DDP_COMPONENT_MERGE4,
0038     DDP_COMPONENT_MERGE5,
0039     DDP_COMPONENT_OD0,
0040     DDP_COMPONENT_OD1,
0041     DDP_COMPONENT_OVL0,
0042     DDP_COMPONENT_OVL_2L0,
0043     DDP_COMPONENT_OVL_2L1,
0044     DDP_COMPONENT_OVL_2L2,
0045     DDP_COMPONENT_OVL1,
0046     DDP_COMPONENT_POSTMASK0,
0047     DDP_COMPONENT_PWM0,
0048     DDP_COMPONENT_PWM1,
0049     DDP_COMPONENT_PWM2,
0050     DDP_COMPONENT_RDMA0,
0051     DDP_COMPONENT_RDMA1,
0052     DDP_COMPONENT_RDMA2,
0053     DDP_COMPONENT_RDMA4,
0054     DDP_COMPONENT_UFOE,
0055     DDP_COMPONENT_WDMA0,
0056     DDP_COMPONENT_WDMA1,
0057     DDP_COMPONENT_ID_MAX,
0058 };
0059
0060 void mtk_mmsys_ddp_connect(struct device *dev,
0061                enum mtk_ddp_comp_id cur,
0062                enum mtk_ddp_comp_id next);
0063
0064 void mtk_mmsys_ddp_disconnect(struct device *dev,
0065                   enum mtk_ddp_comp_id cur,
0066                   enum mtk_ddp_comp_id next);
0067
0068 #endif /* __MTK_MMSYS_H */