marvell/octeontx2/asm.h

0001 /* SPDX-License-Identifier: GPL-2.0-only
0002  * Copyright (C) 2020 Marvell.
0003  */
0004
0005 #ifndef __SOC_OTX2_ASM_H
0006 #define __SOC_OTX2_ASM_H
0007
0008 #include <linux/types.h>
0009 #if defined(CONFIG_ARM64)
0010 /*
0011  * otx2_lmt_flush is used for LMT store operation.
0012  * On octeontx2 platform CPT instruction enqueue and
0013  * NIX packet send are only possible via LMTST
0014  * operations and it uses LDEOR instruction targeting
0015  * the coprocessor address.
0016  */
0017 #define otx2_lmt_flush(ioaddr)                          \
0018 ({                                                      \
0019     u64 result = 0;                                 \
0020     __asm__ volatile(".cpu  generic+lse\n"          \
0021              "ldeor xzr, %x[rf], [%[rs]]"   \
0022              : [rf]"=r" (result)            \
0023              : [rs]"r" (ioaddr));           \
0024     (result);                                       \
0025 })
0026 /*
0027  * STEORL store to memory with release semantics.
0028  * This will avoid using DMB barrier after each LMTST
0029  * operation.
0030  */
0031 #define cn10k_lmt_flush(val, addr)          \
0032 ({                          \
0033     __asm__ volatile(".cpu  generic+lse\n"      \
0034              "steorl %x[rf],[%[rs]]"        \
0035              : [rf] "+r"(val)       \
0036              : [rs] "r"(addr));     \
0037 })
0038
0039 static inline u64 otx2_atomic64_fetch_add(u64 incr, u64 *ptr)
0040 {
0041     u64 result;
0042
0043     asm volatile (".cpu  generic+lse\n"
0044               "ldadda %x[i], %x[r], [%[b]]"
0045               : [r] "=r" (result), "+m" (*ptr)
0046               : [i] "r" (incr), [b] "r" (ptr)
0047               : "memory");
0048     return result;
0049 }
0050
0051 #else
0052 #define otx2_lmt_flush(ioaddr)          ({ 0; })
0053 #define cn10k_lmt_flush(val, addr)  ({ addr = val; })
0054 #define otx2_atomic64_fetch_add(incr, ptr)  ({ incr; })
0055 #endif
0056
0057 #endif /* __SOC_OTX2_ASM_H */