soc/ixp4xx/cpu.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * IXP4XX cpu type detection
0004  *
0005  * Copyright (C) 2007 MontaVista Software, Inc.
0006  */
0007
0008 #ifndef __SOC_IXP4XX_CPU_H__
0009 #define __SOC_IXP4XX_CPU_H__
0010
0011 #include <linux/io.h>
0012 #include <linux/regmap.h>
0013 #ifdef CONFIG_ARM
0014 #include <asm/cputype.h>
0015 #endif
0016
0017 /* Processor id value in CP15 Register 0 */
0018 #define IXP42X_PROCESSOR_ID_VALUE   0x690541c0 /* including unused 0x690541Ex */
0019 #define IXP42X_PROCESSOR_ID_MASK    0xffffffc0
0020
0021 #define IXP43X_PROCESSOR_ID_VALUE   0x69054040
0022 #define IXP43X_PROCESSOR_ID_MASK    0xfffffff0
0023
0024 #define IXP46X_PROCESSOR_ID_VALUE   0x69054200 /* including IXP455 */
0025 #define IXP46X_PROCESSOR_ID_MASK    0xfffffff0
0026
0027 /* Feature register in the expansion bus controller */
0028 #define IXP4XX_EXP_CNFG2        0x2c
0029
0030 /* "fuse" bits of IXP_EXP_CFG2 */
0031 /* All IXP4xx CPUs */
0032 #define IXP4XX_FEATURE_RCOMP        (1 << 0)
0033 #define IXP4XX_FEATURE_USB_DEVICE   (1 << 1)
0034 #define IXP4XX_FEATURE_HASH     (1 << 2)
0035 #define IXP4XX_FEATURE_AES      (1 << 3)
0036 #define IXP4XX_FEATURE_DES      (1 << 4)
0037 #define IXP4XX_FEATURE_HDLC     (1 << 5)
0038 #define IXP4XX_FEATURE_AAL      (1 << 6)
0039 #define IXP4XX_FEATURE_HSS      (1 << 7)
0040 #define IXP4XX_FEATURE_UTOPIA       (1 << 8)
0041 #define IXP4XX_FEATURE_NPEB_ETH0    (1 << 9)
0042 #define IXP4XX_FEATURE_NPEC_ETH     (1 << 10)
0043 #define IXP4XX_FEATURE_RESET_NPEA   (1 << 11)
0044 #define IXP4XX_FEATURE_RESET_NPEB   (1 << 12)
0045 #define IXP4XX_FEATURE_RESET_NPEC   (1 << 13)
0046 #define IXP4XX_FEATURE_PCI      (1 << 14)
0047 #define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16)
0048 #define IXP4XX_FEATURE_XSCALE_MAX_FREQ  (3 << 22)
0049 #define IXP42X_FEATURE_MASK     (IXP4XX_FEATURE_RCOMP            | \
0050                      IXP4XX_FEATURE_USB_DEVICE       | \
0051                      IXP4XX_FEATURE_HASH             | \
0052                      IXP4XX_FEATURE_AES              | \
0053                      IXP4XX_FEATURE_DES              | \
0054                      IXP4XX_FEATURE_HDLC             | \
0055                      IXP4XX_FEATURE_AAL              | \
0056                      IXP4XX_FEATURE_HSS              | \
0057                      IXP4XX_FEATURE_UTOPIA           | \
0058                      IXP4XX_FEATURE_NPEB_ETH0        | \
0059                      IXP4XX_FEATURE_NPEC_ETH         | \
0060                      IXP4XX_FEATURE_RESET_NPEA       | \
0061                      IXP4XX_FEATURE_RESET_NPEB       | \
0062                      IXP4XX_FEATURE_RESET_NPEC       | \
0063                      IXP4XX_FEATURE_PCI              | \
0064                      IXP4XX_FEATURE_UTOPIA_PHY_LIMIT | \
0065                      IXP4XX_FEATURE_XSCALE_MAX_FREQ)
0066
0067
0068 /* IXP43x/46x CPUs */
0069 #define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15)
0070 #define IXP4XX_FEATURE_USB_HOST     (1 << 18)
0071 #define IXP4XX_FEATURE_NPEA_ETH     (1 << 19)
0072 #define IXP43X_FEATURE_MASK     (IXP42X_FEATURE_MASK             | \
0073                      IXP4XX_FEATURE_ECC_TIMESYNC     | \
0074                      IXP4XX_FEATURE_USB_HOST         | \
0075                      IXP4XX_FEATURE_NPEA_ETH)
0076
0077 /* IXP46x CPU (including IXP455) only */
0078 #define IXP4XX_FEATURE_NPEB_ETH_1_TO_3  (1 << 20)
0079 #define IXP4XX_FEATURE_RSA      (1 << 21)
0080 #define IXP46X_FEATURE_MASK     (IXP43X_FEATURE_MASK             | \
0081                      IXP4XX_FEATURE_NPEB_ETH_1_TO_3  | \
0082                      IXP4XX_FEATURE_RSA)
0083
0084 #ifdef CONFIG_ARCH_IXP4XX
0085 #define cpu_is_ixp42x_rev_a0() ((read_cpuid_id() & (IXP42X_PROCESSOR_ID_MASK | 0xF)) == \
0086                 IXP42X_PROCESSOR_ID_VALUE)
0087 #define cpu_is_ixp42x() ((read_cpuid_id() & IXP42X_PROCESSOR_ID_MASK) == \
0088              IXP42X_PROCESSOR_ID_VALUE)
0089 #define cpu_is_ixp43x() ((read_cpuid_id() & IXP43X_PROCESSOR_ID_MASK) == \
0090              IXP43X_PROCESSOR_ID_VALUE)
0091 #define cpu_is_ixp46x() ((read_cpuid_id() & IXP46X_PROCESSOR_ID_MASK) == \
0092              IXP46X_PROCESSOR_ID_VALUE)
0093 static inline u32 cpu_ixp4xx_features(struct regmap *rmap)
0094 {
0095     u32 val;
0096
0097     regmap_read(rmap, IXP4XX_EXP_CNFG2, &val);
0098     /* For some reason this register is inverted */
0099     val = ~val;
0100     if (cpu_is_ixp42x_rev_a0())
0101         return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP |
0102                            IXP4XX_FEATURE_AES);
0103     if (cpu_is_ixp42x())
0104         return val & IXP42X_FEATURE_MASK;
0105     if (cpu_is_ixp43x())
0106         return val & IXP43X_FEATURE_MASK;
0107     return val & IXP46X_FEATURE_MASK;
0108 }
0109 #else
0110 #define cpu_is_ixp42x_rev_a0()      0
0111 #define cpu_is_ixp42x()         0
0112 #define cpu_is_ixp43x()         0
0113 #define cpu_is_ixp46x()         0
0114 static inline u32 cpu_ixp4xx_features(struct regmap *rmap)
0115 {
0116     return 0;
0117 }
0118 #endif
0119
0120 #endif  /* _ASM_ARCH_CPU_H */