include/linux/sh_dma.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Header for the new SH dmaengine driver
0004  *
0005  * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
0006  */
0007 #ifndef SH_DMA_H
0008 #define SH_DMA_H
0009
0010 #include <linux/dmaengine.h>
0011 #include <linux/list.h>
0012 #include <linux/shdma-base.h>
0013 #include <linux/types.h>
0014
0015 struct device;
0016
0017 /* Used by slave DMA clients to request DMA to/from a specific peripheral */
0018 struct sh_dmae_slave {
0019     struct shdma_slave      shdma_slave;    /* Set by the platform */
0020 };
0021
0022 /*
0023  * Supplied by platforms to specify, how a DMA channel has to be configured for
0024  * a certain peripheral
0025  */
0026 struct sh_dmae_slave_config {
0027     int     slave_id;
0028     dma_addr_t  addr;
0029     u32     chcr;
0030     char        mid_rid;
0031 };
0032
0033 /**
0034  * struct sh_dmae_channel - DMAC channel platform data
0035  * @offset:     register offset within the main IOMEM resource
0036  * @dmars:      channel DMARS register offset
0037  * @chclr_offset:   channel CHCLR register offset
0038  * @dmars_bit:      channel DMARS field offset within the register
0039  * @chclr_bit:      bit position, to be set to reset the channel
0040  */
0041 struct sh_dmae_channel {
0042     unsigned int    offset;
0043     unsigned int    dmars;
0044     unsigned int    chclr_offset;
0045     unsigned char   dmars_bit;
0046     unsigned char   chclr_bit;
0047 };
0048
0049 /**
0050  * struct sh_dmae_pdata - DMAC platform data
0051  * @slave:      array of slaves
0052  * @slave_num:      number of slaves in the above array
0053  * @channel:        array of DMA channels
0054  * @channel_num:    number of channels in the above array
0055  * @ts_low_shift:   shift of the low part of the TS field
0056  * @ts_low_mask:    low TS field mask
0057  * @ts_high_shift:  additional shift of the high part of the TS field
0058  * @ts_high_mask:   high TS field mask
0059  * @ts_shift:       array of Transfer Size shifts, indexed by TS value
0060  * @ts_shift_num:   number of shifts in the above array
0061  * @dmaor_init:     DMAOR initialisation value
0062  * @chcr_offset:    CHCR address offset
0063  * @chcr_ie_bit:    CHCR Interrupt Enable bit
0064  * @dmaor_is_32bit: DMAOR is a 32-bit register
0065  * @needs_tend_set: the TEND register has to be set
0066  * @no_dmars:       DMAC has no DMARS registers
0067  * @chclr_present:  DMAC has one or several CHCLR registers
0068  * @chclr_bitwise:  channel CHCLR registers are bitwise
0069  * @slave_only:     DMAC cannot be used for MEMCPY
0070  */
0071 struct sh_dmae_pdata {
0072     const struct sh_dmae_slave_config *slave;
0073     int slave_num;
0074     const struct sh_dmae_channel *channel;
0075     int channel_num;
0076     unsigned int ts_low_shift;
0077     unsigned int ts_low_mask;
0078     unsigned int ts_high_shift;
0079     unsigned int ts_high_mask;
0080     const unsigned int *ts_shift;
0081     int ts_shift_num;
0082     u16 dmaor_init;
0083     unsigned int chcr_offset;
0084     u32 chcr_ie_bit;
0085
0086     unsigned int dmaor_is_32bit:1;
0087     unsigned int needs_tend_set:1;
0088     unsigned int no_dmars:1;
0089     unsigned int chclr_present:1;
0090     unsigned int chclr_bitwise:1;
0091     unsigned int slave_only:1;
0092 };
0093
0094 /* DMAOR definitions */
0095 #define DMAOR_AE    0x00000004  /* Address Error Flag */
0096 #define DMAOR_NMIF  0x00000002
0097 #define DMAOR_DME   0x00000001  /* DMA Master Enable */
0098
0099 /* Definitions for the SuperH DMAC */
0100 #define DM_INC  0x00004000  /* Destination addresses are incremented */
0101 #define DM_DEC  0x00008000  /* Destination addresses are decremented */
0102 #define DM_FIX  0x0000c000  /* Destination address is fixed */
0103 #define SM_INC  0x00001000  /* Source addresses are incremented */
0104 #define SM_DEC  0x00002000  /* Source addresses are decremented */
0105 #define SM_FIX  0x00003000  /* Source address is fixed */
0106 #define RS_AUTO 0x00000400  /* Auto Request */
0107 #define RS_ERS  0x00000800  /* DMA extended resource selector */
0108 #define CHCR_DE 0x00000001  /* DMA Enable */
0109 #define CHCR_TE 0x00000002  /* Transfer End Flag */
0110 #define CHCR_IE 0x00000004  /* Interrupt Enable */
0111
0112 #endif