include/linux/sh_clk.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __SH_CLOCK_H
0003 #define __SH_CLOCK_H
0004
0005 #include <linux/list.h>
0006 #include <linux/seq_file.h>
0007 #include <linux/cpufreq.h>
0008 #include <linux/types.h>
0009 #include <linux/kref.h>
0010 #include <linux/clk.h>
0011 #include <linux/err.h>
0012
0013 struct clk;
0014
0015 struct clk_mapping {
0016     phys_addr_t     phys;
0017     void __iomem        *base;
0018     unsigned long       len;
0019     struct kref     ref;
0020 };
0021
0022 struct sh_clk_ops {
0023 #ifdef CONFIG_SH_CLK_CPG_LEGACY
0024     void (*init)(struct clk *clk);
0025 #endif
0026     int (*enable)(struct clk *clk);
0027     void (*disable)(struct clk *clk);
0028     unsigned long (*recalc)(struct clk *clk);
0029     int (*set_rate)(struct clk *clk, unsigned long rate);
0030     int (*set_parent)(struct clk *clk, struct clk *parent);
0031     long (*round_rate)(struct clk *clk, unsigned long rate);
0032 };
0033
0034 #define SH_CLK_DIV_MSK(div) ((1 << (div)) - 1)
0035 #define SH_CLK_DIV4_MSK     SH_CLK_DIV_MSK(4)
0036 #define SH_CLK_DIV6_MSK     SH_CLK_DIV_MSK(6)
0037
0038 struct clk {
0039     struct list_head    node;
0040     struct clk      *parent;
0041     struct clk      **parent_table; /* list of parents to */
0042     unsigned short      parent_num; /* choose between */
0043     unsigned char       src_shift;  /* source clock field in the */
0044     unsigned char       src_width;  /* configuration register */
0045     struct sh_clk_ops   *ops;
0046
0047     struct list_head    children;
0048     struct list_head    sibling;    /* node for children */
0049
0050     int         usecount;
0051
0052     unsigned long       rate;
0053     unsigned long       flags;
0054
0055     void __iomem        *enable_reg;
0056     void __iomem        *status_reg;
0057     unsigned int        enable_bit;
0058     void __iomem        *mapped_reg;
0059
0060     unsigned int        div_mask;
0061     unsigned long       arch_flags;
0062     void            *priv;
0063     struct clk_mapping  *mapping;
0064     struct cpufreq_frequency_table *freq_table;
0065     unsigned int        nr_freqs;
0066 };
0067
0068 #define CLK_ENABLE_ON_INIT  BIT(0)
0069
0070 #define CLK_ENABLE_REG_32BIT    BIT(1)  /* default access size */
0071 #define CLK_ENABLE_REG_16BIT    BIT(2)
0072 #define CLK_ENABLE_REG_8BIT BIT(3)
0073
0074 #define CLK_MASK_DIV_ON_DISABLE BIT(4)
0075
0076 #define CLK_ENABLE_REG_MASK (CLK_ENABLE_REG_32BIT | \
0077                  CLK_ENABLE_REG_16BIT | \
0078                  CLK_ENABLE_REG_8BIT)
0079
0080 /* drivers/sh/clk.c */
0081 unsigned long followparent_recalc(struct clk *);
0082 void recalculate_root_clocks(void);
0083 void propagate_rate(struct clk *);
0084 int clk_reparent(struct clk *child, struct clk *parent);
0085 int clk_register(struct clk *);
0086 void clk_unregister(struct clk *);
0087 void clk_enable_init_clocks(void);
0088
0089 struct clk_div_mult_table {
0090     unsigned int *divisors;
0091     unsigned int nr_divisors;
0092     unsigned int *multipliers;
0093     unsigned int nr_multipliers;
0094 };
0095
0096 struct cpufreq_frequency_table;
0097 void clk_rate_table_build(struct clk *clk,
0098               struct cpufreq_frequency_table *freq_table,
0099               int nr_freqs,
0100               struct clk_div_mult_table *src_table,
0101               unsigned long *bitmap);
0102
0103 long clk_rate_table_round(struct clk *clk,
0104               struct cpufreq_frequency_table *freq_table,
0105               unsigned long rate);
0106
0107 int clk_rate_table_find(struct clk *clk,
0108             struct cpufreq_frequency_table *freq_table,
0109             unsigned long rate);
0110
0111 long clk_rate_div_range_round(struct clk *clk, unsigned int div_min,
0112                   unsigned int div_max, unsigned long rate);
0113
0114 long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min,
0115                    unsigned int mult_max, unsigned long rate);
0116
0117 #define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _status_reg, _flags) \
0118 {                                   \
0119     .parent     = _parent,                  \
0120     .enable_reg = (void __iomem *)_enable_reg,          \
0121     .enable_bit = _enable_bit,                  \
0122     .status_reg = _status_reg,                  \
0123     .flags      = _flags,                   \
0124 }
0125
0126 #define SH_CLK_MSTP32(_p, _r, _b, _f)               \
0127     SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_32BIT)
0128
0129 #define SH_CLK_MSTP32_STS(_p, _r, _b, _s, _f)           \
0130     SH_CLK_MSTP(_p, _r, _b, _s, _f | CLK_ENABLE_REG_32BIT)
0131
0132 #define SH_CLK_MSTP16(_p, _r, _b, _f)               \
0133     SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_16BIT)
0134
0135 #define SH_CLK_MSTP8(_p, _r, _b, _f)                \
0136     SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_8BIT)
0137
0138 int sh_clk_mstp_register(struct clk *clks, int nr);
0139
0140 /*
0141  * MSTP registration never really cared about access size, despite the
0142  * original enable/disable pairs assuming a 32-bit access. Clocks are
0143  * responsible for defining their access sizes either directly or via the
0144  * clock definition wrappers.
0145  */
0146 static inline int __deprecated sh_clk_mstp32_register(struct clk *clks, int nr)
0147 {
0148     return sh_clk_mstp_register(clks, nr);
0149 }
0150
0151 #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \
0152 {                               \
0153     .parent = _parent,                  \
0154     .enable_reg = (void __iomem *)_reg,         \
0155     .enable_bit = _shift,                   \
0156     .arch_flags = _div_bitmap,              \
0157     .div_mask = SH_CLK_DIV4_MSK,                \
0158     .flags = _flags,                    \
0159 }
0160
0161 struct clk_div_table {
0162     struct clk_div_mult_table *div_mult_table;
0163     void (*kick)(struct clk *clk);
0164 };
0165
0166 #define clk_div4_table clk_div_table
0167
0168 int sh_clk_div4_register(struct clk *clks, int nr,
0169              struct clk_div4_table *table);
0170 int sh_clk_div4_enable_register(struct clk *clks, int nr,
0171              struct clk_div4_table *table);
0172 int sh_clk_div4_reparent_register(struct clk *clks, int nr,
0173              struct clk_div4_table *table);
0174
0175 #define SH_CLK_DIV6_EXT(_reg, _flags, _parents,         \
0176             _num_parents, _src_shift, _src_width)   \
0177 {                               \
0178     .enable_reg = (void __iomem *)_reg,         \
0179     .enable_bit = 0, /* unused */               \
0180     .flags = _flags | CLK_MASK_DIV_ON_DISABLE,      \
0181     .div_mask = SH_CLK_DIV6_MSK,                \
0182     .parent_table = _parents,               \
0183     .parent_num = _num_parents,             \
0184     .src_shift = _src_shift,                \
0185     .src_width = _src_width,                \
0186 }
0187
0188 #define SH_CLK_DIV6(_parent, _reg, _flags)          \
0189 {                               \
0190     .parent     = _parent,              \
0191     .enable_reg = (void __iomem *)_reg,         \
0192     .enable_bit = 0,    /* unused */            \
0193     .div_mask   = SH_CLK_DIV6_MSK,          \
0194     .flags      = _flags | CLK_MASK_DIV_ON_DISABLE, \
0195 }
0196
0197 int sh_clk_div6_register(struct clk *clks, int nr);
0198 int sh_clk_div6_reparent_register(struct clk *clks, int nr);
0199
0200 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
0201 #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
0202 #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
0203
0204 /* .enable_reg will be updated to .mapping on sh_clk_fsidiv_register() */
0205 #define SH_CLK_FSIDIV(_reg, _parent)        \
0206 {                       \
0207     .enable_reg = (void __iomem *)_reg, \
0208     .parent     = _parent,      \
0209 }
0210
0211 int sh_clk_fsidiv_register(struct clk *clks, int nr);
0212
0213 #endif /* __SH_CLOCK_H */