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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Driver for Realtek RTS5139 USB card reader
0003  *
0004  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
0005  *
0006  * Author:
0007  *   Roger Tseng <rogerable@realtek.com>
0008  */
0009 
0010 #ifndef __RTSX_USB_H
0011 #define __RTSX_USB_H
0012 
0013 #include <linux/usb.h>
0014 
0015 /* related module names */
0016 #define RTSX_USB_SD_CARD    0
0017 #define RTSX_USB_MS_CARD    1
0018 
0019 /* endpoint numbers */
0020 #define EP_BULK_OUT     1
0021 #define EP_BULK_IN      2
0022 #define EP_INTR_IN      3
0023 
0024 /* USB vendor requests */
0025 #define RTSX_USB_REQ_REG_OP 0x00
0026 #define RTSX_USB_REQ_POLL   0x02
0027 
0028 /* miscellaneous parameters */
0029 #define MIN_DIV_N       60
0030 #define MAX_DIV_N       120
0031 
0032 #define MAX_PHASE       15
0033 #define RX_TUNING_CNT       3
0034 
0035 #define QFN24           0
0036 #define LQFP48          1
0037 #define CHECK_PKG(ucr, pkg) ((ucr)->package == (pkg))
0038 
0039 /* data structures */
0040 struct rtsx_ucr {
0041     u16         vendor_id;
0042     u16         product_id;
0043 
0044     int         package;
0045     u8          ic_version;
0046     bool            is_rts5179;
0047 
0048     unsigned int        cur_clk;
0049 
0050     u8          *cmd_buf;
0051     unsigned int        cmd_idx;
0052     u8          *rsp_buf;
0053 
0054     struct usb_device   *pusb_dev;
0055     struct usb_interface    *pusb_intf;
0056     struct usb_sg_request   current_sg;
0057 
0058     struct timer_list   sg_timer;
0059     struct mutex        dev_mutex;
0060 };
0061 
0062 /* buffer size */
0063 #define IOBUF_SIZE      1024
0064 
0065 /* prototypes of exported functions */
0066 extern int rtsx_usb_get_card_status(struct rtsx_ucr *ucr, u16 *status);
0067 
0068 extern int rtsx_usb_read_register(struct rtsx_ucr *ucr, u16 addr, u8 *data);
0069 extern int rtsx_usb_write_register(struct rtsx_ucr *ucr, u16 addr, u8 mask,
0070         u8 data);
0071 
0072 extern int rtsx_usb_ep0_write_register(struct rtsx_ucr *ucr, u16 addr, u8 mask,
0073         u8 data);
0074 extern int rtsx_usb_ep0_read_register(struct rtsx_ucr *ucr, u16 addr,
0075         u8 *data);
0076 
0077 extern void rtsx_usb_add_cmd(struct rtsx_ucr *ucr, u8 cmd_type,
0078         u16 reg_addr, u8 mask, u8 data);
0079 extern int rtsx_usb_send_cmd(struct rtsx_ucr *ucr, u8 flag, int timeout);
0080 extern int rtsx_usb_get_rsp(struct rtsx_ucr *ucr, int rsp_len, int timeout);
0081 extern int rtsx_usb_transfer_data(struct rtsx_ucr *ucr, unsigned int pipe,
0082                   void *buf, unsigned int len, int use_sg,
0083                   unsigned int *act_len, int timeout);
0084 
0085 extern int rtsx_usb_read_ppbuf(struct rtsx_ucr *ucr, u8 *buf, int buf_len);
0086 extern int rtsx_usb_write_ppbuf(struct rtsx_ucr *ucr, u8 *buf, int buf_len);
0087 extern int rtsx_usb_switch_clock(struct rtsx_ucr *ucr, unsigned int card_clock,
0088         u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
0089 extern int rtsx_usb_card_exclusive_check(struct rtsx_ucr *ucr, int card);
0090 
0091 /* card status */
0092 #define SD_CD       0x01
0093 #define MS_CD       0x02
0094 #define XD_CD       0x04
0095 #define CD_MASK     (SD_CD | MS_CD | XD_CD)
0096 #define SD_WP       0x08
0097 
0098 /* reader command field offset & parameters */
0099 #define READ_REG_CMD        0
0100 #define WRITE_REG_CMD       1
0101 #define CHECK_REG_CMD       2
0102 
0103 #define PACKET_TYPE     4
0104 #define CNT_H           5
0105 #define CNT_L           6
0106 #define STAGE_FLAG      7
0107 #define CMD_OFFSET      8
0108 #define SEQ_WRITE_DATA_OFFSET   12
0109 
0110 #define BATCH_CMD       0
0111 #define SEQ_READ        1
0112 #define SEQ_WRITE       2
0113 
0114 #define STAGE_R         0x01
0115 #define STAGE_DI        0x02
0116 #define STAGE_DO        0x04
0117 #define STAGE_MS_STATUS     0x08
0118 #define STAGE_XD_STATUS     0x10
0119 #define MODE_C          0x00
0120 #define MODE_CR         (STAGE_R)
0121 #define MODE_CDIR       (STAGE_R | STAGE_DI)
0122 #define MODE_CDOR       (STAGE_R | STAGE_DO)
0123 
0124 #define EP0_OP_SHIFT        14
0125 #define EP0_READ_REG_CMD    2
0126 #define EP0_WRITE_REG_CMD   3
0127 
0128 #define rtsx_usb_cmd_hdr_tag(ucr)       \
0129     do {                    \
0130         ucr->cmd_buf[0] = 'R';      \
0131         ucr->cmd_buf[1] = 'T';      \
0132         ucr->cmd_buf[2] = 'C';      \
0133         ucr->cmd_buf[3] = 'R';      \
0134     } while (0)
0135 
0136 static inline void rtsx_usb_init_cmd(struct rtsx_ucr *ucr)
0137 {
0138     rtsx_usb_cmd_hdr_tag(ucr);
0139     ucr->cmd_idx = 0;
0140     ucr->cmd_buf[PACKET_TYPE] = BATCH_CMD;
0141 }
0142 
0143 /* internal register address */
0144 #define FPDCTL              0xFC00
0145 #define SSC_DIV_N_0         0xFC07
0146 #define SSC_CTL1            0xFC09
0147 #define SSC_CTL2            0xFC0A
0148 #define CFG_MODE            0xFC0E
0149 #define CFG_MODE_1          0xFC0F
0150 #define RCCTL               0xFC14
0151 #define SOF_WDOG            0xFC28
0152 #define SYS_DUMMY0          0xFC30
0153 
0154 #define MS_BLKEND           0xFD30
0155 #define MS_READ_START           0xFD31
0156 #define MS_READ_COUNT           0xFD32
0157 #define MS_WRITE_START          0xFD33
0158 #define MS_WRITE_COUNT          0xFD34
0159 #define MS_COMMAND          0xFD35
0160 #define MS_OLD_BLOCK_0          0xFD36
0161 #define MS_OLD_BLOCK_1          0xFD37
0162 #define MS_NEW_BLOCK_0          0xFD38
0163 #define MS_NEW_BLOCK_1          0xFD39
0164 #define MS_LOG_BLOCK_0          0xFD3A
0165 #define MS_LOG_BLOCK_1          0xFD3B
0166 #define MS_BUS_WIDTH            0xFD3C
0167 #define MS_PAGE_START           0xFD3D
0168 #define MS_PAGE_LENGTH          0xFD3E
0169 #define MS_CFG              0xFD40
0170 #define MS_TPC              0xFD41
0171 #define MS_TRANS_CFG            0xFD42
0172 #define MS_TRANSFER         0xFD43
0173 #define MS_INT_REG          0xFD44
0174 #define MS_BYTE_CNT         0xFD45
0175 #define MS_SECTOR_CNT_L         0xFD46
0176 #define MS_SECTOR_CNT_H         0xFD47
0177 #define MS_DBUS_H           0xFD48
0178 
0179 #define CARD_DMA1_CTL           0xFD5C
0180 #define CARD_PULL_CTL1          0xFD60
0181 #define CARD_PULL_CTL2          0xFD61
0182 #define CARD_PULL_CTL3          0xFD62
0183 #define CARD_PULL_CTL4          0xFD63
0184 #define CARD_PULL_CTL5          0xFD64
0185 #define CARD_PULL_CTL6          0xFD65
0186 #define CARD_EXIST          0xFD6F
0187 #define CARD_INT_PEND           0xFD71
0188 
0189 #define LDO_POWER_CFG           0xFD7B
0190 
0191 #define SD_CFG1             0xFDA0
0192 #define SD_CFG2             0xFDA1
0193 #define SD_CFG3             0xFDA2
0194 #define SD_STAT1            0xFDA3
0195 #define SD_STAT2            0xFDA4
0196 #define SD_BUS_STAT         0xFDA5
0197 #define SD_PAD_CTL          0xFDA6
0198 #define SD_SAMPLE_POINT_CTL     0xFDA7
0199 #define SD_PUSH_POINT_CTL       0xFDA8
0200 #define SD_CMD0             0xFDA9
0201 #define SD_CMD1             0xFDAA
0202 #define SD_CMD2             0xFDAB
0203 #define SD_CMD3             0xFDAC
0204 #define SD_CMD4             0xFDAD
0205 #define SD_CMD5             0xFDAE
0206 #define SD_BYTE_CNT_L           0xFDAF
0207 #define SD_BYTE_CNT_H           0xFDB0
0208 #define SD_BLOCK_CNT_L          0xFDB1
0209 #define SD_BLOCK_CNT_H          0xFDB2
0210 #define SD_TRANSFER         0xFDB3
0211 #define SD_CMD_STATE            0xFDB5
0212 #define SD_DATA_STATE           0xFDB6
0213 #define SD_VPCLK0_CTL           0xFC2A
0214 #define SD_VPCLK1_CTL           0xFC2B
0215 #define SD_DCMPS0_CTL           0xFC2C
0216 #define SD_DCMPS1_CTL           0xFC2D
0217 
0218 #define CARD_DMA1_CTL           0xFD5C
0219 
0220 #define HW_VERSION          0xFC01
0221 
0222 #define SSC_CLK_FPGA_SEL        0xFC02
0223 #define CLK_DIV             0xFC03
0224 #define SFSM_ED             0xFC04
0225 
0226 #define CD_DEGLITCH_WIDTH       0xFC20
0227 #define CD_DEGLITCH_EN          0xFC21
0228 #define AUTO_DELINK_EN          0xFC23
0229 
0230 #define FPGA_PULL_CTL           0xFC1D
0231 #define CARD_CLK_SOURCE         0xFC2E
0232 
0233 #define CARD_SHARE_MODE         0xFD51
0234 #define CARD_DRIVE_SEL          0xFD52
0235 #define CARD_STOP           0xFD53
0236 #define CARD_OE             0xFD54
0237 #define CARD_AUTO_BLINK         0xFD55
0238 #define CARD_GPIO           0xFD56
0239 #define SD30_DRIVE_SEL          0xFD57
0240 
0241 #define CARD_DATA_SOURCE        0xFD5D
0242 #define CARD_SELECT         0xFD5E
0243 
0244 #define CARD_CLK_EN         0xFD79
0245 #define CARD_PWR_CTL            0xFD7A
0246 
0247 #define OCPCTL              0xFD80
0248 #define OCPPARA1            0xFD81
0249 #define OCPPARA2            0xFD82
0250 #define OCPSTAT             0xFD83
0251 
0252 #define HS_USB_STAT         0xFE01
0253 #define HS_VCONTROL         0xFE26
0254 #define HS_VSTAIN           0xFE27
0255 #define HS_VLOADM           0xFE28
0256 #define HS_VSTAOUT          0xFE29
0257 
0258 #define MC_IRQ              0xFF00
0259 #define MC_IRQEN            0xFF01
0260 #define MC_FIFO_CTL         0xFF02
0261 #define MC_FIFO_BC0         0xFF03
0262 #define MC_FIFO_BC1         0xFF04
0263 #define MC_FIFO_STAT            0xFF05
0264 #define MC_FIFO_MODE            0xFF06
0265 #define MC_FIFO_RD_PTR0         0xFF07
0266 #define MC_FIFO_RD_PTR1         0xFF08
0267 #define MC_DMA_CTL          0xFF10
0268 #define MC_DMA_TC0          0xFF11
0269 #define MC_DMA_TC1          0xFF12
0270 #define MC_DMA_TC2          0xFF13
0271 #define MC_DMA_TC3          0xFF14
0272 #define MC_DMA_RST          0xFF15
0273 
0274 #define RBUF_SIZE_MASK          0xFBFF
0275 #define RBUF_BASE           0xF000
0276 #define PPBUF_BASE1         0xF800
0277 #define PPBUF_BASE2         0xFA00
0278 
0279 /* internal register value macros */
0280 #define POWER_OFF           0x03
0281 #define PARTIAL_POWER_ON        0x02
0282 #define POWER_ON            0x00
0283 #define POWER_MASK          0x03
0284 #define LDO3318_PWR_MASK        0x0C
0285 #define LDO_ON              0x00
0286 #define LDO_SUSPEND         0x08
0287 #define LDO_OFF             0x0C
0288 #define DV3318_AUTO_PWR_OFF     0x10
0289 #define FORCE_LDO_POWERB        0x60
0290 
0291 /* LDO_POWER_CFG */
0292 #define TUNE_SD18_MASK          0x1C
0293 #define TUNE_SD18_1V7           0x00
0294 #define TUNE_SD18_1V8           (0x01 << 2)
0295 #define TUNE_SD18_1V9           (0x02 << 2)
0296 #define TUNE_SD18_2V0           (0x03 << 2)
0297 #define TUNE_SD18_2V7           (0x04 << 2)
0298 #define TUNE_SD18_2V8           (0x05 << 2)
0299 #define TUNE_SD18_2V9           (0x06 << 2)
0300 #define TUNE_SD18_3V3           (0x07 << 2)
0301 
0302 /* CLK_DIV */
0303 #define CLK_CHANGE          0x80
0304 #define CLK_DIV_1           0x00
0305 #define CLK_DIV_2           0x01
0306 #define CLK_DIV_4           0x02
0307 #define CLK_DIV_8           0x03
0308 
0309 #define SSC_POWER_MASK          0x01
0310 #define SSC_POWER_DOWN          0x01
0311 #define SSC_POWER_ON            0x00
0312 
0313 #define FPGA_VER            0x80
0314 #define HW_VER_MASK         0x0F
0315 
0316 #define EXTEND_DMA1_ASYNC_SIGNAL    0x02
0317 
0318 /* CFG_MODE*/
0319 #define XTAL_FREE           0x80
0320 #define CLK_MODE_MASK           0x03
0321 #define CLK_MODE_12M_XTAL       0x00
0322 #define CLK_MODE_NON_XTAL       0x01
0323 #define CLK_MODE_24M_OSC        0x02
0324 #define CLK_MODE_48M_OSC        0x03
0325 
0326 /* CFG_MODE_1*/
0327 #define RTS5179             0x02
0328 
0329 #define NYET_EN             0x01
0330 #define NYET_MSAK           0x01
0331 
0332 #define SD30_DRIVE_MASK         0x07
0333 #define SD20_DRIVE_MASK         0x03
0334 
0335 #define DISABLE_SD_CD           0x08
0336 #define DISABLE_MS_CD           0x10
0337 #define DISABLE_XD_CD           0x20
0338 #define SD_CD_DEGLITCH_EN       0x01
0339 #define MS_CD_DEGLITCH_EN       0x02
0340 #define XD_CD_DEGLITCH_EN       0x04
0341 
0342 #define CARD_SHARE_LQFP48       0x04
0343 #define CARD_SHARE_QFN24        0x00
0344 #define CARD_SHARE_LQFP_SEL     0x04
0345 #define CARD_SHARE_XD           0x00
0346 #define CARD_SHARE_SD           0x01
0347 #define CARD_SHARE_MS           0x02
0348 #define CARD_SHARE_MASK         0x03
0349 
0350 
0351 /* SD30_DRIVE_SEL */
0352 #define DRIVER_TYPE_A           0x05
0353 #define DRIVER_TYPE_B           0x03
0354 #define DRIVER_TYPE_C           0x02
0355 #define DRIVER_TYPE_D           0x01
0356 
0357 /* SD_BUS_STAT */
0358 #define SD_CLK_TOGGLE_EN        0x80
0359 #define SD_CLK_FORCE_STOP           0x40
0360 #define SD_DAT3_STATUS              0x10
0361 #define SD_DAT2_STATUS              0x08
0362 #define SD_DAT1_STATUS              0x04
0363 #define SD_DAT0_STATUS              0x02
0364 #define SD_CMD_STATUS           0x01
0365 
0366 /* SD_PAD_CTL */
0367 #define SD_IO_USING_1V8             0x80
0368 #define SD_IO_USING_3V3             0x7F
0369 #define TYPE_A_DRIVING              0x00
0370 #define TYPE_B_DRIVING          0x01
0371 #define TYPE_C_DRIVING          0x02
0372 #define TYPE_D_DRIVING              0x03
0373 
0374 /* CARD_CLK_EN */
0375 #define SD_CLK_EN           0x04
0376 #define MS_CLK_EN           0x08
0377 
0378 /* CARD_SELECT */
0379 #define SD_MOD_SEL          2
0380 #define MS_MOD_SEL          3
0381 
0382 /* CARD_SHARE_MODE */
0383 #define CARD_SHARE_LQFP48       0x04
0384 #define CARD_SHARE_QFN24        0x00
0385 #define CARD_SHARE_LQFP_SEL     0x04
0386 #define CARD_SHARE_XD           0x00
0387 #define CARD_SHARE_SD           0x01
0388 #define CARD_SHARE_MS           0x02
0389 #define CARD_SHARE_MASK         0x03
0390 
0391 /* SSC_CTL1 */
0392 #define SSC_RSTB            0x80
0393 #define SSC_8X_EN           0x40
0394 #define SSC_FIX_FRAC            0x20
0395 #define SSC_SEL_1M          0x00
0396 #define SSC_SEL_2M          0x08
0397 #define SSC_SEL_4M          0x10
0398 #define SSC_SEL_8M          0x18
0399 
0400 /* SSC_CTL2 */
0401 #define SSC_DEPTH_MASK          0x03
0402 #define SSC_DEPTH_DISALBE       0x00
0403 #define SSC_DEPTH_2M            0x01
0404 #define SSC_DEPTH_1M            0x02
0405 #define SSC_DEPTH_512K          0x03
0406 
0407 /* SD_VPCLK0_CTL */
0408 #define PHASE_CHANGE            0x80
0409 #define PHASE_NOT_RESET         0x40
0410 
0411 /* SD_TRANSFER */
0412 #define SD_TRANSFER_START       0x80
0413 #define SD_TRANSFER_END         0x40
0414 #define SD_STAT_IDLE            0x20
0415 #define SD_TRANSFER_ERR         0x10
0416 #define SD_TM_NORMAL_WRITE      0x00
0417 #define SD_TM_AUTO_WRITE_3      0x01
0418 #define SD_TM_AUTO_WRITE_4      0x02
0419 #define SD_TM_AUTO_READ_3       0x05
0420 #define SD_TM_AUTO_READ_4       0x06
0421 #define SD_TM_CMD_RSP           0x08
0422 #define SD_TM_AUTO_WRITE_1      0x09
0423 #define SD_TM_AUTO_WRITE_2      0x0A
0424 #define SD_TM_NORMAL_READ       0x0C
0425 #define SD_TM_AUTO_READ_1       0x0D
0426 #define SD_TM_AUTO_READ_2       0x0E
0427 #define SD_TM_AUTO_TUNING       0x0F
0428 
0429 /* SD_CFG1 */
0430 #define SD_CLK_DIVIDE_0         0x00
0431 #define SD_CLK_DIVIDE_256       0xC0
0432 #define SD_CLK_DIVIDE_128       0x80
0433 #define SD_CLK_DIVIDE_MASK      0xC0
0434 #define SD_BUS_WIDTH_1BIT       0x00
0435 #define SD_BUS_WIDTH_4BIT       0x01
0436 #define SD_BUS_WIDTH_8BIT       0x02
0437 #define SD_ASYNC_FIFO_RST       0x10
0438 #define SD_20_MODE          0x00
0439 #define SD_DDR_MODE         0x04
0440 #define SD_30_MODE          0x08
0441 
0442 /* SD_CFG2 */
0443 #define SD_CALCULATE_CRC7       0x00
0444 #define SD_NO_CALCULATE_CRC7        0x80
0445 #define SD_CHECK_CRC16          0x00
0446 #define SD_NO_CHECK_CRC16       0x40
0447 #define SD_WAIT_CRC_TO_EN       0x20
0448 #define SD_WAIT_BUSY_END        0x08
0449 #define SD_NO_WAIT_BUSY_END     0x00
0450 #define SD_CHECK_CRC7           0x00
0451 #define SD_NO_CHECK_CRC7        0x04
0452 #define SD_RSP_LEN_0            0x00
0453 #define SD_RSP_LEN_6            0x01
0454 #define SD_RSP_LEN_17           0x02
0455 #define SD_RSP_TYPE_R0          0x04
0456 #define SD_RSP_TYPE_R1          0x01
0457 #define SD_RSP_TYPE_R1b         0x09
0458 #define SD_RSP_TYPE_R2          0x02
0459 #define SD_RSP_TYPE_R3          0x05
0460 #define SD_RSP_TYPE_R4          0x05
0461 #define SD_RSP_TYPE_R5          0x01
0462 #define SD_RSP_TYPE_R6          0x01
0463 #define SD_RSP_TYPE_R7          0x01
0464 
0465 /* SD_STAT1 */
0466 #define SD_CRC7_ERR         0x80
0467 #define SD_CRC16_ERR            0x40
0468 #define SD_CRC_WRITE_ERR        0x20
0469 #define SD_CRC_WRITE_ERR_MASK       0x1C
0470 #define GET_CRC_TIME_OUT        0x02
0471 #define SD_TUNING_COMPARE_ERR       0x01
0472 
0473 /* SD_DATA_STATE */
0474 #define SD_DATA_IDLE            0x80
0475 
0476 /* CARD_DATA_SOURCE */
0477 #define PINGPONG_BUFFER         0x01
0478 #define RING_BUFFER         0x00
0479 
0480 /* CARD_OE */
0481 #define SD_OUTPUT_EN            0x04
0482 #define MS_OUTPUT_EN            0x08
0483 
0484 /* CARD_STOP */
0485 #define SD_STOP             0x04
0486 #define MS_STOP             0x08
0487 #define SD_CLR_ERR          0x40
0488 #define MS_CLR_ERR          0x80
0489 
0490 /* CARD_CLK_SOURCE */
0491 #define CRC_FIX_CLK         (0x00 << 0)
0492 #define CRC_VAR_CLK0            (0x01 << 0)
0493 #define CRC_VAR_CLK1            (0x02 << 0)
0494 #define SD30_FIX_CLK            (0x00 << 2)
0495 #define SD30_VAR_CLK0           (0x01 << 2)
0496 #define SD30_VAR_CLK1           (0x02 << 2)
0497 #define SAMPLE_FIX_CLK          (0x00 << 4)
0498 #define SAMPLE_VAR_CLK0         (0x01 << 4)
0499 #define SAMPLE_VAR_CLK1         (0x02 << 4)
0500 
0501 /* SD_SAMPLE_POINT_CTL */
0502 #define DDR_FIX_RX_DAT          0x00
0503 #define DDR_VAR_RX_DAT          0x80
0504 #define DDR_FIX_RX_DAT_EDGE     0x00
0505 #define DDR_FIX_RX_DAT_14_DELAY     0x40
0506 #define DDR_FIX_RX_CMD          0x00
0507 #define DDR_VAR_RX_CMD          0x20
0508 #define DDR_FIX_RX_CMD_POS_EDGE     0x00
0509 #define DDR_FIX_RX_CMD_14_DELAY     0x10
0510 #define SD20_RX_POS_EDGE        0x00
0511 #define SD20_RX_14_DELAY        0x08
0512 #define SD20_RX_SEL_MASK        0x08
0513 
0514 /* SD_PUSH_POINT_CTL */
0515 #define DDR_FIX_TX_CMD_DAT      0x00
0516 #define DDR_VAR_TX_CMD_DAT      0x80
0517 #define DDR_FIX_TX_DAT_14_TSU       0x00
0518 #define DDR_FIX_TX_DAT_12_TSU       0x40
0519 #define DDR_FIX_TX_CMD_NEG_EDGE     0x00
0520 #define DDR_FIX_TX_CMD_14_AHEAD     0x20
0521 #define SD20_TX_NEG_EDGE        0x00
0522 #define SD20_TX_14_AHEAD        0x10
0523 #define SD20_TX_SEL_MASK        0x10
0524 #define DDR_VAR_SDCLK_POL_SWAP      0x01
0525 
0526 /* MS_CFG */
0527 #define SAMPLE_TIME_RISING      0x00
0528 #define SAMPLE_TIME_FALLING     0x80
0529 #define PUSH_TIME_DEFAULT       0x00
0530 #define PUSH_TIME_ODD           0x40
0531 #define NO_EXTEND_TOGGLE        0x00
0532 #define EXTEND_TOGGLE_CHK       0x20
0533 #define MS_BUS_WIDTH_1          0x00
0534 #define MS_BUS_WIDTH_4          0x10
0535 #define MS_BUS_WIDTH_8          0x18
0536 #define MS_2K_SECTOR_MODE       0x04
0537 #define MS_512_SECTOR_MODE      0x00
0538 #define MS_TOGGLE_TIMEOUT_EN        0x00
0539 #define MS_TOGGLE_TIMEOUT_DISEN     0x01
0540 #define MS_NO_CHECK_INT         0x02
0541 
0542 /* MS_TRANS_CFG */
0543 #define WAIT_INT            0x80
0544 #define NO_WAIT_INT         0x00
0545 #define NO_AUTO_READ_INT_REG        0x00
0546 #define AUTO_READ_INT_REG       0x40
0547 #define MS_CRC16_ERR            0x20
0548 #define MS_RDY_TIMEOUT          0x10
0549 #define MS_INT_CMDNK            0x08
0550 #define MS_INT_BREQ         0x04
0551 #define MS_INT_ERR          0x02
0552 #define MS_INT_CED          0x01
0553 
0554 /* MS_TRANSFER */
0555 #define MS_TRANSFER_START       0x80
0556 #define MS_TRANSFER_END         0x40
0557 #define MS_TRANSFER_ERR         0x20
0558 #define MS_BS_STATE         0x10
0559 #define MS_TM_READ_BYTES        0x00
0560 #define MS_TM_NORMAL_READ       0x01
0561 #define MS_TM_WRITE_BYTES       0x04
0562 #define MS_TM_NORMAL_WRITE      0x05
0563 #define MS_TM_AUTO_READ         0x08
0564 #define MS_TM_AUTO_WRITE        0x0C
0565 #define MS_TM_SET_CMD           0x06
0566 #define MS_TM_COPY_PAGE         0x07
0567 #define MS_TM_MULTI_READ        0x02
0568 #define MS_TM_MULTI_WRITE       0x03
0569 
0570 /* MC_FIFO_CTL */
0571 #define FIFO_FLUSH          0x01
0572 
0573 /* MC_DMA_RST */
0574 #define DMA_RESET  0x01
0575 
0576 /* MC_DMA_CTL */
0577 #define DMA_TC_EQ_0         0x80
0578 #define DMA_DIR_TO_CARD         0x00
0579 #define DMA_DIR_FROM_CARD       0x02
0580 #define DMA_EN              0x01
0581 #define DMA_128             (0 << 2)
0582 #define DMA_256             (1 << 2)
0583 #define DMA_512             (2 << 2)
0584 #define DMA_1024            (3 << 2)
0585 #define DMA_PACK_SIZE_MASK      0x0C
0586 
0587 /* CARD_INT_PEND */
0588 #define XD_INT              0x10
0589 #define MS_INT              0x08
0590 #define SD_INT              0x04
0591 
0592 /* LED operations*/
0593 static inline int rtsx_usb_turn_on_led(struct rtsx_ucr *ucr)
0594 {
0595     return  rtsx_usb_ep0_write_register(ucr, CARD_GPIO, 0x03, 0x02);
0596 }
0597 
0598 static inline int rtsx_usb_turn_off_led(struct rtsx_ucr *ucr)
0599 {
0600     return rtsx_usb_ep0_write_register(ucr, CARD_GPIO, 0x03, 0x03);
0601 }
0602 
0603 /* HW error clearing */
0604 static inline void rtsx_usb_clear_fsm_err(struct rtsx_ucr *ucr)
0605 {
0606     rtsx_usb_ep0_write_register(ucr, SFSM_ED, 0xf8, 0xf8);
0607 }
0608 
0609 static inline void rtsx_usb_clear_dma_err(struct rtsx_ucr *ucr)
0610 {
0611     rtsx_usb_ep0_write_register(ucr, MC_FIFO_CTL,
0612             FIFO_FLUSH, FIFO_FLUSH);
0613     rtsx_usb_ep0_write_register(ucr, MC_DMA_RST, DMA_RESET, DMA_RESET);
0614 }
0615 #endif /* __RTS51139_H */
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