linux/reset/reset-simple.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Simple Reset Controller ops
0004  *
0005  * Based on Allwinner SoCs Reset Controller driver
0006  *
0007  * Copyright 2013 Maxime Ripard
0008  *
0009  * Maxime Ripard <maxime.ripard@free-electrons.com>
0010  */
0011
0012 #ifndef __RESET_SIMPLE_H__
0013 #define __RESET_SIMPLE_H__
0014
0015 #include <linux/io.h>
0016 #include <linux/reset-controller.h>
0017 #include <linux/spinlock.h>
0018
0019 /**
0020  * struct reset_simple_data - driver data for simple reset controllers
0021  * @lock: spinlock to protect registers during read-modify-write cycles
0022  * @membase: memory mapped I/O register range
0023  * @rcdev: reset controller device base structure
0024  * @active_low: if true, bits are cleared to assert the reset. Otherwise, bits
0025  *              are set to assert the reset. Note that this says nothing about
0026  *              the voltage level of the actual reset line.
0027  * @status_active_low: if true, bits read back as cleared while the reset is
0028  *                     asserted. Otherwise, bits read back as set while the
0029  *                     reset is asserted.
0030  * @reset_us: Minimum delay in microseconds needed that needs to be
0031  *            waited for between an assert and a deassert to reset the
0032  *            device. If multiple consumers with different delay
0033  *            requirements are connected to this controller, it must
0034  *            be the largest minimum delay. 0 means that such a delay is
0035  *            unknown and the reset operation is unsupported.
0036  */
0037 struct reset_simple_data {
0038     spinlock_t          lock;
0039     void __iomem            *membase;
0040     struct reset_controller_dev rcdev;
0041     bool                active_low;
0042     bool                status_active_low;
0043     unsigned int            reset_us;
0044 };
0045
0046 extern const struct reset_control_ops reset_simple_ops;
0047
0048 #endif /* __RESET_SIMPLE_H__ */