linux/regulator/pca9450.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /* Copyright 2020 NXP. */
0003
0004 #ifndef __LINUX_REG_PCA9450_H__
0005 #define __LINUX_REG_PCA9450_H__
0006
0007 #include <linux/regmap.h>
0008
0009 enum pca9450_chip_type {
0010     PCA9450_TYPE_PCA9450A = 0,
0011     PCA9450_TYPE_PCA9450BC,
0012     PCA9450_TYPE_AMOUNT,
0013 };
0014
0015 enum {
0016     PCA9450_BUCK1 = 0,
0017     PCA9450_BUCK2,
0018     PCA9450_BUCK3,
0019     PCA9450_BUCK4,
0020     PCA9450_BUCK5,
0021     PCA9450_BUCK6,
0022     PCA9450_LDO1,
0023     PCA9450_LDO2,
0024     PCA9450_LDO3,
0025     PCA9450_LDO4,
0026     PCA9450_LDO5,
0027     PCA9450_REGULATOR_CNT,
0028 };
0029
0030 enum {
0031     PCA9450_DVS_LEVEL_RUN = 0,
0032     PCA9450_DVS_LEVEL_STANDBY,
0033     PCA9450_DVS_LEVEL_MAX,
0034 };
0035
0036 #define PCA9450_BUCK1_VOLTAGE_NUM   0x80
0037 #define PCA9450_BUCK2_VOLTAGE_NUM   0x80
0038 #define PCA9450_BUCK3_VOLTAGE_NUM   0x80
0039 #define PCA9450_BUCK4_VOLTAGE_NUM   0x80
0040
0041 #define PCA9450_BUCK5_VOLTAGE_NUM   0x80
0042 #define PCA9450_BUCK6_VOLTAGE_NUM   0x80
0043
0044 #define PCA9450_LDO1_VOLTAGE_NUM    0x08
0045 #define PCA9450_LDO2_VOLTAGE_NUM    0x08
0046 #define PCA9450_LDO3_VOLTAGE_NUM    0x20
0047 #define PCA9450_LDO4_VOLTAGE_NUM    0x20
0048 #define PCA9450_LDO5_VOLTAGE_NUM    0x10
0049
0050 enum {
0051     PCA9450_REG_DEV_ID      = 0x00,
0052     PCA9450_REG_INT1        = 0x01,
0053     PCA9450_REG_INT1_MSK        = 0x02,
0054     PCA9450_REG_STATUS1     = 0x03,
0055     PCA9450_REG_STATUS2     = 0x04,
0056     PCA9450_REG_PWRON_STAT      = 0x05,
0057     PCA9450_REG_SWRST       = 0x06,
0058     PCA9450_REG_PWRCTRL         = 0x07,
0059     PCA9450_REG_RESET_CTRL      = 0x08,
0060     PCA9450_REG_CONFIG1         = 0x09,
0061     PCA9450_REG_CONFIG2         = 0x0A,
0062     PCA9450_REG_BUCK123_DVS     = 0x0C,
0063     PCA9450_REG_BUCK1OUT_LIMIT  = 0x0D,
0064     PCA9450_REG_BUCK2OUT_LIMIT  = 0x0E,
0065     PCA9450_REG_BUCK3OUT_LIMIT  = 0x0F,
0066     PCA9450_REG_BUCK1CTRL       = 0x10,
0067     PCA9450_REG_BUCK1OUT_DVS0   = 0x11,
0068     PCA9450_REG_BUCK1OUT_DVS1   = 0x12,
0069     PCA9450_REG_BUCK2CTRL       = 0x13,
0070     PCA9450_REG_BUCK2OUT_DVS0   = 0x14,
0071     PCA9450_REG_BUCK2OUT_DVS1   = 0x15,
0072     PCA9450_REG_BUCK3CTRL       = 0x16,
0073     PCA9450_REG_BUCK3OUT_DVS0   = 0x17,
0074     PCA9450_REG_BUCK3OUT_DVS1   = 0x18,
0075     PCA9450_REG_BUCK4CTRL       = 0x19,
0076     PCA9450_REG_BUCK4OUT        = 0x1A,
0077     PCA9450_REG_BUCK5CTRL       = 0x1B,
0078     PCA9450_REG_BUCK5OUT        = 0x1C,
0079     PCA9450_REG_BUCK6CTRL       = 0x1D,
0080     PCA9450_REG_BUCK6OUT        = 0x1E,
0081     PCA9450_REG_LDO_AD_CTRL     = 0x20,
0082     PCA9450_REG_LDO1CTRL        = 0x21,
0083     PCA9450_REG_LDO2CTRL        = 0x22,
0084     PCA9450_REG_LDO3CTRL        = 0x23,
0085     PCA9450_REG_LDO4CTRL        = 0x24,
0086     PCA9450_REG_LDO5CTRL_L      = 0x25,
0087     PCA9450_REG_LDO5CTRL_H      = 0x26,
0088     PCA9450_REG_LOADSW_CTRL     = 0x2A,
0089     PCA9450_REG_VRFLT1_STS      = 0x2B,
0090     PCA9450_REG_VRFLT2_STS      = 0x2C,
0091     PCA9450_REG_VRFLT1_MASK     = 0x2D,
0092     PCA9450_REG_VRFLT2_MASK     = 0x2E,
0093     PCA9450_MAX_REGISTER        = 0x2F,
0094 };
0095
0096 /* PCA9450 BUCK ENMODE bits */
0097 #define BUCK_ENMODE_OFF         0x00
0098 #define BUCK_ENMODE_ONREQ       0x01
0099 #define BUCK_ENMODE_ONREQ_STBYREQ   0x02
0100 #define BUCK_ENMODE_ON          0x03
0101
0102 /* PCA9450_REG_BUCK1_CTRL bits */
0103 #define BUCK1_RAMP_MASK         0xC0
0104 #define BUCK1_RAMP_25MV         0x0
0105 #define BUCK1_RAMP_12P5MV       0x1
0106 #define BUCK1_RAMP_6P25MV       0x2
0107 #define BUCK1_RAMP_3P125MV      0x3
0108 #define BUCK1_DVS_CTRL          0x10
0109 #define BUCK1_AD            0x08
0110 #define BUCK1_FPWM          0x04
0111 #define BUCK1_ENMODE_MASK       0x03
0112
0113 /* PCA9450_REG_BUCK2_CTRL bits */
0114 #define BUCK2_RAMP_MASK         0xC0
0115 #define BUCK2_RAMP_25MV         0x0
0116 #define BUCK2_RAMP_12P5MV       0x1
0117 #define BUCK2_RAMP_6P25MV       0x2
0118 #define BUCK2_RAMP_3P125MV      0x3
0119 #define BUCK2_DVS_CTRL          0x10
0120 #define BUCK2_AD            0x08
0121 #define BUCK2_FPWM          0x04
0122 #define BUCK2_ENMODE_MASK       0x03
0123
0124 /* PCA9450_REG_BUCK3_CTRL bits */
0125 #define BUCK3_RAMP_MASK         0xC0
0126 #define BUCK3_RAMP_25MV         0x0
0127 #define BUCK3_RAMP_12P5MV       0x1
0128 #define BUCK3_RAMP_6P25MV       0x2
0129 #define BUCK3_RAMP_3P125MV      0x3
0130 #define BUCK3_DVS_CTRL          0x10
0131 #define BUCK3_AD            0x08
0132 #define BUCK3_FPWM          0x04
0133 #define BUCK3_ENMODE_MASK       0x03
0134
0135 /* PCA9450_REG_BUCK4_CTRL bits */
0136 #define BUCK4_AD            0x08
0137 #define BUCK4_FPWM          0x04
0138 #define BUCK4_ENMODE_MASK       0x03
0139
0140 /* PCA9450_REG_BUCK5_CTRL bits */
0141 #define BUCK5_AD            0x08
0142 #define BUCK5_FPWM          0x04
0143 #define BUCK5_ENMODE_MASK       0x03
0144
0145 /* PCA9450_REG_BUCK6_CTRL bits */
0146 #define BUCK6_AD            0x08
0147 #define BUCK6_FPWM          0x04
0148 #define BUCK6_ENMODE_MASK       0x03
0149
0150 /* PCA9450_REG_BUCK123_PRESET_EN bit */
0151 #define BUCK123_PRESET_EN       0x80
0152
0153 /* PCA9450_BUCK1OUT_DVS0 bits */
0154 #define BUCK1OUT_DVS0_MASK      0x7F
0155 #define BUCK1OUT_DVS0_DEFAULT       0x14
0156
0157 /* PCA9450_BUCK1OUT_DVS1 bits */
0158 #define BUCK1OUT_DVS1_MASK      0x7F
0159 #define BUCK1OUT_DVS1_DEFAULT       0x14
0160
0161 /* PCA9450_BUCK2OUT_DVS0 bits */
0162 #define BUCK2OUT_DVS0_MASK      0x7F
0163 #define BUCK2OUT_DVS0_DEFAULT       0x14
0164
0165 /* PCA9450_BUCK2OUT_DVS1 bits */
0166 #define BUCK2OUT_DVS1_MASK      0x7F
0167 #define BUCK2OUT_DVS1_DEFAULT       0x14
0168
0169 /* PCA9450_BUCK3OUT_DVS0 bits */
0170 #define BUCK3OUT_DVS0_MASK      0x7F
0171 #define BUCK3OUT_DVS0_DEFAULT       0x14
0172
0173 /* PCA9450_BUCK3OUT_DVS1 bits */
0174 #define BUCK3OUT_DVS1_MASK      0x7F
0175 #define BUCK3OUT_DVS1_DEFAULT       0x14
0176
0177 /* PCA9450_REG_BUCK4OUT bits */
0178 #define BUCK4OUT_MASK           0x7F
0179 #define BUCK4OUT_DEFAULT        0x6C
0180
0181 /* PCA9450_REG_BUCK5OUT bits */
0182 #define BUCK5OUT_MASK           0x7F
0183 #define BUCK5OUT_DEFAULT        0x30
0184
0185 /* PCA9450_REG_BUCK6OUT bits */
0186 #define BUCK6OUT_MASK           0x7F
0187 #define BUCK6OUT_DEFAULT        0x14
0188
0189 /* PCA9450_REG_LDO1_VOLT bits */
0190 #define LDO1_EN_MASK            0xC0
0191 #define LDO1OUT_MASK            0x07
0192
0193 /* PCA9450_REG_LDO2_VOLT bits */
0194 #define LDO2_EN_MASK            0xC0
0195 #define LDO2OUT_MASK            0x07
0196
0197 /* PCA9450_REG_LDO3_VOLT bits */
0198 #define LDO3_EN_MASK            0xC0
0199 #define LDO3OUT_MASK            0x0F
0200
0201 /* PCA9450_REG_LDO4_VOLT bits */
0202 #define LDO4_EN_MASK            0xC0
0203 #define LDO4OUT_MASK            0x0F
0204
0205 /* PCA9450_REG_LDO5_VOLT bits */
0206 #define LDO5L_EN_MASK           0xC0
0207 #define LDO5LOUT_MASK           0x0F
0208
0209 #define LDO5H_EN_MASK           0xC0
0210 #define LDO5HOUT_MASK           0x0F
0211
0212 /* PCA9450_REG_IRQ bits */
0213 #define IRQ_PWRON           0x80
0214 #define IRQ_WDOGB           0x40
0215 #define IRQ_RSVD            0x20
0216 #define IRQ_VR_FLT1         0x10
0217 #define IRQ_VR_FLT2         0x08
0218 #define IRQ_LOWVSYS         0x04
0219 #define IRQ_THERM_105           0x02
0220 #define IRQ_THERM_125           0x01
0221
0222 /* PCA9450_REG_RESET_CTRL bits */
0223 #define WDOG_B_CFG_MASK         0xC0
0224 #define WDOG_B_CFG_NONE         0x00
0225 #define WDOG_B_CFG_WARM         0x40
0226 #define WDOG_B_CFG_COLD_LDO12       0x80
0227 #define WDOG_B_CFG_COLD         0xC0
0228
0229 /* PCA9450_REG_CONFIG2 bits */
0230 #define I2C_LT_MASK         0x03
0231 #define I2C_LT_FORCE_DISABLE        0x00
0232 #define I2C_LT_ON_STANDBY_RUN       0x01
0233 #define I2C_LT_ON_RUN           0x02
0234 #define I2C_LT_FORCE_ENABLE     0x03
0235
0236 #endif /* __LINUX_REG_PCA9450_H__ */