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0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
0002 /* QLogic qed NIC Driver
0003  * Copyright (c) 2015-2017  QLogic Corporation
0004  * Copyright (c) 2019-2020 Marvell International Ltd.
0005  */
0006 
0007 #ifndef _QED_RDMA_IF_H
0008 #define _QED_RDMA_IF_H
0009 #include <linux/types.h>
0010 #include <linux/delay.h>
0011 #include <linux/list.h>
0012 #include <linux/slab.h>
0013 #include <linux/qed/qed_if.h>
0014 #include <linux/qed/qed_ll2_if.h>
0015 #include <linux/qed/rdma_common.h>
0016 
0017 #define QED_RDMA_MAX_CNQ_SIZE               (0xFFFF)
0018 
0019 /* rdma interface */
0020 
0021 enum qed_roce_qp_state {
0022     QED_ROCE_QP_STATE_RESET,
0023     QED_ROCE_QP_STATE_INIT,
0024     QED_ROCE_QP_STATE_RTR,
0025     QED_ROCE_QP_STATE_RTS,
0026     QED_ROCE_QP_STATE_SQD,
0027     QED_ROCE_QP_STATE_ERR,
0028     QED_ROCE_QP_STATE_SQE
0029 };
0030 
0031 enum qed_rdma_qp_type {
0032     QED_RDMA_QP_TYPE_RC,
0033     QED_RDMA_QP_TYPE_XRC_INI,
0034     QED_RDMA_QP_TYPE_XRC_TGT,
0035     QED_RDMA_QP_TYPE_INVAL = 0xffff,
0036 };
0037 
0038 enum qed_rdma_tid_type {
0039     QED_RDMA_TID_REGISTERED_MR,
0040     QED_RDMA_TID_FMR,
0041     QED_RDMA_TID_MW
0042 };
0043 
0044 struct qed_rdma_events {
0045     void *context;
0046     void (*affiliated_event)(void *context, u8 fw_event_code,
0047                  void *fw_handle);
0048     void (*unaffiliated_event)(void *context, u8 event_code);
0049 };
0050 
0051 struct qed_rdma_device {
0052     u32 vendor_id;
0053     u32 vendor_part_id;
0054     u32 hw_ver;
0055     u64 fw_ver;
0056 
0057     u64 node_guid;
0058     u64 sys_image_guid;
0059 
0060     u8 max_cnq;
0061     u8 max_sge;
0062     u8 max_srq_sge;
0063     u16 max_inline;
0064     u32 max_wqe;
0065     u32 max_srq_wqe;
0066     u8 max_qp_resp_rd_atomic_resc;
0067     u8 max_qp_req_rd_atomic_resc;
0068     u64 max_dev_resp_rd_atomic_resc;
0069     u32 max_cq;
0070     u32 max_qp;
0071     u32 max_srq;
0072     u32 max_mr;
0073     u64 max_mr_size;
0074     u32 max_cqe;
0075     u32 max_mw;
0076     u32 max_mr_mw_fmr_pbl;
0077     u64 max_mr_mw_fmr_size;
0078     u32 max_pd;
0079     u32 max_ah;
0080     u8 max_pkey;
0081     u16 max_srq_wr;
0082     u8 max_stats_queues;
0083     u32 dev_caps;
0084 
0085     /* Abilty to support RNR-NAK generation */
0086 
0087 #define QED_RDMA_DEV_CAP_RNR_NAK_MASK                           0x1
0088 #define QED_RDMA_DEV_CAP_RNR_NAK_SHIFT                  0
0089     /* Abilty to support shutdown port */
0090 #define QED_RDMA_DEV_CAP_SHUTDOWN_PORT_MASK                     0x1
0091 #define QED_RDMA_DEV_CAP_SHUTDOWN_PORT_SHIFT                    1
0092     /* Abilty to support port active event */
0093 #define QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT_MASK         0x1
0094 #define QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT_SHIFT                2
0095     /* Abilty to support port change event */
0096 #define QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT_MASK         0x1
0097 #define QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT_SHIFT                3
0098     /* Abilty to support system image GUID */
0099 #define QED_RDMA_DEV_CAP_SYS_IMAGE_MASK                 0x1
0100 #define QED_RDMA_DEV_CAP_SYS_IMAGE_SHIFT                        4
0101     /* Abilty to support bad P_Key counter support */
0102 #define QED_RDMA_DEV_CAP_BAD_PKEY_CNT_MASK                      0x1
0103 #define QED_RDMA_DEV_CAP_BAD_PKEY_CNT_SHIFT                     5
0104     /* Abilty to support atomic operations */
0105 #define QED_RDMA_DEV_CAP_ATOMIC_OP_MASK                 0x1
0106 #define QED_RDMA_DEV_CAP_ATOMIC_OP_SHIFT                        6
0107 #define QED_RDMA_DEV_CAP_RESIZE_CQ_MASK                 0x1
0108 #define QED_RDMA_DEV_CAP_RESIZE_CQ_SHIFT                        7
0109     /* Abilty to support modifying the maximum number of
0110      * outstanding work requests per QP
0111      */
0112 #define QED_RDMA_DEV_CAP_RESIZE_MAX_WR_MASK                     0x1
0113 #define QED_RDMA_DEV_CAP_RESIZE_MAX_WR_SHIFT                    8
0114     /* Abilty to support automatic path migration */
0115 #define QED_RDMA_DEV_CAP_AUTO_PATH_MIG_MASK                     0x1
0116 #define QED_RDMA_DEV_CAP_AUTO_PATH_MIG_SHIFT                    9
0117     /* Abilty to support the base memory management extensions */
0118 #define QED_RDMA_DEV_CAP_BASE_MEMORY_EXT_MASK                   0x1
0119 #define QED_RDMA_DEV_CAP_BASE_MEMORY_EXT_SHIFT          10
0120 #define QED_RDMA_DEV_CAP_BASE_QUEUE_EXT_MASK                    0x1
0121 #define QED_RDMA_DEV_CAP_BASE_QUEUE_EXT_SHIFT                   11
0122     /* Abilty to support multipile page sizes per memory region */
0123 #define QED_RDMA_DEV_CAP_MULTI_PAGE_PER_MR_EXT_MASK             0x1
0124 #define QED_RDMA_DEV_CAP_MULTI_PAGE_PER_MR_EXT_SHIFT            12
0125     /* Abilty to support block list physical buffer list */
0126 #define QED_RDMA_DEV_CAP_BLOCK_MODE_MASK                        0x1
0127 #define QED_RDMA_DEV_CAP_BLOCK_MODE_SHIFT                       13
0128     /* Abilty to support zero based virtual addresses */
0129 #define QED_RDMA_DEV_CAP_ZBVA_MASK                              0x1
0130 #define QED_RDMA_DEV_CAP_ZBVA_SHIFT                             14
0131     /* Abilty to support local invalidate fencing */
0132 #define QED_RDMA_DEV_CAP_LOCAL_INV_FENCE_MASK                   0x1
0133 #define QED_RDMA_DEV_CAP_LOCAL_INV_FENCE_SHIFT          15
0134     /* Abilty to support Loopback on QP */
0135 #define QED_RDMA_DEV_CAP_LB_INDICATOR_MASK                      0x1
0136 #define QED_RDMA_DEV_CAP_LB_INDICATOR_SHIFT                     16
0137     u64 page_size_caps;
0138     u8 dev_ack_delay;
0139     u32 reserved_lkey;
0140     u32 bad_pkey_counter;
0141     struct qed_rdma_events events;
0142 };
0143 
0144 enum qed_port_state {
0145     QED_RDMA_PORT_UP,
0146     QED_RDMA_PORT_DOWN,
0147 };
0148 
0149 enum qed_roce_capability {
0150     QED_ROCE_V1 = 1 << 0,
0151     QED_ROCE_V2 = 1 << 1,
0152 };
0153 
0154 struct qed_rdma_port {
0155     enum qed_port_state port_state;
0156     int link_speed;
0157     u64 max_msg_size;
0158     u8 source_gid_table_len;
0159     void *source_gid_table_ptr;
0160     u8 pkey_table_len;
0161     void *pkey_table_ptr;
0162     u32 pkey_bad_counter;
0163     enum qed_roce_capability capability;
0164 };
0165 
0166 struct qed_rdma_cnq_params {
0167     u8 num_pbl_pages;
0168     u64 pbl_ptr;
0169 };
0170 
0171 /* The CQ Mode affects the CQ doorbell transaction size.
0172  * 64/32 bit machines should configure to 32/16 bits respectively.
0173  */
0174 enum qed_rdma_cq_mode {
0175     QED_RDMA_CQ_MODE_16_BITS,
0176     QED_RDMA_CQ_MODE_32_BITS,
0177 };
0178 
0179 struct qed_roce_dcqcn_params {
0180     u8 notification_point;
0181     u8 reaction_point;
0182 
0183     /* fields for notification point */
0184     u32 cnp_send_timeout;
0185 
0186     /* fields for reaction point */
0187     u32 rl_bc_rate;
0188     u16 rl_max_rate;
0189     u16 rl_r_ai;
0190     u16 rl_r_hai;
0191     u16 dcqcn_g;
0192     u32 dcqcn_k_us;
0193     u32 dcqcn_timeout_us;
0194 };
0195 
0196 struct qed_rdma_start_in_params {
0197     struct qed_rdma_events *events;
0198     struct qed_rdma_cnq_params cnq_pbl_list[128];
0199     u8 desired_cnq;
0200     enum qed_rdma_cq_mode cq_mode;
0201     struct qed_roce_dcqcn_params dcqcn_params;
0202     u16 max_mtu;
0203     u8 mac_addr[ETH_ALEN];
0204     u8 iwarp_flags;
0205 };
0206 
0207 struct qed_rdma_add_user_out_params {
0208     u16 dpi;
0209     void __iomem *dpi_addr;
0210     u64 dpi_phys_addr;
0211     u32 dpi_size;
0212     u16 wid_count;
0213 };
0214 
0215 enum roce_mode {
0216     ROCE_V1,
0217     ROCE_V2_IPV4,
0218     ROCE_V2_IPV6,
0219     MAX_ROCE_MODE
0220 };
0221 
0222 union qed_gid {
0223     u8 bytes[16];
0224     u16 words[8];
0225     u32 dwords[4];
0226     u64 qwords[2];
0227     u32 ipv4_addr;
0228 };
0229 
0230 struct qed_rdma_register_tid_in_params {
0231     u32 itid;
0232     enum qed_rdma_tid_type tid_type;
0233     u8 key;
0234     u16 pd;
0235     bool local_read;
0236     bool local_write;
0237     bool remote_read;
0238     bool remote_write;
0239     bool remote_atomic;
0240     bool mw_bind;
0241     u64 pbl_ptr;
0242     bool pbl_two_level;
0243     u8 pbl_page_size_log;
0244     u8 page_size_log;
0245     u64 length;
0246     u64 vaddr;
0247     bool phy_mr;
0248     bool dma_mr;
0249 
0250     bool dif_enabled;
0251     u64 dif_error_addr;
0252 };
0253 
0254 struct qed_rdma_create_cq_in_params {
0255     u32 cq_handle_lo;
0256     u32 cq_handle_hi;
0257     u32 cq_size;
0258     u16 dpi;
0259     bool pbl_two_level;
0260     u64 pbl_ptr;
0261     u16 pbl_num_pages;
0262     u8 pbl_page_size_log;
0263     u8 cnq_id;
0264     u16 int_timeout;
0265 };
0266 
0267 struct qed_rdma_create_srq_in_params {
0268     u64 pbl_base_addr;
0269     u64 prod_pair_addr;
0270     u16 num_pages;
0271     u16 pd_id;
0272     u16 page_size;
0273 
0274     /* XRC related only */
0275     bool reserved_key_en;
0276     bool is_xrc;
0277     u32 cq_cid;
0278     u16 xrcd_id;
0279 };
0280 
0281 struct qed_rdma_destroy_cq_in_params {
0282     u16 icid;
0283 };
0284 
0285 struct qed_rdma_destroy_cq_out_params {
0286     u16 num_cq_notif;
0287 };
0288 
0289 struct qed_rdma_create_qp_in_params {
0290     u32 qp_handle_lo;
0291     u32 qp_handle_hi;
0292     u32 qp_handle_async_lo;
0293     u32 qp_handle_async_hi;
0294     bool use_srq;
0295     bool signal_all;
0296     bool fmr_and_reserved_lkey;
0297     u16 pd;
0298     u16 dpi;
0299     u16 sq_cq_id;
0300     u16 sq_num_pages;
0301     u64 sq_pbl_ptr;
0302     u8 max_sq_sges;
0303     u16 rq_cq_id;
0304     u16 rq_num_pages;
0305     u64 rq_pbl_ptr;
0306     u16 srq_id;
0307     u16 xrcd_id;
0308     u8 stats_queue;
0309     enum qed_rdma_qp_type qp_type;
0310     u8 flags;
0311 #define QED_ROCE_EDPM_MODE_MASK      0x1
0312 #define QED_ROCE_EDPM_MODE_SHIFT     0
0313 };
0314 
0315 struct qed_rdma_create_qp_out_params {
0316     u32 qp_id;
0317     u16 icid;
0318     void *rq_pbl_virt;
0319     dma_addr_t rq_pbl_phys;
0320     void *sq_pbl_virt;
0321     dma_addr_t sq_pbl_phys;
0322 };
0323 
0324 struct qed_rdma_modify_qp_in_params {
0325     u32 modify_flags;
0326 #define QED_RDMA_MODIFY_QP_VALID_NEW_STATE_MASK               0x1
0327 #define QED_RDMA_MODIFY_QP_VALID_NEW_STATE_SHIFT              0
0328 #define QED_ROCE_MODIFY_QP_VALID_PKEY_MASK                    0x1
0329 #define QED_ROCE_MODIFY_QP_VALID_PKEY_SHIFT                   1
0330 #define QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN_MASK             0x1
0331 #define QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN_SHIFT            2
0332 #define QED_ROCE_MODIFY_QP_VALID_DEST_QP_MASK                 0x1
0333 #define QED_ROCE_MODIFY_QP_VALID_DEST_QP_SHIFT                3
0334 #define QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR_MASK          0x1
0335 #define QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR_SHIFT         4
0336 #define QED_ROCE_MODIFY_QP_VALID_RQ_PSN_MASK                  0x1
0337 #define QED_ROCE_MODIFY_QP_VALID_RQ_PSN_SHIFT                 5
0338 #define QED_ROCE_MODIFY_QP_VALID_SQ_PSN_MASK                  0x1
0339 #define QED_ROCE_MODIFY_QP_VALID_SQ_PSN_SHIFT                 6
0340 #define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ_MASK       0x1
0341 #define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ_SHIFT      7
0342 #define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP_MASK      0x1
0343 #define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP_SHIFT     8
0344 #define QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT_MASK             0x1
0345 #define QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT_SHIFT            9
0346 #define QED_ROCE_MODIFY_QP_VALID_RETRY_CNT_MASK               0x1
0347 #define QED_ROCE_MODIFY_QP_VALID_RETRY_CNT_SHIFT              10
0348 #define QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT_MASK           0x1
0349 #define QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT_SHIFT          11
0350 #define QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER_MASK       0x1
0351 #define QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER_SHIFT      12
0352 #define QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN_MASK     0x1
0353 #define QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN_SHIFT    13
0354 #define QED_ROCE_MODIFY_QP_VALID_ROCE_MODE_MASK               0x1
0355 #define QED_ROCE_MODIFY_QP_VALID_ROCE_MODE_SHIFT              14
0356 
0357     enum qed_roce_qp_state new_state;
0358     u16 pkey;
0359     bool incoming_rdma_read_en;
0360     bool incoming_rdma_write_en;
0361     bool incoming_atomic_en;
0362     bool e2e_flow_control_en;
0363     u32 dest_qp;
0364     bool lb_indication;
0365     u16 mtu;
0366     u8 traffic_class_tos;
0367     u8 hop_limit_ttl;
0368     u32 flow_label;
0369     union qed_gid sgid;
0370     union qed_gid dgid;
0371     u16 udp_src_port;
0372 
0373     u16 vlan_id;
0374 
0375     u32 rq_psn;
0376     u32 sq_psn;
0377     u8 max_rd_atomic_resp;
0378     u8 max_rd_atomic_req;
0379     u32 ack_timeout;
0380     u8 retry_cnt;
0381     u8 rnr_retry_cnt;
0382     u8 min_rnr_nak_timer;
0383     bool sqd_async;
0384     u8 remote_mac_addr[6];
0385     u8 local_mac_addr[6];
0386     bool use_local_mac;
0387     enum roce_mode roce_mode;
0388 };
0389 
0390 struct qed_rdma_query_qp_out_params {
0391     enum qed_roce_qp_state state;
0392     u32 rq_psn;
0393     u32 sq_psn;
0394     bool draining;
0395     u16 mtu;
0396     u32 dest_qp;
0397     bool incoming_rdma_read_en;
0398     bool incoming_rdma_write_en;
0399     bool incoming_atomic_en;
0400     bool e2e_flow_control_en;
0401     union qed_gid sgid;
0402     union qed_gid dgid;
0403     u32 flow_label;
0404     u8 hop_limit_ttl;
0405     u8 traffic_class_tos;
0406     u32 timeout;
0407     u8 rnr_retry;
0408     u8 retry_cnt;
0409     u8 min_rnr_nak_timer;
0410     u16 pkey_index;
0411     u8 max_rd_atomic;
0412     u8 max_dest_rd_atomic;
0413     bool sqd_async;
0414 };
0415 
0416 struct qed_rdma_create_srq_out_params {
0417     u16 srq_id;
0418 };
0419 
0420 struct qed_rdma_destroy_srq_in_params {
0421     u16 srq_id;
0422     bool is_xrc;
0423 };
0424 
0425 struct qed_rdma_modify_srq_in_params {
0426     u32 wqe_limit;
0427     u16 srq_id;
0428     bool is_xrc;
0429 };
0430 
0431 struct qed_rdma_stats_out_params {
0432     u64 sent_bytes;
0433     u64 sent_pkts;
0434     u64 rcv_bytes;
0435     u64 rcv_pkts;
0436 };
0437 
0438 struct qed_rdma_counters_out_params {
0439     u64 pd_count;
0440     u64 max_pd;
0441     u64 dpi_count;
0442     u64 max_dpi;
0443     u64 cq_count;
0444     u64 max_cq;
0445     u64 qp_count;
0446     u64 max_qp;
0447     u64 tid_count;
0448     u64 max_tid;
0449 };
0450 
0451 #define QED_ROCE_TX_HEAD_FAILURE        (1)
0452 #define QED_ROCE_TX_FRAG_FAILURE        (2)
0453 
0454 enum qed_iwarp_event_type {
0455     QED_IWARP_EVENT_MPA_REQUEST,      /* Passive side request received */
0456     QED_IWARP_EVENT_PASSIVE_COMPLETE, /* ack on mpa response */
0457     QED_IWARP_EVENT_ACTIVE_COMPLETE,  /* Active side reply received */
0458     QED_IWARP_EVENT_DISCONNECT,
0459     QED_IWARP_EVENT_CLOSE,
0460     QED_IWARP_EVENT_IRQ_FULL,
0461     QED_IWARP_EVENT_RQ_EMPTY,
0462     QED_IWARP_EVENT_LLP_TIMEOUT,
0463     QED_IWARP_EVENT_REMOTE_PROTECTION_ERROR,
0464     QED_IWARP_EVENT_CQ_OVERFLOW,
0465     QED_IWARP_EVENT_QP_CATASTROPHIC,
0466     QED_IWARP_EVENT_ACTIVE_MPA_REPLY,
0467     QED_IWARP_EVENT_LOCAL_ACCESS_ERROR,
0468     QED_IWARP_EVENT_REMOTE_OPERATION_ERROR,
0469     QED_IWARP_EVENT_TERMINATE_RECEIVED,
0470     QED_IWARP_EVENT_SRQ_LIMIT,
0471     QED_IWARP_EVENT_SRQ_EMPTY,
0472 };
0473 
0474 enum qed_tcp_ip_version {
0475     QED_TCP_IPV4,
0476     QED_TCP_IPV6,
0477 };
0478 
0479 struct qed_iwarp_cm_info {
0480     enum qed_tcp_ip_version ip_version;
0481     u32 remote_ip[4];
0482     u32 local_ip[4];
0483     u16 remote_port;
0484     u16 local_port;
0485     u16 vlan;
0486     u8 ord;
0487     u8 ird;
0488     u16 private_data_len;
0489     const void *private_data;
0490 };
0491 
0492 struct qed_iwarp_cm_event_params {
0493     enum qed_iwarp_event_type event;
0494     const struct qed_iwarp_cm_info *cm_info;
0495     void *ep_context;   /* To be passed to accept call */
0496     int status;
0497 };
0498 
0499 typedef int (*iwarp_event_handler) (void *context,
0500                     struct qed_iwarp_cm_event_params *event);
0501 
0502 struct qed_iwarp_connect_in {
0503     iwarp_event_handler event_cb;
0504     void *cb_context;
0505     struct qed_rdma_qp *qp;
0506     struct qed_iwarp_cm_info cm_info;
0507     u16 mss;
0508     u8 remote_mac_addr[ETH_ALEN];
0509     u8 local_mac_addr[ETH_ALEN];
0510 };
0511 
0512 struct qed_iwarp_connect_out {
0513     void *ep_context;
0514 };
0515 
0516 struct qed_iwarp_listen_in {
0517     iwarp_event_handler event_cb;
0518     void *cb_context;   /* passed to event_cb */
0519     u32 max_backlog;
0520     enum qed_tcp_ip_version ip_version;
0521     u32 ip_addr[4];
0522     u16 port;
0523     u16 vlan;
0524 };
0525 
0526 struct qed_iwarp_listen_out {
0527     void *handle;
0528 };
0529 
0530 struct qed_iwarp_accept_in {
0531     void *ep_context;
0532     void *cb_context;
0533     struct qed_rdma_qp *qp;
0534     const void *private_data;
0535     u16 private_data_len;
0536     u8 ord;
0537     u8 ird;
0538 };
0539 
0540 struct qed_iwarp_reject_in {
0541     void *ep_context;
0542     void *cb_context;
0543     const void *private_data;
0544     u16 private_data_len;
0545 };
0546 
0547 struct qed_iwarp_send_rtr_in {
0548     void *ep_context;
0549 };
0550 
0551 struct qed_roce_ll2_header {
0552     void *vaddr;
0553     dma_addr_t baddr;
0554     size_t len;
0555 };
0556 
0557 struct qed_roce_ll2_buffer {
0558     dma_addr_t baddr;
0559     size_t len;
0560 };
0561 
0562 struct qed_roce_ll2_packet {
0563     struct qed_roce_ll2_header header;
0564     int n_seg;
0565     struct qed_roce_ll2_buffer payload[RDMA_MAX_SGE_PER_SQ_WQE];
0566     int roce_mode;
0567     enum qed_ll2_tx_dest tx_dest;
0568 };
0569 
0570 enum qed_rdma_type {
0571     QED_RDMA_TYPE_ROCE,
0572     QED_RDMA_TYPE_IWARP
0573 };
0574 
0575 struct qed_dev_rdma_info {
0576     struct qed_dev_info common;
0577     enum qed_rdma_type rdma_type;
0578     u8 user_dpm_enabled;
0579 };
0580 
0581 struct qed_rdma_ops {
0582     const struct qed_common_ops *common;
0583 
0584     int (*fill_dev_info)(struct qed_dev *cdev,
0585                  struct qed_dev_rdma_info *info);
0586     void *(*rdma_get_rdma_ctx)(struct qed_dev *cdev);
0587 
0588     int (*rdma_init)(struct qed_dev *dev,
0589              struct qed_rdma_start_in_params *iparams);
0590 
0591     int (*rdma_add_user)(void *rdma_cxt,
0592                  struct qed_rdma_add_user_out_params *oparams);
0593 
0594     void (*rdma_remove_user)(void *rdma_cxt, u16 dpi);
0595     int (*rdma_stop)(void *rdma_cxt);
0596     struct qed_rdma_device* (*rdma_query_device)(void *rdma_cxt);
0597     struct qed_rdma_port* (*rdma_query_port)(void *rdma_cxt);
0598     int (*rdma_get_start_sb)(struct qed_dev *cdev);
0599     int (*rdma_get_min_cnq_msix)(struct qed_dev *cdev);
0600     void (*rdma_cnq_prod_update)(void *rdma_cxt, u8 cnq_index, u16 prod);
0601     int (*rdma_get_rdma_int)(struct qed_dev *cdev,
0602                  struct qed_int_info *info);
0603     int (*rdma_set_rdma_int)(struct qed_dev *cdev, u16 cnt);
0604     int (*rdma_alloc_pd)(void *rdma_cxt, u16 *pd);
0605     void (*rdma_dealloc_pd)(void *rdma_cxt, u16 pd);
0606     int (*rdma_alloc_xrcd)(void *rdma_cxt, u16 *xrcd);
0607     void (*rdma_dealloc_xrcd)(void *rdma_cxt, u16 xrcd);
0608     int (*rdma_create_cq)(void *rdma_cxt,
0609                   struct qed_rdma_create_cq_in_params *params,
0610                   u16 *icid);
0611     int (*rdma_destroy_cq)(void *rdma_cxt,
0612                    struct qed_rdma_destroy_cq_in_params *iparams,
0613                    struct qed_rdma_destroy_cq_out_params *oparams);
0614     struct qed_rdma_qp *
0615     (*rdma_create_qp)(void *rdma_cxt,
0616               struct qed_rdma_create_qp_in_params *iparams,
0617               struct qed_rdma_create_qp_out_params *oparams);
0618 
0619     int (*rdma_modify_qp)(void *roce_cxt, struct qed_rdma_qp *qp,
0620                   struct qed_rdma_modify_qp_in_params *iparams);
0621 
0622     int (*rdma_query_qp)(void *rdma_cxt, struct qed_rdma_qp *qp,
0623                  struct qed_rdma_query_qp_out_params *oparams);
0624     int (*rdma_destroy_qp)(void *rdma_cxt, struct qed_rdma_qp *qp);
0625 
0626     int
0627     (*rdma_register_tid)(void *rdma_cxt,
0628                  struct qed_rdma_register_tid_in_params *iparams);
0629 
0630     int (*rdma_deregister_tid)(void *rdma_cxt, u32 itid);
0631     int (*rdma_alloc_tid)(void *rdma_cxt, u32 *itid);
0632     void (*rdma_free_tid)(void *rdma_cxt, u32 itid);
0633 
0634     int (*rdma_create_srq)(void *rdma_cxt,
0635                    struct qed_rdma_create_srq_in_params *iparams,
0636                    struct qed_rdma_create_srq_out_params *oparams);
0637     int (*rdma_destroy_srq)(void *rdma_cxt,
0638                 struct qed_rdma_destroy_srq_in_params *iparams);
0639     int (*rdma_modify_srq)(void *rdma_cxt,
0640                    struct qed_rdma_modify_srq_in_params *iparams);
0641 
0642     int (*ll2_acquire_connection)(void *rdma_cxt,
0643                       struct qed_ll2_acquire_data *data);
0644 
0645     int (*ll2_establish_connection)(void *rdma_cxt, u8 connection_handle);
0646     int (*ll2_terminate_connection)(void *rdma_cxt, u8 connection_handle);
0647     void (*ll2_release_connection)(void *rdma_cxt, u8 connection_handle);
0648 
0649     int (*ll2_prepare_tx_packet)(void *rdma_cxt,
0650                      u8 connection_handle,
0651                      struct qed_ll2_tx_pkt_info *pkt,
0652                      bool notify_fw);
0653 
0654     int (*ll2_set_fragment_of_tx_packet)(void *rdma_cxt,
0655                          u8 connection_handle,
0656                          dma_addr_t addr,
0657                          u16 nbytes);
0658     int (*ll2_post_rx_buffer)(void *rdma_cxt, u8 connection_handle,
0659                   dma_addr_t addr, u16 buf_len, void *cookie,
0660                   u8 notify_fw);
0661     int (*ll2_get_stats)(void *rdma_cxt,
0662                  u8 connection_handle,
0663                  struct qed_ll2_stats *p_stats);
0664     int (*ll2_set_mac_filter)(struct qed_dev *cdev,
0665                   u8 *old_mac_address,
0666                   const u8 *new_mac_address);
0667 
0668     int (*iwarp_set_engine_affin)(struct qed_dev *cdev, bool b_reset);
0669 
0670     int (*iwarp_connect)(void *rdma_cxt,
0671                  struct qed_iwarp_connect_in *iparams,
0672                  struct qed_iwarp_connect_out *oparams);
0673 
0674     int (*iwarp_create_listen)(void *rdma_cxt,
0675                    struct qed_iwarp_listen_in *iparams,
0676                    struct qed_iwarp_listen_out *oparams);
0677 
0678     int (*iwarp_accept)(void *rdma_cxt,
0679                 struct qed_iwarp_accept_in *iparams);
0680 
0681     int (*iwarp_reject)(void *rdma_cxt,
0682                 struct qed_iwarp_reject_in *iparams);
0683 
0684     int (*iwarp_destroy_listen)(void *rdma_cxt, void *handle);
0685 
0686     int (*iwarp_send_rtr)(void *rdma_cxt,
0687                   struct qed_iwarp_send_rtr_in *iparams);
0688 };
0689 
0690 const struct qed_rdma_ops *qed_get_rdma_ops(void);
0691 
0692 #endif
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