linux/qed/nvmetcp_common.h

0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
0002 /* Copyright 2021 Marvell. All rights reserved. */
0003
0004 #ifndef __NVMETCP_COMMON__
0005 #define __NVMETCP_COMMON__
0006
0007 #include "tcp_common.h"
0008 #include <linux/nvme-tcp.h>
0009
0010 #define NVMETCP_SLOW_PATH_LAYER_CODE (6)
0011 #define NVMETCP_WQE_NUM_SGES_SLOWIO (0xf)
0012
0013 /* NVMeTCP firmware function init parameters */
0014 struct nvmetcp_spe_func_init {
0015     __le16 half_way_close_timeout;
0016     u8 num_sq_pages_in_ring;
0017     u8 num_r2tq_pages_in_ring;
0018     u8 num_uhq_pages_in_ring;
0019     u8 ll2_rx_queue_id;
0020     u8 flags;
0021 #define NVMETCP_SPE_FUNC_INIT_COUNTERS_EN_MASK 0x1
0022 #define NVMETCP_SPE_FUNC_INIT_COUNTERS_EN_SHIFT 0
0023 #define NVMETCP_SPE_FUNC_INIT_NVMETCP_MODE_MASK 0x1
0024 #define NVMETCP_SPE_FUNC_INIT_NVMETCP_MODE_SHIFT 1
0025 #define NVMETCP_SPE_FUNC_INIT_RESERVED0_MASK 0x3F
0026 #define NVMETCP_SPE_FUNC_INIT_RESERVED0_SHIFT 2
0027     u8 debug_flags;
0028     __le16 reserved1;
0029     u8 params;
0030 #define NVMETCP_SPE_FUNC_INIT_MAX_SYN_RT_MASK   0xF
0031 #define NVMETCP_SPE_FUNC_INIT_MAX_SYN_RT_SHIFT  0
0032 #define NVMETCP_SPE_FUNC_INIT_RESERVED1_MASK    0xF
0033 #define NVMETCP_SPE_FUNC_INIT_RESERVED1_SHIFT   4
0034     u8 reserved2[5];
0035     struct scsi_init_func_params func_params;
0036     struct scsi_init_func_queues q_params;
0037 };
0038
0039 /* NVMeTCP init params passed by driver to FW in NVMeTCP init ramrod. */
0040 struct nvmetcp_init_ramrod_params {
0041     struct nvmetcp_spe_func_init nvmetcp_init_spe;
0042     struct tcp_init_params tcp_init;
0043 };
0044
0045 /* NVMeTCP Ramrod Command IDs */
0046 enum nvmetcp_ramrod_cmd_id {
0047     NVMETCP_RAMROD_CMD_ID_UNUSED = 0,
0048     NVMETCP_RAMROD_CMD_ID_INIT_FUNC = 1,
0049     NVMETCP_RAMROD_CMD_ID_DESTROY_FUNC = 2,
0050     NVMETCP_RAMROD_CMD_ID_OFFLOAD_CONN = 3,
0051     NVMETCP_RAMROD_CMD_ID_UPDATE_CONN = 4,
0052     NVMETCP_RAMROD_CMD_ID_TERMINATION_CONN = 5,
0053     NVMETCP_RAMROD_CMD_ID_CLEAR_SQ = 6,
0054     MAX_NVMETCP_RAMROD_CMD_ID
0055 };
0056
0057 struct nvmetcp_glbl_queue_entry {
0058     struct regpair cq_pbl_addr;
0059     struct regpair reserved;
0060 };
0061
0062 /* NVMeTCP conn level EQEs */
0063 enum nvmetcp_eqe_opcode {
0064     NVMETCP_EVENT_TYPE_INIT_FUNC = 0, /* Response after init Ramrod */
0065     NVMETCP_EVENT_TYPE_DESTROY_FUNC, /* Response after destroy Ramrod */
0066     NVMETCP_EVENT_TYPE_OFFLOAD_CONN,/* Response after option 2 offload Ramrod */
0067     NVMETCP_EVENT_TYPE_UPDATE_CONN, /* Response after update Ramrod */
0068     NVMETCP_EVENT_TYPE_CLEAR_SQ, /* Response after clear sq Ramrod */
0069     NVMETCP_EVENT_TYPE_TERMINATE_CONN, /* Response after termination Ramrod */
0070     NVMETCP_EVENT_TYPE_RESERVED0,
0071     NVMETCP_EVENT_TYPE_RESERVED1,
0072     NVMETCP_EVENT_TYPE_ASYN_CONNECT_COMPLETE, /* Connect completed (A-syn EQE) */
0073     NVMETCP_EVENT_TYPE_ASYN_TERMINATE_DONE, /* Termination completed (A-syn EQE) */
0074     NVMETCP_EVENT_TYPE_START_OF_ERROR_TYPES = 10, /* Separate EQs from err EQs */
0075     NVMETCP_EVENT_TYPE_ASYN_ABORT_RCVD, /* TCP RST packet receive (A-syn EQE) */
0076     NVMETCP_EVENT_TYPE_ASYN_CLOSE_RCVD, /* TCP FIN packet receive (A-syn EQE) */
0077     NVMETCP_EVENT_TYPE_ASYN_SYN_RCVD, /* TCP SYN+ACK packet receive (A-syn EQE) */
0078     NVMETCP_EVENT_TYPE_ASYN_MAX_RT_TIME, /* TCP max retransmit time (A-syn EQE) */
0079     NVMETCP_EVENT_TYPE_ASYN_MAX_RT_CNT, /* TCP max retransmit count (A-syn EQE) */
0080     NVMETCP_EVENT_TYPE_ASYN_MAX_KA_PROBES_CNT, /* TCP ka probes count (A-syn EQE) */
0081     NVMETCP_EVENT_TYPE_ASYN_FIN_WAIT2, /* TCP fin wait 2 (A-syn EQE) */
0082     NVMETCP_EVENT_TYPE_NVMETCP_CONN_ERROR, /* NVMeTCP error response (A-syn EQE) */
0083     NVMETCP_EVENT_TYPE_TCP_CONN_ERROR, /* NVMeTCP error - tcp error (A-syn EQE) */
0084     MAX_NVMETCP_EQE_OPCODE
0085 };
0086
0087 struct nvmetcp_conn_offload_section {
0088     struct regpair cccid_itid_table_addr; /* CCCID to iTID table address */
0089     __le16 cccid_max_range; /* CCCID max value - used for validation */
0090     __le16 reserved[3];
0091 };
0092
0093 /* NVMe TCP connection offload params passed by driver to FW in NVMeTCP offload ramrod */
0094 struct nvmetcp_conn_offload_params {
0095     struct regpair sq_pbl_addr;
0096     struct regpair r2tq_pbl_addr;
0097     struct regpair xhq_pbl_addr;
0098     struct regpair uhq_pbl_addr;
0099     __le16 physical_q0;
0100     __le16 physical_q1;
0101     u8 flags;
0102 #define NVMETCP_CONN_OFFLOAD_PARAMS_TCP_ON_CHIP_1B_MASK 0x1
0103 #define NVMETCP_CONN_OFFLOAD_PARAMS_TCP_ON_CHIP_1B_SHIFT 0
0104 #define NVMETCP_CONN_OFFLOAD_PARAMS_TARGET_MODE_MASK 0x1
0105 #define NVMETCP_CONN_OFFLOAD_PARAMS_TARGET_MODE_SHIFT 1
0106 #define NVMETCP_CONN_OFFLOAD_PARAMS_RESTRICTED_MODE_MASK 0x1
0107 #define NVMETCP_CONN_OFFLOAD_PARAMS_RESTRICTED_MODE_SHIFT 2
0108 #define NVMETCP_CONN_OFFLOAD_PARAMS_NVMETCP_MODE_MASK 0x1
0109 #define NVMETCP_CONN_OFFLOAD_PARAMS_NVMETCP_MODE_SHIFT 3
0110 #define NVMETCP_CONN_OFFLOAD_PARAMS_RESERVED1_MASK 0xF
0111 #define NVMETCP_CONN_OFFLOAD_PARAMS_RESERVED1_SHIFT 4
0112     u8 default_cq;
0113     __le16 reserved0;
0114     __le32 reserved1;
0115     __le32 initial_ack;
0116
0117     struct nvmetcp_conn_offload_section nvmetcp; /* NVMe/TCP section */
0118 };
0119
0120 /* NVMe TCP and TCP connection offload params passed by driver to FW in NVMeTCP offload ramrod. */
0121 struct nvmetcp_spe_conn_offload {
0122     __le16 reserved;
0123     __le16 conn_id;
0124     __le32 fw_cid;
0125     struct nvmetcp_conn_offload_params nvmetcp;
0126     struct tcp_offload_params_opt2 tcp;
0127 };
0128
0129 /* NVMeTCP connection update params passed by driver to FW in NVMETCP update ramrod. */
0130 struct nvmetcp_conn_update_ramrod_params {
0131     __le16 reserved0;
0132     __le16 conn_id;
0133     __le32 reserved1;
0134     u8 flags;
0135 #define NVMETCP_CONN_UPDATE_RAMROD_PARAMS_HD_EN_MASK 0x1
0136 #define NVMETCP_CONN_UPDATE_RAMROD_PARAMS_HD_EN_SHIFT 0
0137 #define NVMETCP_CONN_UPDATE_RAMROD_PARAMS_DD_EN_MASK 0x1
0138 #define NVMETCP_CONN_UPDATE_RAMROD_PARAMS_DD_EN_SHIFT 1
0139 #define NVMETCP_CONN_UPDATE_RAMROD_PARAMS_RESERVED0_MASK 0x1
0140 #define NVMETCP_CONN_UPDATE_RAMROD_PARAMS_RESERVED0_SHIFT 2
0141 #define NVMETCP_CONN_UPDATE_RAMROD_PARAMS_RESERVED1_MASK 0x1
0142 #define NVMETCP_CONN_UPDATE_RAMROD_PARAMS_RESERVED1_DATA_SHIFT 3
0143 #define NVMETCP_CONN_UPDATE_RAMROD_PARAMS_RESERVED2_MASK 0x1
0144 #define NVMETCP_CONN_UPDATE_RAMROD_PARAMS_RESERVED2_SHIFT 4
0145 #define NVMETCP_CONN_UPDATE_RAMROD_PARAMS_RESERVED3_MASK 0x1
0146 #define NVMETCP_CONN_UPDATE_RAMROD_PARAMS_RESERVED3_SHIFT 5
0147 #define NVMETCP_CONN_UPDATE_RAMROD_PARAMS_RESERVED4_MASK 0x1
0148 #define NVMETCP_CONN_UPDATE_RAMROD_PARAMS_RESERVED4_SHIFT 6
0149 #define NVMETCP_CONN_UPDATE_RAMROD_PARAMS_RESERVED5_MASK 0x1
0150 #define NVMETCP_CONN_UPDATE_RAMROD_PARAMS_RESERVED5_SHIFT 7
0151     u8 reserved3[3];
0152     __le32 max_seq_size;
0153     __le32 max_send_pdu_length;
0154     __le32 max_recv_pdu_length;
0155     __le32 first_seq_length;
0156     __le32 reserved4[5];
0157 };
0158
0159 /* NVMeTCP connection termination request */
0160 struct nvmetcp_spe_conn_termination {
0161     __le16 reserved0;
0162     __le16 conn_id;
0163     __le32 reserved1;
0164     u8 abortive;
0165     u8 reserved2[7];
0166     struct regpair reserved3;
0167     struct regpair reserved4;
0168 };
0169
0170 struct nvmetcp_dif_flags {
0171     u8 flags;
0172 };
0173
0174 enum nvmetcp_wqe_type {
0175     NVMETCP_WQE_TYPE_NORMAL,
0176     NVMETCP_WQE_TYPE_TASK_CLEANUP,
0177     NVMETCP_WQE_TYPE_MIDDLE_PATH,
0178     NVMETCP_WQE_TYPE_IC,
0179     MAX_NVMETCP_WQE_TYPE
0180 };
0181
0182 struct nvmetcp_wqe {
0183     __le16 task_id;
0184     u8 flags;
0185 #define NVMETCP_WQE_WQE_TYPE_MASK 0x7 /* [use nvmetcp_wqe_type] */
0186 #define NVMETCP_WQE_WQE_TYPE_SHIFT 0
0187 #define NVMETCP_WQE_NUM_SGES_MASK 0xF
0188 #define NVMETCP_WQE_NUM_SGES_SHIFT 3
0189 #define NVMETCP_WQE_RESPONSE_MASK 0x1
0190 #define NVMETCP_WQE_RESPONSE_SHIFT 7
0191     struct nvmetcp_dif_flags prot_flags;
0192     __le32 contlen_cdbsize;
0193 #define NVMETCP_WQE_CONT_LEN_MASK 0xFFFFFF
0194 #define NVMETCP_WQE_CONT_LEN_SHIFT 0
0195 #define NVMETCP_WQE_CDB_SIZE_OR_NVMETCP_CMD_MASK 0xFF
0196 #define NVMETCP_WQE_CDB_SIZE_OR_NVMETCP_CMD_SHIFT 24
0197 };
0198
0199 struct nvmetcp_host_cccid_itid_entry {
0200     __le16 itid;
0201 };
0202
0203 struct nvmetcp_connect_done_results {
0204     __le16 icid;
0205     __le16 conn_id;
0206     struct tcp_ulp_connect_done_params params;
0207 };
0208
0209 struct nvmetcp_eqe_data {
0210     __le16 icid;
0211     __le16 conn_id;
0212     __le16 reserved;
0213     u8 error_code;
0214     u8 error_pdu_opcode_reserved;
0215 #define NVMETCP_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F
0216 #define NVMETCP_EQE_DATA_ERROR_PDU_OPCODE_SHIFT  0
0217 #define NVMETCP_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK  0x1
0218 #define NVMETCP_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT  6
0219 #define NVMETCP_EQE_DATA_RESERVED0_MASK 0x1
0220 #define NVMETCP_EQE_DATA_RESERVED0_SHIFT 7
0221 };
0222
0223 enum nvmetcp_task_type {
0224     NVMETCP_TASK_TYPE_HOST_WRITE,
0225     NVMETCP_TASK_TYPE_HOST_READ,
0226     NVMETCP_TASK_TYPE_INIT_CONN_REQUEST,
0227     NVMETCP_TASK_TYPE_RESERVED0,
0228     NVMETCP_TASK_TYPE_CLEANUP,
0229     NVMETCP_TASK_TYPE_HOST_READ_NO_CQE,
0230     MAX_NVMETCP_TASK_TYPE
0231 };
0232
0233 struct nvmetcp_db_data {
0234     u8 params;
0235 #define NVMETCP_DB_DATA_DEST_MASK 0x3 /* destination of doorbell (use enum db_dest) */
0236 #define NVMETCP_DB_DATA_DEST_SHIFT 0
0237 #define NVMETCP_DB_DATA_AGG_CMD_MASK 0x3 /* aggregative command to CM (use enum db_agg_cmd_sel) */
0238 #define NVMETCP_DB_DATA_AGG_CMD_SHIFT 2
0239 #define NVMETCP_DB_DATA_BYPASS_EN_MASK 0x1 /* enable QM bypass */
0240 #define NVMETCP_DB_DATA_BYPASS_EN_SHIFT 4
0241 #define NVMETCP_DB_DATA_RESERVED_MASK 0x1
0242 #define NVMETCP_DB_DATA_RESERVED_SHIFT 5
0243 #define NVMETCP_DB_DATA_AGG_VAL_SEL_MASK 0x3 /* aggregative value selection */
0244 #define NVMETCP_DB_DATA_AGG_VAL_SEL_SHIFT 6
0245     u8 agg_flags; /* bit for every DQ counter flags in CM context that DQ can increment */
0246     __le16 sq_prod;
0247 };
0248
0249 struct nvmetcp_fw_nvmf_cqe {
0250     __le32 reserved[4];
0251 };
0252
0253 struct nvmetcp_icresp_mdata {
0254     u8  digest;
0255     u8  cpda;
0256     __le16  pfv;
0257     __le32 maxdata;
0258     __le16 rsvd[4];
0259 };
0260
0261 union nvmetcp_fw_cqe_data {
0262     struct nvmetcp_fw_nvmf_cqe nvme_cqe;
0263     struct nvmetcp_icresp_mdata icresp_mdata;
0264 };
0265
0266 struct nvmetcp_fw_cqe {
0267     __le16 conn_id;
0268     u8 cqe_type;
0269     u8 cqe_error_status_bits;
0270 #define CQE_ERROR_BITMAP_DIF_ERR_BITS_MASK 0x7
0271 #define CQE_ERROR_BITMAP_DIF_ERR_BITS_SHIFT 0
0272 #define CQE_ERROR_BITMAP_DATA_DIGEST_ERR_MASK 0x1
0273 #define CQE_ERROR_BITMAP_DATA_DIGEST_ERR_SHIFT 3
0274 #define CQE_ERROR_BITMAP_RCV_ON_INVALID_CONN_MASK 0x1
0275 #define CQE_ERROR_BITMAP_RCV_ON_INVALID_CONN_SHIFT 4
0276     __le16 itid;
0277     u8 task_type;
0278     u8 fw_dbg_field;
0279     u8 caused_conn_err;
0280     u8 reserved0[3];
0281     __le32 reserved1;
0282     union nvmetcp_fw_cqe_data cqe_data;
0283     struct regpair task_opaque;
0284     __le32 reserved[6];
0285 };
0286
0287 enum nvmetcp_fw_cqes_type {
0288     NVMETCP_FW_CQE_TYPE_NORMAL = 1,
0289     NVMETCP_FW_CQE_TYPE_RESERVED0,
0290     NVMETCP_FW_CQE_TYPE_RESERVED1,
0291     NVMETCP_FW_CQE_TYPE_CLEANUP,
0292     NVMETCP_FW_CQE_TYPE_DUMMY,
0293     MAX_NVMETCP_FW_CQES_TYPE
0294 };
0295
0296 struct ystorm_nvmetcp_task_state {
0297     struct scsi_cached_sges data_desc;
0298     struct scsi_sgl_params sgl_params;
0299     __le32 resrved0;
0300     __le32 buffer_offset;
0301     __le16 cccid;
0302     struct nvmetcp_dif_flags dif_flags;
0303     u8 flags;
0304 #define YSTORM_NVMETCP_TASK_STATE_LOCAL_COMP_MASK 0x1
0305 #define YSTORM_NVMETCP_TASK_STATE_LOCAL_COMP_SHIFT 0
0306 #define YSTORM_NVMETCP_TASK_STATE_SLOW_IO_MASK 0x1
0307 #define YSTORM_NVMETCP_TASK_STATE_SLOW_IO_SHIFT 1
0308 #define YSTORM_NVMETCP_TASK_STATE_SET_DIF_OFFSET_MASK 0x1
0309 #define YSTORM_NVMETCP_TASK_STATE_SET_DIF_OFFSET_SHIFT 2
0310 #define YSTORM_NVMETCP_TASK_STATE_SEND_W_RSP_MASK 0x1
0311 #define YSTORM_NVMETCP_TASK_STATE_SEND_W_RSP_SHIFT 3
0312 };
0313
0314 struct ystorm_nvmetcp_task_rxmit_opt {
0315     __le32 reserved[4];
0316 };
0317
0318 struct nvmetcp_task_hdr {
0319     __le32 reg[18];
0320 };
0321
0322 struct nvmetcp_task_hdr_aligned {
0323     struct nvmetcp_task_hdr task_hdr;
0324     __le32 reserved[2]; /* HSI_COMMENT: Align to QREG */
0325 };
0326
0327 struct e5_tdif_task_context {
0328     __le32 reserved[16];
0329 };
0330
0331 struct e5_rdif_task_context {
0332     __le32 reserved[12];
0333 };
0334
0335 struct ystorm_nvmetcp_task_st_ctx {
0336     struct ystorm_nvmetcp_task_state state;
0337     struct ystorm_nvmetcp_task_rxmit_opt rxmit_opt;
0338     struct nvmetcp_task_hdr_aligned pdu_hdr;
0339 };
0340
0341 struct mstorm_nvmetcp_task_st_ctx {
0342     struct scsi_cached_sges data_desc;
0343     struct scsi_sgl_params sgl_params;
0344     __le32 rem_task_size;
0345     __le32 data_buffer_offset;
0346     u8 task_type;
0347     struct nvmetcp_dif_flags dif_flags;
0348     __le16 dif_task_icid;
0349     struct regpair reserved0;
0350     __le32 expected_itt;
0351     __le32 reserved1;
0352 };
0353
0354 struct ustorm_nvmetcp_task_st_ctx {
0355     __le32 rem_rcv_len;
0356     __le32 exp_data_transfer_len;
0357     __le32 exp_data_sn;
0358     struct regpair reserved0;
0359     __le32 reg1_map;
0360 #define REG1_NUM_SGES_MASK 0xF
0361 #define REG1_NUM_SGES_SHIFT 0
0362 #define REG1_RESERVED1_MASK 0xFFFFFFF
0363 #define REG1_RESERVED1_SHIFT 4
0364     u8 flags2;
0365 #define USTORM_NVMETCP_TASK_ST_CTX_AHS_EXIST_MASK 0x1
0366 #define USTORM_NVMETCP_TASK_ST_CTX_AHS_EXIST_SHIFT 0
0367 #define USTORM_NVMETCP_TASK_ST_CTX_RESERVED1_MASK 0x7F
0368 #define USTORM_NVMETCP_TASK_ST_CTX_RESERVED1_SHIFT 1
0369     struct nvmetcp_dif_flags dif_flags;
0370     __le16 reserved3;
0371     __le16 tqe_opaque[2];
0372     __le32 reserved5;
0373     __le32 nvme_tcp_opaque_lo;
0374     __le32 nvme_tcp_opaque_hi;
0375     u8 task_type;
0376     u8 error_flags;
0377 #define USTORM_NVMETCP_TASK_ST_CTX_DATA_DIGEST_ERROR_MASK 0x1
0378 #define USTORM_NVMETCP_TASK_ST_CTX_DATA_DIGEST_ERROR_SHIFT 0
0379 #define USTORM_NVMETCP_TASK_ST_CTX_DATA_TRUNCATED_ERROR_MASK 0x1
0380 #define USTORM_NVMETCP_TASK_ST_CTX_DATA_TRUNCATED_ERROR_SHIFT 1
0381 #define USTORM_NVMETCP_TASK_ST_CTX_UNDER_RUN_ERROR_MASK 0x1
0382 #define USTORM_NVMETCP_TASK_ST_CTX_UNDER_RUN_ERROR_SHIFT 2
0383 #define USTORM_NVMETCP_TASK_ST_CTX_NVME_TCP_MASK 0x1
0384 #define USTORM_NVMETCP_TASK_ST_CTX_NVME_TCP_SHIFT 3
0385     u8 flags;
0386 #define USTORM_NVMETCP_TASK_ST_CTX_CQE_WRITE_MASK 0x3
0387 #define USTORM_NVMETCP_TASK_ST_CTX_CQE_WRITE_SHIFT 0
0388 #define USTORM_NVMETCP_TASK_ST_CTX_LOCAL_COMP_MASK 0x1
0389 #define USTORM_NVMETCP_TASK_ST_CTX_LOCAL_COMP_SHIFT 2
0390 #define USTORM_NVMETCP_TASK_ST_CTX_Q0_R2TQE_WRITE_MASK 0x1
0391 #define USTORM_NVMETCP_TASK_ST_CTX_Q0_R2TQE_WRITE_SHIFT 3
0392 #define USTORM_NVMETCP_TASK_ST_CTX_TOTAL_DATA_ACKED_DONE_MASK 0x1
0393 #define USTORM_NVMETCP_TASK_ST_CTX_TOTAL_DATA_ACKED_DONE_SHIFT 4
0394 #define USTORM_NVMETCP_TASK_ST_CTX_HQ_SCANNED_DONE_MASK 0x1
0395 #define USTORM_NVMETCP_TASK_ST_CTX_HQ_SCANNED_DONE_SHIFT 5
0396 #define USTORM_NVMETCP_TASK_ST_CTX_R2T2RECV_DONE_MASK 0x1
0397 #define USTORM_NVMETCP_TASK_ST_CTX_R2T2RECV_DONE_SHIFT 6
0398     u8 cq_rss_number;
0399 };
0400
0401 struct e5_ystorm_nvmetcp_task_ag_ctx {
0402     u8 reserved /* cdu_validation */;
0403     u8 byte1 /* state_and_core_id */;
0404     __le16 word0 /* icid */;
0405     u8 flags0;
0406     u8 flags1;
0407     u8 flags2;
0408     u8 flags3;
0409     __le32 TTT;
0410     u8 byte2;
0411     u8 byte3;
0412     u8 byte4;
0413     u8 reserved7;
0414 };
0415
0416 struct e5_mstorm_nvmetcp_task_ag_ctx {
0417     u8 cdu_validation;
0418     u8 byte1;
0419     __le16 task_cid;
0420     u8 flags0;
0421 #define E5_MSTORM_NVMETCP_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
0422 #define E5_MSTORM_NVMETCP_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
0423 #define E5_MSTORM_NVMETCP_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
0424 #define E5_MSTORM_NVMETCP_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
0425 #define E5_MSTORM_NVMETCP_TASK_AG_CTX_CONN_CLEAR_SQ_FLAG_MASK 0x1
0426 #define E5_MSTORM_NVMETCP_TASK_AG_CTX_CONN_CLEAR_SQ_FLAG_SHIFT 5
0427 #define E5_MSTORM_NVMETCP_TASK_AG_CTX_VALID_MASK 0x1
0428 #define E5_MSTORM_NVMETCP_TASK_AG_CTX_VALID_SHIFT 6
0429 #define E5_MSTORM_NVMETCP_TASK_AG_CTX_TASK_CLEANUP_FLAG_MASK 0x1
0430 #define E5_MSTORM_NVMETCP_TASK_AG_CTX_TASK_CLEANUP_FLAG_SHIFT 7
0431     u8 flags1;
0432 #define E5_MSTORM_NVMETCP_TASK_AG_CTX_TASK_CLEANUP_CF_MASK 0x3
0433 #define E5_MSTORM_NVMETCP_TASK_AG_CTX_TASK_CLEANUP_CF_SHIFT 0
0434 #define E5_MSTORM_NVMETCP_TASK_AG_CTX_CF1_MASK 0x3
0435 #define E5_MSTORM_NVMETCP_TASK_AG_CTX_CF1_SHIFT 2
0436 #define E5_MSTORM_NVMETCP_TASK_AG_CTX_CF2_MASK 0x3
0437 #define E5_MSTORM_NVMETCP_TASK_AG_CTX_CF2_SHIFT 4
0438 #define E5_MSTORM_NVMETCP_TASK_AG_CTX_TASK_CLEANUP_CF_EN_MASK 0x1
0439 #define E5_MSTORM_NVMETCP_TASK_AG_CTX_TASK_CLEANUP_CF_EN_SHIFT 6
0440 #define E5_MSTORM_NVMETCP_TASK_AG_CTX_CF1EN_MASK 0x1
0441 #define E5_MSTORM_NVMETCP_TASK_AG_CTX_CF1EN_SHIFT 7
0442     u8 flags2;
0443     u8 flags3;
0444     __le32 reg0;
0445     u8 byte2;
0446     u8 byte3;
0447     u8 byte4;
0448     u8 reserved7;
0449 };
0450
0451 struct e5_ustorm_nvmetcp_task_ag_ctx {
0452     u8 reserved;
0453     u8 state_and_core_id;
0454     __le16 icid;
0455     u8 flags0;
0456 #define E5_USTORM_NVMETCP_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
0457 #define E5_USTORM_NVMETCP_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
0458 #define E5_USTORM_NVMETCP_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
0459 #define E5_USTORM_NVMETCP_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
0460 #define E5_USTORM_NVMETCP_TASK_AG_CTX_CONN_CLEAR_SQ_FLAG_MASK 0x1
0461 #define E5_USTORM_NVMETCP_TASK_AG_CTX_CONN_CLEAR_SQ_FLAG_SHIFT 5
0462 #define E5_USTORM_NVMETCP_TASK_AG_CTX_HQ_SCANNED_CF_MASK 0x3
0463 #define E5_USTORM_NVMETCP_TASK_AG_CTX_HQ_SCANNED_CF_SHIFT 6
0464     u8 flags1;
0465 #define E5_USTORM_NVMETCP_TASK_AG_CTX_RESERVED1_MASK 0x3
0466 #define E5_USTORM_NVMETCP_TASK_AG_CTX_RESERVED1_SHIFT 0
0467 #define E5_USTORM_NVMETCP_TASK_AG_CTX_R2T2RECV_MASK 0x3
0468 #define E5_USTORM_NVMETCP_TASK_AG_CTX_R2T2RECV_SHIFT 2
0469 #define E5_USTORM_NVMETCP_TASK_AG_CTX_CF3_MASK 0x3
0470 #define E5_USTORM_NVMETCP_TASK_AG_CTX_CF3_SHIFT 4
0471 #define E5_USTORM_NVMETCP_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
0472 #define E5_USTORM_NVMETCP_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
0473     u8 flags2;
0474 #define E5_USTORM_NVMETCP_TASK_AG_CTX_HQ_SCANNED_CF_EN_MASK 0x1
0475 #define E5_USTORM_NVMETCP_TASK_AG_CTX_HQ_SCANNED_CF_EN_SHIFT 0
0476 #define E5_USTORM_NVMETCP_TASK_AG_CTX_DISABLE_DATA_ACKED_MASK 0x1
0477 #define E5_USTORM_NVMETCP_TASK_AG_CTX_DISABLE_DATA_ACKED_SHIFT 1
0478 #define E5_USTORM_NVMETCP_TASK_AG_CTX_R2T2RECV_EN_MASK 0x1
0479 #define E5_USTORM_NVMETCP_TASK_AG_CTX_R2T2RECV_EN_SHIFT 2
0480 #define E5_USTORM_NVMETCP_TASK_AG_CTX_CF3EN_MASK 0x1
0481 #define E5_USTORM_NVMETCP_TASK_AG_CTX_CF3EN_SHIFT 3
0482 #define E5_USTORM_NVMETCP_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
0483 #define E5_USTORM_NVMETCP_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
0484 #define E5_USTORM_NVMETCP_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_MASK 0x1
0485 #define E5_USTORM_NVMETCP_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_SHIFT 5
0486 #define E5_USTORM_NVMETCP_TASK_AG_CTX_RULE1EN_MASK 0x1
0487 #define E5_USTORM_NVMETCP_TASK_AG_CTX_RULE1EN_SHIFT 6
0488 #define E5_USTORM_NVMETCP_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_MASK 0x1
0489 #define E5_USTORM_NVMETCP_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_SHIFT 7
0490     u8 flags3;
0491     u8 flags4;
0492 #define E5_USTORM_NVMETCP_TASK_AG_CTX_RESERVED5_MASK 0x3
0493 #define E5_USTORM_NVMETCP_TASK_AG_CTX_RESERVED5_SHIFT 0
0494 #define E5_USTORM_NVMETCP_TASK_AG_CTX_RESERVED6_MASK 0x1
0495 #define E5_USTORM_NVMETCP_TASK_AG_CTX_RESERVED6_SHIFT 2
0496 #define E5_USTORM_NVMETCP_TASK_AG_CTX_RESERVED7_MASK 0x1
0497 #define E5_USTORM_NVMETCP_TASK_AG_CTX_RESERVED7_SHIFT 3
0498 #define E5_USTORM_NVMETCP_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
0499 #define E5_USTORM_NVMETCP_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
0500     u8 byte2;
0501     u8 byte3;
0502     u8 reserved8;
0503     __le32 dif_err_intervals;
0504     __le32 dif_error_1st_interval;
0505     __le32 rcv_cont_len;
0506     __le32 exp_cont_len;
0507     __le32 total_data_acked;
0508     __le32 exp_data_acked;
0509     __le16 word1;
0510     __le16 next_tid;
0511     __le32 hdr_residual_count;
0512     __le32 exp_r2t_sn;
0513 };
0514
0515 struct e5_nvmetcp_task_context {
0516     struct ystorm_nvmetcp_task_st_ctx ystorm_st_context;
0517     struct e5_ystorm_nvmetcp_task_ag_ctx ystorm_ag_context;
0518     struct regpair ystorm_ag_padding[2];
0519     struct e5_tdif_task_context tdif_context;
0520     struct e5_mstorm_nvmetcp_task_ag_ctx mstorm_ag_context;
0521     struct regpair mstorm_ag_padding[2];
0522     struct e5_ustorm_nvmetcp_task_ag_ctx ustorm_ag_context;
0523     struct regpair ustorm_ag_padding[2];
0524     struct mstorm_nvmetcp_task_st_ctx mstorm_st_context;
0525     struct regpair mstorm_st_padding[2];
0526     struct ustorm_nvmetcp_task_st_ctx ustorm_st_context;
0527     struct regpair ustorm_st_padding[2];
0528     struct e5_rdif_task_context rdif_context;
0529 };
0530
0531 #endif /* __NVMETCP_COMMON__*/