include/linux/qcom_scm.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved.
0003  * Copyright (C) 2015 Linaro Ltd.
0004  */
0005 #ifndef __QCOM_SCM_H
0006 #define __QCOM_SCM_H
0007
0008 #include <linux/err.h>
0009 #include <linux/types.h>
0010 #include <linux/cpumask.h>
0011
0012 #define QCOM_SCM_VERSION(major, minor)  (((major) << 16) | ((minor) & 0xFF))
0013 #define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
0014 #define QCOM_SCM_CPU_PWR_DOWN_L2_OFF    0x1
0015 #define QCOM_SCM_HDCP_MAX_REQ_CNT   5
0016
0017 struct qcom_scm_hdcp_req {
0018     u32 addr;
0019     u32 val;
0020 };
0021
0022 struct qcom_scm_vmperm {
0023     int vmid;
0024     int perm;
0025 };
0026
0027 enum qcom_scm_ocmem_client {
0028     QCOM_SCM_OCMEM_UNUSED_ID = 0x0,
0029     QCOM_SCM_OCMEM_GRAPHICS_ID,
0030     QCOM_SCM_OCMEM_VIDEO_ID,
0031     QCOM_SCM_OCMEM_LP_AUDIO_ID,
0032     QCOM_SCM_OCMEM_SENSORS_ID,
0033     QCOM_SCM_OCMEM_OTHER_OS_ID,
0034     QCOM_SCM_OCMEM_DEBUG_ID,
0035 };
0036
0037 enum qcom_scm_sec_dev_id {
0038     QCOM_SCM_MDSS_DEV_ID    = 1,
0039     QCOM_SCM_OCMEM_DEV_ID   = 5,
0040     QCOM_SCM_PCIE0_DEV_ID   = 11,
0041     QCOM_SCM_PCIE1_DEV_ID   = 12,
0042     QCOM_SCM_GFX_DEV_ID     = 18,
0043     QCOM_SCM_UFS_DEV_ID     = 19,
0044     QCOM_SCM_ICE_DEV_ID     = 20,
0045 };
0046
0047 enum qcom_scm_ice_cipher {
0048     QCOM_SCM_ICE_CIPHER_AES_128_XTS = 0,
0049     QCOM_SCM_ICE_CIPHER_AES_128_CBC = 1,
0050     QCOM_SCM_ICE_CIPHER_AES_256_XTS = 3,
0051     QCOM_SCM_ICE_CIPHER_AES_256_CBC = 4,
0052 };
0053
0054 #define QCOM_SCM_VMID_HLOS       0x3
0055 #define QCOM_SCM_VMID_MSS_MSA    0xF
0056 #define QCOM_SCM_VMID_WLAN       0x18
0057 #define QCOM_SCM_VMID_WLAN_CE    0x19
0058 #define QCOM_SCM_PERM_READ       0x4
0059 #define QCOM_SCM_PERM_WRITE      0x2
0060 #define QCOM_SCM_PERM_EXEC       0x1
0061 #define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE)
0062 #define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
0063
0064 extern bool qcom_scm_is_available(void);
0065
0066 extern int qcom_scm_set_cold_boot_addr(void *entry);
0067 extern int qcom_scm_set_warm_boot_addr(void *entry);
0068 extern void qcom_scm_cpu_power_down(u32 flags);
0069 extern int qcom_scm_set_remote_state(u32 state, u32 id);
0070
0071 struct qcom_scm_pas_metadata {
0072     void *ptr;
0073     dma_addr_t phys;
0074     ssize_t size;
0075 };
0076
0077 extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
0078                    size_t size,
0079                    struct qcom_scm_pas_metadata *ctx);
0080 void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx);
0081 extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
0082                   phys_addr_t size);
0083 extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
0084 extern int qcom_scm_pas_shutdown(u32 peripheral);
0085 extern bool qcom_scm_pas_supported(u32 peripheral);
0086
0087 extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
0088 extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
0089
0090 extern bool qcom_scm_restore_sec_cfg_available(void);
0091 extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
0092 extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
0093 extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
0094 extern int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size);
0095 extern int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
0096                       u32 cp_nonpixel_start,
0097                       u32 cp_nonpixel_size);
0098 extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
0099                    unsigned int *src,
0100                    const struct qcom_scm_vmperm *newvm,
0101                    unsigned int dest_cnt);
0102
0103 extern bool qcom_scm_ocmem_lock_available(void);
0104 extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
0105                    u32 size, u32 mode);
0106 extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset,
0107                  u32 size);
0108
0109 extern bool qcom_scm_ice_available(void);
0110 extern int qcom_scm_ice_invalidate_key(u32 index);
0111 extern int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size,
0112                 enum qcom_scm_ice_cipher cipher,
0113                 u32 data_unit_size);
0114
0115 extern bool qcom_scm_hdcp_available(void);
0116 extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
0117                  u32 *resp);
0118
0119 extern int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt);
0120 extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
0121
0122 extern int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
0123                   u64 limit_node, u32 node_id, u64 version);
0124 extern int qcom_scm_lmh_profile_change(u32 profile_id);
0125 extern bool qcom_scm_lmh_dcvsh_available(void);
0126
0127 #endif