include/linux/pxa2xx_ssp.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2003 Russell King, All Rights Reserved.
0004  *
0005  * This driver supports the following PXA CPU/SSP ports:-
0006  *
0007  *       PXA250     SSP
0008  *       PXA255     SSP, NSSP
0009  *       PXA26x     SSP, NSSP, ASSP
0010  *       PXA27x     SSP1, SSP2, SSP3
0011  *       PXA3xx     SSP1, SSP2, SSP3, SSP4
0012  */
0013
0014 #ifndef __LINUX_PXA2XX_SSP_H
0015 #define __LINUX_PXA2XX_SSP_H
0016
0017 #include <linux/bits.h>
0018 #include <linux/compiler_types.h>
0019 #include <linux/io.h>
0020 #include <linux/kconfig.h>
0021 #include <linux/list.h>
0022 #include <linux/types.h>
0023
0024 struct clk;
0025 struct device;
0026 struct device_node;
0027
0028 /*
0029  * SSP Serial Port Registers
0030  * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
0031  * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
0032  */
0033
0034 #define SSCR0       (0x00)  /* SSP Control Register 0 */
0035 #define SSCR1       (0x04)  /* SSP Control Register 1 */
0036 #define SSSR        (0x08)  /* SSP Status Register */
0037 #define SSITR       (0x0C)  /* SSP Interrupt Test Register */
0038 #define SSDR        (0x10)  /* SSP Data Write/Data Read Register */
0039
0040 #define SSTO        (0x28)  /* SSP Time Out Register */
0041 #define SSPSP       (0x2C)  /* SSP Programmable Serial Protocol */
0042 #define SSTSA       (0x30)  /* SSP Tx Timeslot Active */
0043 #define SSRSA       (0x34)  /* SSP Rx Timeslot Active */
0044 #define SSTSS       (0x38)  /* SSP Timeslot Status */
0045 #define SSACD       (0x3C)  /* SSP Audio Clock Divider */
0046 #define SSACDD      (0x40)  /* SSP Audio Clock Dither Divider */
0047
0048 /* Common PXA2xx bits first */
0049 #define SSCR0_DSS   GENMASK(3, 0)   /* Data Size Select (mask) */
0050 #define SSCR0_DataSize(x)  ((x) - 1)    /* Data Size Select [4..16] */
0051 #define SSCR0_FRF   GENMASK(5, 4)   /* FRame Format (mask) */
0052 #define SSCR0_Motorola  (0x0 << 4)  /* Motorola's Serial Peripheral Interface (SPI) */
0053 #define SSCR0_TI    (0x1 << 4)  /* Texas Instruments' Synchronous Serial Protocol (SSP) */
0054 #define SSCR0_National  (0x2 << 4)  /* National Microwire */
0055 #define SSCR0_ECS   BIT(6)      /* External clock select */
0056 #define SSCR0_SSE   BIT(7)      /* Synchronous Serial Port Enable */
0057 #define SSCR0_SCR(x)    ((x) << 8)  /* Serial Clock Rate (mask) */
0058
0059 /* PXA27x, PXA3xx */
0060 #define SSCR0_EDSS  BIT(20)     /* Extended data size select */
0061 #define SSCR0_NCS   BIT(21)     /* Network clock select */
0062 #define SSCR0_RIM   BIT(22)     /* Receive FIFO overrun interrupt mask */
0063 #define SSCR0_TUM   BIT(23)     /* Transmit FIFO underrun interrupt mask */
0064 #define SSCR0_FRDC  GENMASK(26, 24) /* Frame rate divider control (mask) */
0065 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24)  /* Time slots per frame [1..8] */
0066 #define SSCR0_FPCKE BIT(29)     /* FIFO packing enable */
0067 #define SSCR0_ACS   BIT(30)     /* Audio clock select */
0068 #define SSCR0_MOD   BIT(31)     /* Mode (normal or network) */
0069
0070 #define SSCR1_RIE   BIT(0)      /* Receive FIFO Interrupt Enable */
0071 #define SSCR1_TIE   BIT(1)      /* Transmit FIFO Interrupt Enable */
0072 #define SSCR1_LBM   BIT(2)      /* Loop-Back Mode */
0073 #define SSCR1_SPO   BIT(3)      /* Motorola SPI SSPSCLK polarity setting */
0074 #define SSCR1_SPH   BIT(4)      /* Motorola SPI SSPSCLK phase setting */
0075 #define SSCR1_MWDS  BIT(5)      /* Microwire Transmit Data Size */
0076
0077 #define SSSR_ALT_FRM_MASK   GENMASK(1, 0)   /* Masks the SFRM signal number */
0078 #define SSSR_TNF        BIT(2)      /* Transmit FIFO Not Full */
0079 #define SSSR_RNE        BIT(3)      /* Receive FIFO Not Empty */
0080 #define SSSR_BSY        BIT(4)      /* SSP Busy */
0081 #define SSSR_TFS        BIT(5)      /* Transmit FIFO Service Request */
0082 #define SSSR_RFS        BIT(6)      /* Receive FIFO Service Request */
0083 #define SSSR_ROR        BIT(7)      /* Receive FIFO Overrun */
0084
0085 #define RX_THRESH_DFLT  8
0086 #define TX_THRESH_DFLT  8
0087
0088 #define SSSR_TFL_MASK   GENMASK(11, 8)  /* Transmit FIFO Level mask */
0089 #define SSSR_RFL_MASK   GENMASK(15, 12) /* Receive FIFO Level mask */
0090
0091 #define SSCR1_TFT   GENMASK(9, 6)   /* Transmit FIFO Threshold (mask) */
0092 #define SSCR1_TxTresh(x) (((x) - 1) << 6)   /* level [1..16] */
0093 #define SSCR1_RFT   GENMASK(13, 10) /* Receive FIFO Threshold (mask) */
0094 #define SSCR1_RxTresh(x) (((x) - 1) << 10)  /* level [1..16] */
0095
0096 #define RX_THRESH_CE4100_DFLT   2
0097 #define TX_THRESH_CE4100_DFLT   2
0098
0099 #define CE4100_SSSR_TFL_MASK    GENMASK(9, 8)   /* Transmit FIFO Level mask */
0100 #define CE4100_SSSR_RFL_MASK    GENMASK(13, 12) /* Receive FIFO Level mask */
0101
0102 #define CE4100_SSCR1_TFT    GENMASK(7, 6)   /* Transmit FIFO Threshold (mask) */
0103 #define CE4100_SSCR1_TxTresh(x) (((x) - 1) << 6)    /* level [1..4] */
0104 #define CE4100_SSCR1_RFT    GENMASK(11, 10) /* Receive FIFO Threshold (mask) */
0105 #define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10)   /* level [1..4] */
0106
0107 /* Intel Quark X1000 */
0108 #define DDS_RATE        0x28         /* SSP DDS Clock Rate Register */
0109
0110 /* QUARK_X1000 SSCR0 bit definition */
0111 #define QUARK_X1000_SSCR0_DSS       GENMASK(4, 0)   /* Data Size Select (mask) */
0112 #define QUARK_X1000_SSCR0_DataSize(x)   ((x) - 1)   /* Data Size Select [4..32] */
0113 #define QUARK_X1000_SSCR0_FRF       GENMASK(6, 5)   /* FRame Format (mask) */
0114 #define QUARK_X1000_SSCR0_Motorola  (0x0 << 5)  /* Motorola's Serial Peripheral Interface (SPI) */
0115
0116 #define RX_THRESH_QUARK_X1000_DFLT  1
0117 #define TX_THRESH_QUARK_X1000_DFLT  16
0118
0119 #define QUARK_X1000_SSSR_TFL_MASK   GENMASK(12, 8)  /* Transmit FIFO Level mask */
0120 #define QUARK_X1000_SSSR_RFL_MASK   GENMASK(17, 13) /* Receive FIFO Level mask */
0121
0122 #define QUARK_X1000_SSCR1_TFT   GENMASK(10, 6)  /* Transmit FIFO Threshold (mask) */
0123 #define QUARK_X1000_SSCR1_TxTresh(x) (((x) - 1) << 6)   /* level [1..32] */
0124 #define QUARK_X1000_SSCR1_RFT   GENMASK(15, 11) /* Receive FIFO Threshold (mask) */
0125 #define QUARK_X1000_SSCR1_RxTresh(x) (((x) - 1) << 11)  /* level [1..32] */
0126 #define QUARK_X1000_SSCR1_EFWR  BIT(16)     /* Enable FIFO Write/Read */
0127 #define QUARK_X1000_SSCR1_STRF  BIT(17)     /* Select FIFO or EFWR */
0128
0129 /* Extra bits in PXA255, PXA26x and PXA27x SSP ports */
0130 #define SSCR0_TISSP     (1 << 4)    /* TI Sync Serial Protocol */
0131 #define SSCR0_PSP       (3 << 4)    /* PSP - Programmable Serial Protocol */
0132
0133 #define SSCR1_EFWR      BIT(14)     /* Enable FIFO Write/Read */
0134 #define SSCR1_STRF      BIT(15)     /* Select FIFO or EFWR */
0135 #define SSCR1_IFS       BIT(16)     /* Invert Frame Signal */
0136 #define SSCR1_PINTE     BIT(18)     /* Peripheral Trailing Byte Interrupt Enable */
0137 #define SSCR1_TINTE     BIT(19)     /* Receiver Time-out Interrupt enable */
0138 #define SSCR1_RSRE      BIT(20)     /* Receive Service Request Enable */
0139 #define SSCR1_TSRE      BIT(21)     /* Transmit Service Request Enable */
0140 #define SSCR1_TRAIL     BIT(22)     /* Trailing Byte */
0141 #define SSCR1_RWOT      BIT(23)     /* Receive Without Transmit */
0142 #define SSCR1_SFRMDIR       BIT(24)     /* Frame Direction */
0143 #define SSCR1_SCLKDIR       BIT(25)     /* Serial Bit Rate Clock Direction */
0144 #define SSCR1_ECRB      BIT(26)     /* Enable Clock request B */
0145 #define SSCR1_ECRA      BIT(27)     /* Enable Clock Request A */
0146 #define SSCR1_SCFR      BIT(28)     /* Slave Clock free Running */
0147 #define SSCR1_EBCEI     BIT(29)     /* Enable Bit Count Error interrupt */
0148 #define SSCR1_TTE       BIT(30)     /* TXD Tristate Enable */
0149 #define SSCR1_TTELP     BIT(31)     /* TXD Tristate Enable Last Phase */
0150
0151 #define SSSR_PINT       BIT(18)     /* Peripheral Trailing Byte Interrupt */
0152 #define SSSR_TINT       BIT(19)     /* Receiver Time-out Interrupt */
0153 #define SSSR_EOC        BIT(20)     /* End Of Chain */
0154 #define SSSR_TUR        BIT(21)     /* Transmit FIFO Under Run */
0155 #define SSSR_CSS        BIT(22)     /* Clock Synchronisation Status */
0156 #define SSSR_BCE        BIT(23)     /* Bit Count Error */
0157
0158 #define SSPSP_SCMODE(x)     ((x) << 0)  /* Serial Bit Rate Clock Mode */
0159 #define SSPSP_SFRMP     BIT(2)      /* Serial Frame Polarity */
0160 #define SSPSP_ETDS      BIT(3)      /* End of Transfer data State */
0161 #define SSPSP_STRTDLY(x)    ((x) << 4)  /* Start Delay */
0162 #define SSPSP_DMYSTRT(x)    ((x) << 7)  /* Dummy Start */
0163 #define SSPSP_SFRMDLY(x)    ((x) << 9)  /* Serial Frame Delay */
0164 #define SSPSP_SFRMWDTH(x)   ((x) << 16) /* Serial Frame Width */
0165 #define SSPSP_DMYSTOP(x)    ((x) << 23) /* Dummy Stop */
0166 #define SSPSP_FSRT      BIT(25)     /* Frame Sync Relative Timing */
0167
0168 /* PXA3xx */
0169 #define SSPSP_EDMYSTRT(x)   ((x) << 26)     /* Extended Dummy Start */
0170 #define SSPSP_EDMYSTOP(x)   ((x) << 28)     /* Extended Dummy Stop */
0171 #define SSPSP_TIMING_MASK   (0x7f8001f0)
0172
0173 #define SSACD_ACDS(x)       ((x) << 0)  /* Audio clock divider select */
0174 #define SSACD_ACDS_1        (0)
0175 #define SSACD_ACDS_2        (1)
0176 #define SSACD_ACDS_4        (2)
0177 #define SSACD_ACDS_8        (3)
0178 #define SSACD_ACDS_16       (4)
0179 #define SSACD_ACDS_32       (5)
0180 #define SSACD_SCDB      BIT(3)      /* SSPSYSCLK Divider Bypass */
0181 #define SSACD_SCDB_4X       (0)
0182 #define SSACD_SCDB_1X       (1)
0183 #define SSACD_ACPS(x)       ((x) << 4)  /* Audio clock PLL select */
0184 #define SSACD_SCDX8     BIT(7)      /* SYSCLK division ratio select */
0185
0186 /* Intel Merrifield SSP */
0187 #define SFIFOL          0x68        /* FIFO level */
0188 #define SFIFOTT         0x6c        /* FIFO trigger threshold */
0189
0190 #define RX_THRESH_MRFLD_DFLT    16
0191 #define TX_THRESH_MRFLD_DFLT    16
0192
0193 #define SFIFOL_TFL_MASK     GENMASK(15, 0)  /* Transmit FIFO Level mask */
0194 #define SFIFOL_RFL_MASK     GENMASK(31, 16) /* Receive FIFO Level mask */
0195
0196 #define SFIFOTT_TFT     GENMASK(15, 0)  /* Transmit FIFO Threshold (mask) */
0197 #define SFIFOTT_TxThresh(x) (((x) - 1) << 0)    /* TX FIFO trigger threshold / level */
0198 #define SFIFOTT_RFT     GENMASK(31, 16) /* Receive FIFO Threshold (mask) */
0199 #define SFIFOTT_RxThresh(x) (((x) - 1) << 16)   /* RX FIFO trigger threshold / level */
0200
0201 /* LPSS SSP */
0202 #define SSITF           0x44        /* TX FIFO trigger level */
0203 #define SSITF_TxHiThresh(x) (((x) - 1) << 0)
0204 #define SSITF_TxLoThresh(x) (((x) - 1) << 8)
0205
0206 #define SSIRF           0x48        /* RX FIFO trigger level */
0207 #define SSIRF_RxThresh(x)   ((x) - 1)
0208
0209 /* LPT/WPT SSP */
0210 #define SSCR2       (0x40)  /* SSP Command / Status 2 */
0211 #define SSPSP2      (0x44)  /* SSP Programmable Serial Protocol 2 */
0212
0213 enum pxa_ssp_type {
0214     SSP_UNDEFINED = 0,
0215     PXA25x_SSP,  /* pxa 210, 250, 255, 26x */
0216     PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
0217     PXA27x_SSP,
0218     PXA3xx_SSP,
0219     PXA168_SSP,
0220     MMP2_SSP,
0221     PXA910_SSP,
0222     CE4100_SSP,
0223     MRFLD_SSP,
0224     QUARK_X1000_SSP,
0225     /* Keep LPSS types sorted with lpss_platforms[] */
0226     LPSS_LPT_SSP,
0227     LPSS_BYT_SSP,
0228     LPSS_BSW_SSP,
0229     LPSS_SPT_SSP,
0230     LPSS_BXT_SSP,
0231     LPSS_CNL_SSP,
0232 };
0233
0234 struct ssp_device {
0235     struct device   *dev;
0236     struct list_head    node;
0237
0238     struct clk  *clk;
0239     void __iomem    *mmio_base;
0240     unsigned long   phys_base;
0241
0242     const char  *label;
0243     int     port_id;
0244     enum pxa_ssp_type type;
0245     int     use_count;
0246     int     irq;
0247
0248     struct device_node  *of_node;
0249 };
0250
0251 /**
0252  * pxa_ssp_write_reg - Write to a SSP register
0253  *
0254  * @dev: SSP device to access
0255  * @reg: Register to write to
0256  * @val: Value to be written.
0257  */
0258 static inline void pxa_ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val)
0259 {
0260     __raw_writel(val, dev->mmio_base + reg);
0261 }
0262
0263 /**
0264  * pxa_ssp_read_reg - Read from a SSP register
0265  *
0266  * @dev: SSP device to access
0267  * @reg: Register to read from
0268  */
0269 static inline u32 pxa_ssp_read_reg(struct ssp_device *dev, u32 reg)
0270 {
0271     return __raw_readl(dev->mmio_base + reg);
0272 }
0273
0274 static inline void pxa_ssp_enable(struct ssp_device *ssp)
0275 {
0276     u32 sscr0;
0277
0278     sscr0 = pxa_ssp_read_reg(ssp, SSCR0) | SSCR0_SSE;
0279     pxa_ssp_write_reg(ssp, SSCR0, sscr0);
0280 }
0281
0282 static inline void pxa_ssp_disable(struct ssp_device *ssp)
0283 {
0284     u32 sscr0;
0285
0286     sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~SSCR0_SSE;
0287     pxa_ssp_write_reg(ssp, SSCR0, sscr0);
0288 }
0289
0290 #if IS_ENABLED(CONFIG_PXA_SSP)
0291 struct ssp_device *pxa_ssp_request(int port, const char *label);
0292 void pxa_ssp_free(struct ssp_device *);
0293 struct ssp_device *pxa_ssp_request_of(const struct device_node *of_node,
0294                       const char *label);
0295 #else
0296 static inline struct ssp_device *pxa_ssp_request(int port, const char *label)
0297 {
0298     return NULL;
0299 }
0300 static inline struct ssp_device *pxa_ssp_request_of(const struct device_node *n,
0301                             const char *name)
0302 {
0303     return NULL;
0304 }
0305 static inline void pxa_ssp_free(struct ssp_device *ssp) {}
0306 #endif
0307
0308 #endif  /* __LINUX_PXA2XX_SSP_H */