linux/power/smartreflex.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * OMAP Smartreflex Defines and Routines
0004  *
0005  * Author: Thara Gopinath   <thara@ti.com>
0006  *
0007  * Copyright (C) 2010 Texas Instruments, Inc.
0008  * Thara Gopinath <thara@ti.com>
0009  *
0010  * Copyright (C) 2008 Nokia Corporation
0011  * Kalle Jokiniemi
0012  *
0013  * Copyright (C) 2007 Texas Instruments, Inc.
0014  * Lesly A M <x0080970@ti.com>
0015  */
0016
0017 #ifndef __POWER_SMARTREFLEX_H
0018 #define __POWER_SMARTREFLEX_H
0019
0020 #include <linux/types.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/delay.h>
0023 #include <linux/platform_data/voltage-omap.h>
0024
0025 /*
0026  * Different Smartreflex IPs version. The v1 is the 65nm version used in
0027  * OMAP3430. The v2 is the update for the 45nm version of the IP
0028  * used in OMAP3630 and OMAP4430
0029  */
0030 #define SR_TYPE_V1  1
0031 #define SR_TYPE_V2  2
0032
0033 /* SMART REFLEX REG ADDRESS OFFSET */
0034 #define SRCONFIG        0x00
0035 #define SRSTATUS        0x04
0036 #define SENVAL          0x08
0037 #define SENMIN          0x0C
0038 #define SENMAX          0x10
0039 #define SENAVG          0x14
0040 #define AVGWEIGHT       0x18
0041 #define NVALUERECIPROCAL    0x1c
0042 #define SENERROR_V1     0x20
0043 #define ERRCONFIG_V1        0x24
0044 #define IRQ_EOI         0x20
0045 #define IRQSTATUS_RAW       0x24
0046 #define IRQSTATUS       0x28
0047 #define IRQENABLE_SET       0x2C
0048 #define IRQENABLE_CLR       0x30
0049 #define SENERROR_V2     0x34
0050 #define ERRCONFIG_V2        0x38
0051
0052 /* Bit/Shift Positions */
0053
0054 /* SRCONFIG */
0055 #define SRCONFIG_ACCUMDATA_SHIFT    22
0056 #define SRCONFIG_SRCLKLENGTH_SHIFT  12
0057 #define SRCONFIG_SENNENABLE_V1_SHIFT    5
0058 #define SRCONFIG_SENPENABLE_V1_SHIFT    3
0059 #define SRCONFIG_SENNENABLE_V2_SHIFT    1
0060 #define SRCONFIG_SENPENABLE_V2_SHIFT    0
0061 #define SRCONFIG_CLKCTRL_SHIFT      0
0062
0063 #define SRCONFIG_ACCUMDATA_MASK     (0x3ff << 22)
0064
0065 #define SRCONFIG_SRENABLE       BIT(11)
0066 #define SRCONFIG_SENENABLE      BIT(10)
0067 #define SRCONFIG_ERRGEN_EN      BIT(9)
0068 #define SRCONFIG_MINMAXAVG_EN       BIT(8)
0069 #define SRCONFIG_DELAYCTRL      BIT(2)
0070
0071 /* AVGWEIGHT */
0072 #define AVGWEIGHT_SENPAVGWEIGHT_SHIFT   2
0073 #define AVGWEIGHT_SENNAVGWEIGHT_SHIFT   0
0074
0075 /* NVALUERECIPROCAL */
0076 #define NVALUERECIPROCAL_SENPGAIN_SHIFT 20
0077 #define NVALUERECIPROCAL_SENNGAIN_SHIFT 16
0078 #define NVALUERECIPROCAL_RNSENP_SHIFT   8
0079 #define NVALUERECIPROCAL_RNSENN_SHIFT   0
0080
0081 /* ERRCONFIG */
0082 #define ERRCONFIG_ERRWEIGHT_SHIFT   16
0083 #define ERRCONFIG_ERRMAXLIMIT_SHIFT 8
0084 #define ERRCONFIG_ERRMINLIMIT_SHIFT 0
0085
0086 #define SR_ERRWEIGHT_MASK       (0x07 << 16)
0087 #define SR_ERRMAXLIMIT_MASK     (0xff << 8)
0088 #define SR_ERRMINLIMIT_MASK     (0xff << 0)
0089
0090 #define ERRCONFIG_VPBOUNDINTEN_V1   BIT(31)
0091 #define ERRCONFIG_VPBOUNDINTST_V1   BIT(30)
0092 #define ERRCONFIG_MCUACCUMINTEN     BIT(29)
0093 #define ERRCONFIG_MCUACCUMINTST     BIT(28)
0094 #define ERRCONFIG_MCUVALIDINTEN     BIT(27)
0095 #define ERRCONFIG_MCUVALIDINTST     BIT(26)
0096 #define ERRCONFIG_MCUBOUNDINTEN     BIT(25)
0097 #define ERRCONFIG_MCUBOUNDINTST     BIT(24)
0098 #define ERRCONFIG_MCUDISACKINTEN    BIT(23)
0099 #define ERRCONFIG_VPBOUNDINTST_V2   BIT(23)
0100 #define ERRCONFIG_MCUDISACKINTST    BIT(22)
0101 #define ERRCONFIG_VPBOUNDINTEN_V2   BIT(22)
0102
0103 #define ERRCONFIG_STATUS_V1_MASK    (ERRCONFIG_VPBOUNDINTST_V1 | \
0104                     ERRCONFIG_MCUACCUMINTST | \
0105                     ERRCONFIG_MCUVALIDINTST | \
0106                     ERRCONFIG_MCUBOUNDINTST | \
0107                     ERRCONFIG_MCUDISACKINTST)
0108 /* IRQSTATUS */
0109 #define IRQSTATUS_MCUACCUMINT       BIT(3)
0110 #define IRQSTATUS_MCVALIDINT        BIT(2)
0111 #define IRQSTATUS_MCBOUNDSINT       BIT(1)
0112 #define IRQSTATUS_MCUDISABLEACKINT  BIT(0)
0113
0114 /* IRQENABLE_SET and IRQENABLE_CLEAR */
0115 #define IRQENABLE_MCUACCUMINT       BIT(3)
0116 #define IRQENABLE_MCUVALIDINT       BIT(2)
0117 #define IRQENABLE_MCUBOUNDSINT      BIT(1)
0118 #define IRQENABLE_MCUDISABLEACKINT  BIT(0)
0119
0120 /* Common Bit values */
0121
0122 #define SRCLKLENGTH_12MHZ_SYSCLK    0x3c
0123 #define SRCLKLENGTH_13MHZ_SYSCLK    0x41
0124 #define SRCLKLENGTH_19MHZ_SYSCLK    0x60
0125 #define SRCLKLENGTH_26MHZ_SYSCLK    0x82
0126 #define SRCLKLENGTH_38MHZ_SYSCLK    0xC0
0127
0128 /*
0129  * 3430 specific values. Maybe these should be passed from board file or
0130  * pmic structures.
0131  */
0132 #define OMAP3430_SR_ACCUMDATA       0x1f4
0133
0134 #define OMAP3430_SR1_SENPAVGWEIGHT  0x03
0135 #define OMAP3430_SR1_SENNAVGWEIGHT  0x03
0136
0137 #define OMAP3430_SR2_SENPAVGWEIGHT  0x01
0138 #define OMAP3430_SR2_SENNAVGWEIGHT  0x01
0139
0140 #define OMAP3430_SR_ERRWEIGHT       0x04
0141 #define OMAP3430_SR_ERRMAXLIMIT     0x02
0142
0143 enum sr_instance {
0144     OMAP_SR_MPU,            /* shared with iva on omap3 */
0145     OMAP_SR_CORE,
0146     OMAP_SR_IVA,
0147     OMAP_SR_NR,
0148 };
0149
0150 struct omap_sr {
0151     char                *name;
0152     struct list_head        node;
0153     struct platform_device      *pdev;
0154     struct omap_sr_nvalue_table *nvalue_table;
0155     struct voltagedomain        *voltdm;
0156     struct dentry           *dbg_dir;
0157     unsigned int            irq;
0158     struct clk          *fck;
0159     int             srid;
0160     int             ip_type;
0161     int             nvalue_count;
0162     bool                autocomp_active;
0163     u32             clk_length;
0164     u32             err_weight;
0165     u32             err_minlimit;
0166     u32             err_maxlimit;
0167     u32             accum_data;
0168     u32             senn_avgweight;
0169     u32             senp_avgweight;
0170     u32             senp_mod;
0171     u32             senn_mod;
0172     void __iomem            *base;
0173     unsigned long           enabled:1;
0174 };
0175
0176 /**
0177  * test_cond_timeout - busy-loop, testing a condition
0178  * @cond: condition to test until it evaluates to true
0179  * @timeout: maximum number of microseconds in the timeout
0180  * @index: loop index (integer)
0181  *
0182  * Loop waiting for @cond to become true or until at least @timeout
0183  * microseconds have passed.  To use, define some integer @index in the
0184  * calling code.  After running, if @index == @timeout, then the loop has
0185  * timed out.
0186  *
0187  * Copied from omap_test_timeout */
0188 #define sr_test_cond_timeout(cond, timeout, index)      \
0189 ({                              \
0190     for (index = 0; index < timeout; index++) {     \
0191         if (cond)                   \
0192             break;                  \
0193         udelay(1);                  \
0194     }                           \
0195 })
0196
0197 /**
0198  * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
0199  *              pmic specific info to smartreflex driver
0200  *
0201  * @sr_pmic_init:   API to initialize smartreflex on the PMIC side.
0202  */
0203 struct omap_sr_pmic_data {
0204     void (*sr_pmic_init) (void);
0205 };
0206
0207 /**
0208  * struct omap_smartreflex_dev_attr - Smartreflex Device attribute.
0209  *
0210  * @sensor_voltdm_name:       Name of voltdomain of SR instance
0211  */
0212 struct omap_smartreflex_dev_attr {
0213     const char      *sensor_voltdm_name;
0214 };
0215
0216 /*
0217  * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
0218  * The smartreflex class driver should pass the class type.
0219  * Should be used to populate the class_type field of the
0220  * omap_smartreflex_class_data structure.
0221  */
0222 #define SR_CLASS1   0x1
0223 #define SR_CLASS2   0x2
0224 #define SR_CLASS3   0x3
0225
0226 /**
0227  * struct omap_sr_class_data - Smartreflex class driver info
0228  *
0229  * @enable:     API to enable a particular class smaartreflex.
0230  * @disable:        API to disable a particular class smartreflex.
0231  * @configure:      API to configure a particular class smartreflex.
0232  * @notify:     API to notify the class driver about an event in SR.
0233  *          Not needed for class3.
0234  * @notify_flags:   specify the events to be notified to the class driver
0235  * @class_type:     specify which smartreflex class.
0236  *          Can be used by the SR driver to take any class
0237  *          based decisions.
0238  */
0239 struct omap_sr_class_data {
0240     int (*enable)(struct omap_sr *sr);
0241     int (*disable)(struct omap_sr *sr, int is_volt_reset);
0242     int (*configure)(struct omap_sr *sr);
0243     int (*notify)(struct omap_sr *sr, u32 status);
0244     u8 notify_flags;
0245     u8 class_type;
0246 };
0247
0248 /**
0249  * struct omap_sr_nvalue_table  - Smartreflex n-target value info
0250  *
0251  * @efuse_offs:   The offset of the efuse where n-target values are stored.
0252  * @nvalue:   The n-target value.
0253  * @errminlimit:  The value of the ERRMINLIMIT bitfield for this n-target
0254  * @volt_nominal: microvolts DC that the VDD is initially programmed to
0255  */
0256 struct omap_sr_nvalue_table {
0257     u32 efuse_offs;
0258     u32 nvalue;
0259     u32 errminlimit;
0260     unsigned long volt_nominal;
0261 };
0262
0263 /**
0264  * struct omap_sr_data - Smartreflex platform data.
0265  *
0266  * @name:       instance name
0267  * @ip_type:        Smartreflex IP type.
0268  * @senp_mod:       SENPENABLE value of the sr CONFIG register
0269  * @senn_mod:       SENNENABLE value for sr CONFIG register
0270  * @err_weight      ERRWEIGHT value of the sr ERRCONFIG register
0271  * @err_maxlimit    ERRMAXLIMIT value of the sr ERRCONFIG register
0272  * @accum_data      ACCUMDATA value of the sr CONFIG register
0273  * @senn_avgweight  SENNAVGWEIGHT value of the sr AVGWEIGHT register
0274  * @senp_avgweight  SENPAVGWEIGHT value of the sr AVGWEIGHT register
0275  * @nvalue_count:   Number of distinct nvalues in the nvalue table
0276  * @enable_on_init: whether this sr module needs to enabled at
0277  *          boot up or not.
0278  * @nvalue_table:   table containing the  efuse offsets and nvalues
0279  *          corresponding to them.
0280  * @voltdm:     Pointer to the voltage domain associated with the SR
0281  */
0282 struct omap_sr_data {
0283     const char          *name;
0284     int             ip_type;
0285     u32             senp_mod;
0286     u32             senn_mod;
0287     u32             err_weight;
0288     u32             err_maxlimit;
0289     u32             accum_data;
0290     u32             senn_avgweight;
0291     u32             senp_avgweight;
0292     int             nvalue_count;
0293     bool                enable_on_init;
0294     struct omap_sr_nvalue_table *nvalue_table;
0295     struct voltagedomain        *voltdm;
0296 };
0297
0298
0299 extern struct omap_sr_data omap_sr_pdata[OMAP_SR_NR];
0300
0301 #ifdef CONFIG_POWER_AVS_OMAP
0302
0303 /* Smartreflex module enable/disable interface */
0304 void omap_sr_enable(struct voltagedomain *voltdm);
0305 void omap_sr_disable(struct voltagedomain *voltdm);
0306 void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
0307
0308 /* Smartreflex driver hooks to be called from Smartreflex class driver */
0309 int sr_enable(struct omap_sr *sr, unsigned long volt);
0310 void sr_disable(struct omap_sr *sr);
0311 int sr_configure_errgen(struct omap_sr *sr);
0312 int sr_disable_errgen(struct omap_sr *sr);
0313 int sr_configure_minmax(struct omap_sr *sr);
0314
0315 /* API to register the smartreflex class driver with the smartreflex driver */
0316 int sr_register_class(struct omap_sr_class_data *class_data);
0317 #else
0318 static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
0319 static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
0320 static inline void omap_sr_disable_reset_volt(
0321         struct voltagedomain *voltdm) {}
0322 #endif
0323 #endif