0001
0002
0003
0004
0005
0006
0007
0008
0009
0010 #ifndef __MAX17042_BATTERY_H_
0011 #define __MAX17042_BATTERY_H_
0012
0013 #define MAX17042_STATUS_BattAbsent (1 << 3)
0014 #define MAX17042_BATTERY_FULL (95)
0015 #define MAX17042_DEFAULT_SNS_RESISTOR (10000)
0016 #define MAX17042_DEFAULT_VMIN (3000)
0017 #define MAX17042_DEFAULT_VMAX (4500)
0018 #define MAX17042_DEFAULT_TEMP_MIN (0)
0019 #define MAX17042_DEFAULT_TEMP_MAX (700)
0020
0021
0022 #define MAX17042_FULL_THRESHOLD 10
0023
0024 #define MAX17042_CHARACTERIZATION_DATA_SIZE 48
0025
0026 enum max17042_register {
0027 MAX17042_STATUS = 0x00,
0028 MAX17042_VALRT_Th = 0x01,
0029 MAX17042_TALRT_Th = 0x02,
0030 MAX17042_SALRT_Th = 0x03,
0031 MAX17042_AtRate = 0x04,
0032 MAX17042_RepCap = 0x05,
0033 MAX17042_RepSOC = 0x06,
0034 MAX17042_Age = 0x07,
0035 MAX17042_TEMP = 0x08,
0036 MAX17042_VCELL = 0x09,
0037 MAX17042_Current = 0x0A,
0038 MAX17042_AvgCurrent = 0x0B,
0039
0040 MAX17042_SOC = 0x0D,
0041 MAX17042_AvSOC = 0x0E,
0042 MAX17042_RemCap = 0x0F,
0043 MAX17042_FullCAP = 0x10,
0044 MAX17042_TTE = 0x11,
0045 MAX17042_V_empty = 0x12,
0046
0047 MAX17042_RSLOW = 0x14,
0048
0049 MAX17042_AvgTA = 0x16,
0050 MAX17042_Cycles = 0x17,
0051 MAX17042_DesignCap = 0x18,
0052 MAX17042_AvgVCELL = 0x19,
0053 MAX17042_MinMaxTemp = 0x1A,
0054 MAX17042_MinMaxVolt = 0x1B,
0055 MAX17042_MinMaxCurr = 0x1C,
0056 MAX17042_CONFIG = 0x1D,
0057 MAX17042_ICHGTerm = 0x1E,
0058 MAX17042_AvCap = 0x1F,
0059 MAX17042_ManName = 0x20,
0060 MAX17042_DevName = 0x21,
0061
0062 MAX17042_FullCAPNom = 0x23,
0063 MAX17042_TempNom = 0x24,
0064 MAX17042_TempLim = 0x25,
0065 MAX17042_TempHot = 0x26,
0066 MAX17042_AIN = 0x27,
0067 MAX17042_LearnCFG = 0x28,
0068 MAX17042_FilterCFG = 0x29,
0069 MAX17042_RelaxCFG = 0x2A,
0070 MAX17042_MiscCFG = 0x2B,
0071 MAX17042_TGAIN = 0x2C,
0072 MAX17042_TOFF = 0x2D,
0073 MAX17042_CGAIN = 0x2E,
0074 MAX17042_COFF = 0x2F,
0075
0076 MAX17042_MaskSOC = 0x32,
0077 MAX17042_SOC_empty = 0x33,
0078 MAX17042_T_empty = 0x34,
0079
0080 MAX17042_FullCAP0 = 0x35,
0081 MAX17042_IAvg_empty = 0x36,
0082 MAX17042_FCTC = 0x37,
0083 MAX17042_RCOMP0 = 0x38,
0084 MAX17042_TempCo = 0x39,
0085 MAX17042_EmptyTempCo = 0x3A,
0086 MAX17042_K_empty0 = 0x3B,
0087 MAX17042_TaskPeriod = 0x3C,
0088 MAX17042_FSTAT = 0x3D,
0089
0090 MAX17042_SHDNTIMER = 0x3F,
0091
0092 MAX17042_dQacc = 0x45,
0093 MAX17042_dPacc = 0x46,
0094
0095 MAX17042_VFSOC0 = 0x48,
0096
0097 MAX17042_QH = 0x4D,
0098 MAX17042_QL = 0x4E,
0099
0100 MAX17042_VFSOC0Enable = 0x60,
0101 MAX17042_MLOCKReg1 = 0x62,
0102 MAX17042_MLOCKReg2 = 0x63,
0103
0104 MAX17042_MODELChrTbl = 0x80,
0105
0106 MAX17042_OCV = 0xEE,
0107
0108 MAX17042_OCVInternal = 0xFB,
0109
0110 MAX17042_VFSOC = 0xFF,
0111 };
0112
0113
0114 enum max17055_register {
0115 MAX17055_QRes = 0x0C,
0116 MAX17055_RCell = 0x14,
0117 MAX17055_TTF = 0x20,
0118 MAX17055_DieTemp = 0x34,
0119 MAX17055_USER_MEM = 0x40,
0120 MAX17055_RGAIN = 0x43,
0121
0122 MAX17055_ConvgCfg = 0x49,
0123 MAX17055_VFRemCap = 0x4A,
0124
0125 MAX17055_STATUS2 = 0xB0,
0126 MAX17055_POWER = 0xB1,
0127 MAX17055_ID = 0xB2,
0128 MAX17055_AvgPower = 0xB3,
0129 MAX17055_IAlrtTh = 0xB4,
0130 MAX17055_TTFCfg = 0xB5,
0131 MAX17055_CVMixCap = 0xB6,
0132 MAX17055_CVHalfTime = 0xB7,
0133 MAX17055_CGTempCo = 0xB8,
0134 MAX17055_Curve = 0xB9,
0135 MAX17055_HibCfg = 0xBA,
0136 MAX17055_Config2 = 0xBB,
0137 MAX17055_VRipple = 0xBC,
0138 MAX17055_RippleCfg = 0xBD,
0139 MAX17055_TimerH = 0xBE,
0140
0141 MAX17055_RSense = 0xD0,
0142 MAX17055_ScOcvLim = 0xD1,
0143
0144 MAX17055_SOCHold = 0xD3,
0145 MAX17055_MaxPeakPwr = 0xD4,
0146 MAX17055_SusPeakPwr = 0xD5,
0147 MAX17055_PackResistance = 0xD6,
0148 MAX17055_SysResistance = 0xD7,
0149 MAX17055_MinSysV = 0xD8,
0150 MAX17055_MPPCurrent = 0xD9,
0151 MAX17055_SPPCurrent = 0xDA,
0152 MAX17055_ModelCfg = 0xDB,
0153 MAX17055_AtQResidual = 0xDC,
0154 MAX17055_AtTTE = 0xDD,
0155 MAX17055_AtAvSOC = 0xDE,
0156 MAX17055_AtAvCap = 0xDF,
0157 };
0158
0159
0160 enum max17047_register {
0161 MAX17047_QRTbl00 = 0x12,
0162 MAX17047_FullSOCThr = 0x13,
0163 MAX17047_QRTbl10 = 0x22,
0164 MAX17047_QRTbl20 = 0x32,
0165 MAX17047_V_empty = 0x3A,
0166 MAX17047_TIMER = 0x3E,
0167 MAX17047_QRTbl30 = 0x42,
0168 };
0169
0170 enum max170xx_chip_type {
0171 MAXIM_DEVICE_TYPE_UNKNOWN = 0,
0172 MAXIM_DEVICE_TYPE_MAX17042,
0173 MAXIM_DEVICE_TYPE_MAX17047,
0174 MAXIM_DEVICE_TYPE_MAX17050,
0175 MAXIM_DEVICE_TYPE_MAX17055,
0176
0177 MAXIM_DEVICE_TYPE_NUM
0178 };
0179
0180
0181
0182
0183
0184
0185 struct max17042_reg_data {
0186 u8 addr;
0187 u16 data;
0188 };
0189
0190 struct max17042_config_data {
0191
0192 u32 cur_sense_val;
0193
0194
0195 u16 tgain;
0196 u16 toff;
0197 u16 cgain;
0198 u16 coff;
0199
0200
0201 u16 valrt_thresh;
0202 u16 talrt_thresh;
0203 u16 soc_alrt_thresh;
0204 u16 config;
0205 u16 shdntimer;
0206
0207
0208 u16 full_soc_thresh;
0209 u16 design_cap;
0210 u16 ichgt_term;
0211
0212
0213 u16 at_rate;
0214 u16 learn_cfg;
0215 u16 filter_cfg;
0216 u16 relax_cfg;
0217 u16 misc_cfg;
0218 u16 masksoc;
0219
0220
0221 u16 fullcap;
0222 u16 fullcapnom;
0223 u16 socempty;
0224 u16 iavg_empty;
0225 u16 dqacc;
0226 u16 dpacc;
0227 u16 qrtbl00;
0228 u16 qrtbl10;
0229 u16 qrtbl20;
0230 u16 qrtbl30;
0231
0232
0233 u16 cell_technology;
0234
0235
0236 u16 vempty;
0237 u16 temp_nom;
0238 u16 temp_lim;
0239 u16 fctc;
0240 u16 rcomp0;
0241 u16 tcompc0;
0242 u16 empty_tempco;
0243 u16 kempty0;
0244 u16 cell_char_tbl[MAX17042_CHARACTERIZATION_DATA_SIZE];
0245 } __packed;
0246
0247 struct max17042_platform_data {
0248 struct max17042_reg_data *init_data;
0249 struct max17042_config_data *config_data;
0250 int num_init_data;
0251 bool enable_current_sense;
0252 bool enable_por_init;
0253
0254
0255
0256
0257
0258
0259 unsigned int r_sns;
0260 int vmin;
0261 int vmax;
0262 int temp_min;
0263 int temp_max;
0264 };
0265
0266 #endif